检索结果-内蒙古大学图书馆

A complex-valued time varying zeroing neural network model for synchronization of complex chaotic systems

NONLINEAR DYNAMICS 2025年第6期113卷 5471-5491页

作者： Jin, Jie Fang, Jing Chen, Chaoyang Li, Zhijing Yu, Fei Hunan Univ Sci & Technol Sanya Inst Sanya 572024 Hainan Peoples R China Hunan Univ Sci & Technol Sch Informat & Elect Engn Xiangtan 411201 Hunan Peoples R China Changsha Med Univ Sch Informat Engn Changsha 410219 Hunan Peoples R China Changsha Univ Sci & Technol Sch Comp & Commun Engn Changsha 410114 Hunan Peoples R China

Zeroing neural network (ZNN) is an effective tool for solving the synchronization problem of chaotic systems and has received widespread attention. However, previous ZNN models only focused on the synchronization problem of real chaotic systems, failing to tackle the synchronization problem of complex chaotic systems. Based on this, this paper proposes a novel complex-valued time varying zeroing neural network (CVTVZNN) model. This paper rigorously derives the fixed-time convergence and external noise suppression ability of the CVTVZNN model in solving the synchronization problem of complex chaotic systems. Through the results of three numerical experiments on the synchronization of complex Chen chaotic system, complex autonomous chaotic system and complex dynamos chaotic system, verified that the CVTVZNN model has faster convergence speed and higher accuracy in suppressing disturbances compared to other existing ZNN models. It is worth noting that the experimental results show that the CVTVZNN model only takes about 0.00115 s to complete the synchronization task, whether in the noise-free or in environments with external noise. However, in the same experimental environment, other models either cannot achieve synchronization at all, or require at least 0.217 s, which is at least 188 times the synchronization time achieved by the CVTVZNN model. Furthermore, its practical application value has been further demonstrated through its implementation on field programmable gate array.

关键词： Zeroing neural network Complex chaotic system synchronization Fixed-time convergence Robustness field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Low-Cost and High-Throughput Hardware Accelerator for Deblocking Filter in HEVC

引用

IETE JOURNAL OF RESEARCH 2025年第3期71卷 909-918页

作者： Saravanan, P. Megalingam, R. Sanjana, S. Priyadharshini, T. Sharon Prashanth, S. Kanna, P. Vignesh PSG Coll Technol Dept ECE Coimbatore India Juniper Network India Pvt Ltd Bangalore India Oracle Financial Serv Software Ltd Bangalore India

This paper proposes a low-cost and high-throughput hardware accelerator for the deblocking filter in the encoder and decoder of high-efficiency video coding (HEVC). The total image is split into CTUs (coding tree units) of size 64 x 64 pixels each, which are further divided into 32 x 32 blocks and individually processed. Parallelism is simultaneously applied in this design to filter two luma edges and one chroma edge. In order to minimize the area utilization, the same filter is used for filtering both horizontal and vertical edges. The proposed architecture takes 36 clock cycles to process a 32 x 32 block of the image. The design is implemented in Virtex-6 and Zybo FPGA boards and also in the Cadence tool. The pipelining techniques are used effectively at various levels to provide a high-throughput design, which supports the deblocking of a 16 K UHD (ultra-high definition) video at 134 frames per second (fps).

关键词： Application-specific integrated circuits deblocking filter field programmable gate array filtering order hardware accelerator high-efficiency video coding

来源：评论

学校读者我要写书评

暂无评论

A dual-neuron memristive hopfield neural network and its application in image encryption

引用

NONLINEAR DYNAMICS 2025年第14期113卷 18705-18726页

作者： Liu, Lin Huang, Yi Chen, Zuguo Chen, Chaoyang Chen, Lei Yao, Wei Jin, Jie Hunan Univ Sci & Technol Sanya Inst Sanya 572024 Hainan Peoples R China Hunan Univ Sci & Technol Sch Phys & Elect Sci Xiangtan 411201 Hunan Peoples R China Changsha Med Univ Sch Informat Engn Changsha 410219 Hunan Peoples R China Changsha Univ Sci & Technol Sch Comp & Commun Engn Changsha 410114 Hunan Peoples R China

As one of the four basic electronic components, memristors have been widely applied in artificial neural networks in recent years. However, most of the existing researches focus on the application of memristors in artificial neural networks with three or more neurons, and the artificial neural networks with two neurons are rarely reported. Therefore, a one equilibrium point dual-neuron memristive Hopfield neural network (DNMHNN) model with a memristor serving as the coupling synapse between neurons is proposed in this work. In this research, the chaotic dynamic characteristics of the proposed DNMHNN model are analyzed by various fundamental dynamic analysis methods. Then, its chaotic dynamic characteristics are further validated by field programmable gate array implementation, which further verifies the consistency of the theoretical analysis and experimental results. Finally, a color image encryption algorithm based on the chaotic sequences generated by the proposed DNMHNN model is designed and implemented, which further validates the practical application feasibility and security of the proposed DNMHNN model and the image encryption algorithm.

关键词： Hopfield neural network Image encryption Chaotic dynamics field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Semantic-Driven Ghosting-Free Image Fusion Using Dual Gain Video Stream With FPGA

引用

INTERNATIONAL JOURNAL ON SEMANTIC WEB AND INFORMATION SYSTEMS 2025年第1期21卷

作者： Xu, Yang Xie, Longhua Huang, Hongchuan Yu, Feihong Zhao, Tingyu Zhejiang Sci Tech Univ Optoelect Informat Engn Hangzhou Peoples R China Zhejiang Univ Opt Engn Hangzhou Peoples R China Lib Zhejiang Scitech Univ Hangzhou 310018 Zhejiang Peoples R China

Conventional methods that merge multiple images with different exposure levels often suffer from blur and ghosting due to object movement. Existing ghosting removal algorithms are usually complex and slow, making them unsuitable for real-time video applications. To address this challenge, on an FPGA. IMX662 image sensor is employed, which simultaneously captures both HCG and LCG images with the same exposure time, enabling efficient HDR image synthesis. The proposed method directly addresses the source of the problem, eliminating the need for post-processing steps, thereby preserving algorithmic simplicity. Experimental results reveal that the proposed method not only removes ghosting by 100% but also processes data on an FPGA 98.79% faster than traditional software-based HDR fusion techniques, enabling real-time video stream processing. This dual gain, ghosting-free fusion algorithm demonstrates promising potential for use in high-speed photography and surveillance.

关键词： Image Fusion Ghosting-Free High Conversion Gain Low Conversion Gain field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Efficient Integer-Only-Inference of Gradient Boosting Decision Trees on Low-Power Devices

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第1期72卷 241-253页

作者： Alsharari, Majed Mai, Son T. Woods, Roger Reano, Carlos Queens Univ Belfast Sch Elect Elect Engn & Comp Sci Belfast BT7 1NN North Ireland Univ Valencia Dept Comp Sci Valencia 46010 Spain

There is increasingly interest in developing embedded machine learning hardware as it can offer better performance in terms of privacy, bandwidth efficiency, and scalability. Gradient-boosted decision trees (GBDT) represent a strong candidate as they employ less complex logic, but their efficient implementation in field programmable gate array (FPGA) needs to be explored in detail. In this paper, we propose sophisticated quantisation approaches to balance the dual goals of efficiency and performance. In particular, we introduce quantisation-aware training of GBDT for integer-only and binary arithmetic. Results are presented for implementations on a Zynq UltraScale + MPSoC FPGA with the best design using only 170 Look-up Tables and 233 flip-flops at a clock speed of 724 MHz. Implementations focused on network intrusion detection and jet substructure classification for large-scale physics experiments are explored. An order of magnitude less FPGA resources are used whilst offering extremely high throughput rate and maintaining accuracy. Code is available at https://***/malsharari/QATGBDT.

关键词： field programmable gate arrays Quantization (signal) Computational modeling Decision trees Accuracy Training Hardware Gradient-boosted decision trees embedded AI field programmable gate array quantization-aware training design framework

来源：评论

学校读者我要写书评

暂无评论

Enhanced Real-Time Multiuser Uplink UWOC System Based on Hybrid Multiple Access and SGD-PID Power Control Algorithm

引用

JOURNAL OF LIGHTWAVE TECHNOLOGY 2025年第1期43卷 190-197页

作者： Li, Xiao Xia, Yu Gui, Liangqi Li, Han Lang, Liang Huazhong Univ Sci & Technol Sch Cyber Sci & Engn Res Ctr 6G Mobile Commun Wuhan 430074 Peoples R China Huazhong Univ Sci & Technol Sch Elect Informat & Commun Wuhan 430074 Peoples R China

Non-orthogonal multiple access (NOMA) has been widely regarded as the most promising technique for achieving high spectral efficiency in optical communication systems. However, the practical implementation of power domain NOMA faces challenges related to inter-user interference and decoding complexity, limiting its multiplexing capability to a pair of users. In this paper, we experimentally demonstrate a hybrid multiple access scheme in the four-user underwater wireless optical communication (UWOC) system. Specifically, power domain NOMA is employed to multiplex two users within a user pair (UP), while time division multiple access (TDMA) is utilized for each UP. To validate the efficacy of the hybrid multiple access technique, robust watertight transceivers are designed and implemented in a 10-m outdoor pool. A calculation method based on the channel condition is first introduced to retain the received power within a proper range when users in the UP are randomly positioned. Besides, an adaptive stochastic gradient descent-based proportional-integral-derivation (SGD-PID) algorithm is proposed for practical scenarios where determining the system and channel parameters is difficult. Experimental results show that the proposed adaptive power control schemes can effectively enhance system performance under different channel conditions experienced by users. The UWOC system achieves a data rate of 30 Mbps for each user, maintaining bit error rates (BERs) below forward error correction (FEC) threshold. The results highlight the remarkable potential of the hybrid multiple access scheme along with our proposed adaptive power control algorithm.

关键词： NOMA Time division multiple access Synchronization Power control Uplink Resource management Real-time systems field programmable gate array hybrid multiple access scheme non-orthogonal multiple access power control underwater wireless optical communication user pairing

来源：评论

学校读者我要写书评

暂无评论

Remote Power Side- Channel Attacks on FPGAs

IEEE DESIGN & TEST

引用

IEEE DESIGN & TEST 2025年第1期42卷 13-19页

作者： Zhao, Mark Suh, G. Edward Stanford Univ Dept Elect Engn Stanford CA 94305 USA Nvidia Westford MA 01886 USA Cornell Univ Sch Elect & Comp Engn Ithaca NY 14853 USA

Editor's notes: Side-channel attacks, like those exploiting power and timing, are generally thought to require physical access to a system. This research challenges that idea by demonstrating how such attacks can be carried out on remote systems without physical access. It emphasizes the need to rethink how modern shared-FPGA systems are designed, prioritizing security as a core consideration. -Jeyavijayan Rajendran, Texas AM University, USA

关键词： field programmable gate arrays Logic Circuits Monitoring Power demand Logic gates Switches Channel models Side-channel attacks field programmable gate array ring oscillator power analysis attack side-channel attack system-on-chip

来源：评论

学校读者我要写书评

暂无评论

Toward Universal Multiplexer Multiply-Accumulate Architecture in Stochastic Computing

引用

IEEE ACCESS 2025年 13卷 33874-33882页

作者： Lee, Yang Yang Halim, Zaini Abdul Ab Wahab, Mohd Nadhir Almohamad, Tarik Adnan Univ Sains Malaysia Sch Elect & Elect Engn Nibong Tebal 14300 Penang Malaysia Univ Sains Malaysia Sch Comp Sci Gelugor 11800 Penang Malaysia Karabuk Univ Fac Engn Dept Elect Elect Engn TR-78050 Karabuk Turkiye

Stochastic Computing (SC) has recently gained attraction due to its inherent error tolerance and extremely simple arithmetic hardware, making it particularly effective for accelerating modern applications such as neural networks on resource-constrained devices. Traditional SC architectures often adopt binary computing principles, relying on dedicated hardware, i.e. AND gates for multiplication and multiplexers (MUX) for addition. However, SC's mathematical foundation enables the fusion of complex operations into remarkably simple hardware. Several SC studies demonstrated the potential of MUX-based architectures to perform multiply-and-accumulate (MAC) operations, but existing designs face correlation complication, scaling problems, and limited application scope. This paper introduces an auxiliary logic block to address the complexity of MUX select inputs, significantly enhancing the scalability of MUX-based MAC operations. The proposed approach has been validated through SC image processing tasks, including grayscale conversion and Sobel edge detection, achieving up to 75% reduction in hardware resource utilization on field-programmable gate arrays (FPGAs) and up to 96% improvement in computational accuracy compared to traditional AND/XNOR-based SC multipliers.

关键词： Binary sequences Logic gates Hardware Arithmetic Correlation Logic Finite impulse response filters field programmable gate arrays Adders Accuracy Stochastic computing stochastic multiplier image processing field programmable gate array multiply-accumulate hardware

来源：评论

学校读者我要写书评

暂无评论

Hardware-Efficient Polar Decoder for 5G Internet of Things Communication 9th

Hardware-Efficient Polar Decoder for 5G Internet of Things C...

引用

9th International Conference on Intelligent IoT as a Service

作者： Guo, Jing Li, Congduan Sun Yat Sen Univ Sch Elect & Commun Engn Shenzhen Peoples R China

ISBN: (纸本)9783031705069;9783031705076

Polar codes have aroused extensive attention due to their capacity-achieving property and low encoding and decoding complexity. With the increasing demand for real-time and high-quality applications, achieving low-latency communication in resource-constrained scenarios such as on Internet of Things (IoT) devices has become essential. This paper proposes a modified semi-parallel decoder for 5G IoT communication, with low decoding latency and high efficiency of hardware resources. 4-bit decoding algorithm and look-ahead approach are used in this work to reduce latency caused by conventional semi-parallel architecture. For a code length of N = 2(10), the proposed decoder improves latency by 48.64% and 75.19% than the conventional semi-parallel decoder and 2-bit decoder, separately. The significant improvement in hardware utilization rate of processing elements by 68.42% and 119.35% leads to high efficiency of hardware resources.

关键词： Internet of things Polar codes Wireless communication Hardware architecture field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Development of a Multi-Channel Ultra-Wideband Electromagnetic Transient Measurement System

引用

SENSORS 2025年第4期25卷 1159-1159页

作者： He, Shaoyin Chen, Xiangyu Zhang, Bohao Song, Liang Xi An Jiao Tong Univ Sch Elect Engn State Key Lab Elect Insulat & Power Equipment Xian 710049 Peoples R China

In complex electromagnetic environments, such as substations, converter stations in power systems, and the compartments of aircraft, trains, and automobiles, electromagnetic immunity testing is crucial. It requires that the electric field sensor has features such as a large dynamic measurement range (amplitude from hundreds of V/m to tens of kV/m), a fast response speed (response time in the order of nanoseconds or sub-nanoseconds), a wide test bandwidth (DC to 1 GHz even above), miniaturization, and robustness to strong electromagnetic interference. This paper introduces a multi-channel, ultra-wideband transient electric field measurement system. The system's analog bandwidth covers the spectrum from DC and a power frequency of 50 Hz to partial discharge signals, from DC to 1.65 GHz, with a storage depth of 2 GB (expandable). It overcomes issues related to the instability, insufficient bandwidth, and lack of accuracy of optical fibers in analog signal transmission by using front-end digital sampling based on field-programmable gate array (FPGA) technology and transmitting digital signals via optical fibers. This approach is effectively applicable to measurements in strong electromagnetic environments. Additionally, the system can simultaneously access four channels of signals, with synchronization timing reaching 300 picoseconds, can be connected to voltage and current sensors simultaneously, and the front-end sensor can be flexibly replaced. The performance of the system is verified by means of a disconnect switch operation and steady state test in an HVDC converter station. It is effectively applicable in scenarios such as the online monitoring of transient electromagnetic environments in high-voltage power equipment, fault diagnosis, and the precise localization of radiation sources such as partial discharge or intentional electromagnetic interference (IEMI).

关键词： transient electric field measurement ultra-wideband electromagnetic pulse electric field probe field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：