The proceedings contain 22 papers. The topics discussed include: embedded floating-point units in FPGAs;measuring the gap between FPGAs and ASICs;optimality study of logic synthesis for LUT-based FPGAs;improvements to...
详细信息
ISBN:
(纸本)1595932925
The proceedings contain 22 papers. The topics discussed include: embedded floating-point units in FPGAs;measuring the gap between FPGAs and ASICs;optimality study of logic synthesis for LUT-based FPGAs;improvements to technology mapping for LUT-based FPGAs;improving performance and robustness of domain-specific CPLDs;design, implementation, and verification of active cache emulator (ACE);modeling and data-dependent performance of pattern-matching architectures;yield enhancements of design-specific FPGAs;FGPA clock network architecture: flexibility vs. area and power;a reconfigurable hardware based embedded scheduler for buffered crossbar switches;and combining module selection and resource sharing for efficient FPGA pipeline synthesis.
Sea Ice in Polar Regions is typically covered with a layer of snow. The thermal insulation properties and high albedo of the snow cover insulates the sea ice beneath it, maintaining low temperatures and limiting ice m...
详细信息
Sea Ice in Polar Regions is typically covered with a layer of snow. The thermal insulation properties and high albedo of the snow cover insulates the sea ice beneath it, maintaining low temperatures and limiting ice melt, and thus affecting sea ice thickness and growth rates. Remote sensing of snow cover thickness plays a major role in understanding the mass balance of sea ice, inter-annual variability of snow depth, and other factors which directly impact climate change. Researchers at the Center for Remote Sensing of Ice Sheets (CReSIS) at University of Kansas have developed an ultra-wide band FMCW Snow Radar used to measure snow thickness and map internal layers of polar firn from low and high-altitude. This system has shown outstanding performance, but it has some limitations in terms of operational altitude and relies on the operator to make adjustments during surveys to capture radar echoes if the altitude changes significantly. In this thesis, an automated onboard real-time surface tracker for the snow radar is presented to detect snow surface elevation from the aircraft and track changes in the surface elevation. A common technique for an FMCW radar to have a long-range (high-altitude) capability relies on the system’s ability to delay the reference chirp signal used for de-chirping to maintain a relatively constant beat frequency. Currently, the radar uses an analog filter bank to condition the received IF signal over discrete altitude ranges and store the spectral power in each band utilizing different Nyquist zones. During airborne missions in Polar Regions with the radar, the operator has to manually switch the filter banks whenever there is a significant change in aircraft elevation. The work done in this thesis aims at eliminating the manual switching operation and providing the radar with surface detection, chirp delay, and a constant beat frequency feedback loop to enhance its long-range capability and ensure autonomous operation.
Since the recent successful implementation of the long-hypothesized memristor, its use in neuronal computing and in the reproduction of biological neural networks has gained increasing attention. In addition to the de...
详细信息
Since the recent successful implementation of the long-hypothesized memristor, its use in neuronal computing and in the reproduction of biological neural networks has gained increasing attention. In addition to the development of these new applications, the growing number of devices with memristive properties is promising to improve already established technologies. Herein, we use the recently reported memristance in magnesium-oxide-based magnetic tunnel junctions to improve the error tolerance in magnetic random access memory and magnetic fieldprogrammable logic arrays. (C) 2011 American Institute of Physics. [doi:10.1063/1.3660521]
This paper presents aproposal of a new optical multi-context blind scrubbing that can not only increase the soft-error tolerance of the configuration memory of field programmable gate arrays (FPGAs) but also support h...
详细信息
This paper presents aproposal of a new optical multi-context blind scrubbing that can not only increase the soft-error tolerance of the configuration memory of field programmable gate arrays (FPGAs) but also support high-speed dynamic reconfiguration suitable for accelerating FPGA operations. The optical multi-context blind scrubbing operation uses a holographic memory as a soft-error free radiation-hardened external memory. It exploits its two-dimensional large-bandwidth optical bus. Optical multi-context blind scrubbing operation was demonstrated with four configuration contexts. The soft-error tolerance of the scrubbing operation was evaluated using a radiation tolerance experiment using two 4-MBq Americium-241 alpha particle sources. Results show the worst case mean time to repair (MTTR) of the scrubbing operation as 560 ns, which can realize sufficient soft-error tolerance in radiation-rich space environments.
Modem fieldprogrammablegate array (FPGA) chips, with their large memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high-density F...
详细信息
Modem fieldprogrammablegate array (FPGA) chips, with their large memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high-density FPGAs, it is now possible to implement a high-performance very long instruction word (VLIW) processor core in an FPGA. This paper describes research results about enabling the DSP TMS320 C6201 model for real-time image processing applications by exploiting FPGA technology. We present a modular DSP C6201 VHDL model with a variable instruction set. We call this new development a minimum mandatory modules (M-3) approach. Our goals are to keep the flexibility of DSP in order to shorten the development cycle and to use the totality of the powerful FPGA resources in order to increase real-time performance. Some common algorithms of image processing and a face tracking in video sequences application were created and validated on an FPGA Virtexll-2000 multimedia board using the development cycle proposed. Our results demonstrate that an algorithm can easily be, in an optimal manner, specified and then automatically converted to VHDL language and implemented on an FPGA device with system-level software. This makes our approach suitable for developing co-design environments. Our approach applies some criteria for co-design tools: flexibility, modularity, performance, and reusability. In this paper, the target VLIW processor is the DSP TMS320C6x. Nonetheless, our design cycle can be generalized to other DSP processors. (C) 2007 SPIE and IS&T.
Using field programmable gate arrays can dramatically reduce design turn-around time and manufacturing costs for prototype circuits. However, it suffers from lower density and performance compared to conventional gate...
详细信息
Using field programmable gate arrays can dramatically reduce design turn-around time and manufacturing costs for prototype circuits. However, it suffers from lower density and performance compared to conventional gatearrays. The fieldprogrammablegate array with hierarchical interconnection structure (HFPGA) has been proposed to overcome those problems. To physically show the superiority of the HFPGA, this paper presents the circuit design and layout considerations for implementing a HFPGA chip. The schematic circuit of the HFPGA is first described and its physical design by using full-custom top-down method is then presented. It shows a very persuasive argument that the density and performance of the HFPGA architecture are better than the conventional FPGA architecture through experimentation on the proposed HFPGA chip.
The smoothed particle hydrodynamics (SPH) is an efficient method used in the simulation of a strophysical systems. The most computation-intensive part of SPH is the process of generating neighbours lists for all parti...
详细信息
The smoothed particle hydrodynamics (SPH) is an efficient method used in the simulation of a strophysical systems. The most computation-intensive part of SPH is the process of generating neighbours lists for all particles in the simulated astrophysical system. In this paper, we propose two computation-efficient approaches to generate neighbours lists. We also outline their implementations on a hardware platform based on field programmable gate arrays. The FPGA platform will accelerate the neighbours list generation process, eventually leading to high speed simulation of astrophysical systems.
With the shrinking feature sizes of static random access memory-based field programmable gate arrays (FPGAs), the occurrence probability of multiple-cell upsets (MCUs) in FPGAs continues to increase. This reduces the ...
详细信息
With the shrinking feature sizes of static random access memory-based field programmable gate arrays (FPGAs), the occurrence probability of multiple-cell upsets (MCUs) in FPGAs continues to increase. This reduces the reliability of FPGAs. This article proposes an improved hybrid scrubbing scheme to solve this problem. Based on the conventional hybrid scrubbing scheme, the error detection process is improved by changing the error correction object from an erroneous frame to an erroneous zone. MCUs can be rapidly corrected through continuous error detection and erroneous zone correction. The theoretical analysis and implementation results show that the improved hybrid scrubbing scheme can effectively reduce the average repair time of MCU errors.
The paper presents a detailed routing algorithm for the hierarchical field-programmablegatearrays (HFPGAs). This algorithm is performed in two phases. First a multilevel HFPGA is transformed into a single-level HFPG...
详细信息
The paper presents a detailed routing algorithm for the hierarchical field-programmablegatearrays (HFPGAs). This algorithm is performed in two phases. First a multilevel HFPGA is transformed into a single-level HFPGA to find the initial routing results. The initial routing problem is reduced to the graph colouring and Steiner-tree problems. Two types of routing structure, disjointed and overlapped structures, are employed to specify different routing resources in order to improve the routing efficiency. In the second phase, the initial routing results are expanded to a multilevel HFPGA. Experimental results on a set of MCNC benchmark circuits show that the algorithm is very efficient. These results not only validate the claim on the performance of the algorithm but also facilitate the usage of the HFPGAs.
暂无评论