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Optical-Comb-Based Frequency Stability Transfer Across the Spectrum With a Multichannel FPGA

IEEE TRANSACTIONS ON ULTRASONICS FERROELECTRICS AND FREQUENCY CONTROL 2025年第3期72卷 397-406页

作者： Savio, Paolo Goti, Irene Pizzocaro, Marco Levi, Filippo Calonico, Davide Clivati, Cecilia Fdn LINKS I-10134 Turin Italy Ist Nazl Ric Metrolog INRIM I-10135 Turin Italy

Using the optical comb as a transfer oscillator is an effective approach to convert the spectral properties of ultrastable lasers to other wavelength domains. We describe a digital locking system that enables this process to be replicated for several lasers at a time, supporting the simultaneous and independent lock of up to six lasers to a single, high-performance reference oscillator. The locks are robust, easily reconfigured, and contribute a short-term instability lower than 3x10(-18) at 1 s, even when the comb is operated in the broad-linewidth regime and with no need for lasers prestabilization. With this system, we transfer the coherence of the ultrastable clock laser of a Yb optical lattice clock at 1156 nm to various lasers in the 1550 nm region, including the one used for frequency dissemination with long-distance fibers, with less than 1x10(-17) instability at 1 s. The digital implementation enables a modular approach with enhanced control over operational parameters, minimizing setup complexity and hardware-related undesired effects. It also allows for immediate reconfiguration and seamless upgrades, being suitable for applications requiring multiple ultrastable lasers at different wavelengths, such as local or distributed optical clock ensembles, coherent spectroscopy, and quantum simulation.

关键词： Main-secondary Oscillators Clocks Laser stability field programmable gate arrays Optical variables control Fluctuations Laser theory Frequency control Fiber lasers field-programmable gated array (FPGA) low-noise frequency synthesis optical frequency comb ultrastable lasers

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FPGA Based MRI Brain Tumor Segmentation Using Modified FCM Method

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2025年 1-20页

作者： Deepesh, B. Latha, T. St Xaviers Catholic Coll Engn Dept Elect & Commun Engn Nagercoil India

Detecting brain tumors with Magnetic resonance imaging (MRI) is vital for early diagnosis, giving patients a better chance for effective treatment by helping doctors pinpoint and understand the tumor. MRI technology is crucial for identifying tumor growth, enabling patients to receive timely treatment whether the growth is malignant or not. This work proposes an optimized FPGA version of a modified Fuzzy C-Means (FCM) algorithm with three clusters segmenting the brain tumors based on their pixel intensity deviation. The modification involves moving the cluster centers and varying the cluster weights with the mean intensity of the cluster of all the pixels, improving the accuracy. Block RAM of the FPGA device is utilized to store the input, intermediate, and output data to improve timing performance. A pipeline architecture is adopted for all units, including membership calculation, division unit, and centroid updating unit. Pipelining enables these units to work in parallel and thus reduce delays and allow a constant stream of data, which enhances the FCM design performance. The hardware implementation and verification are carried out on the Xilinx XC3S500E-4FG320 FPGA and Zynq UltraScale + ZCU104 platforms, while the Application-Specific Integrated Circuit (ASIC) implementation is performed using 45 nm technology library. The modified FCM technique outperforms conventional methods with a 108.271 MHz operating frequency, 0.859W power consumption, and hardware utilization of 8471 LUTs, 70 DSPs, and 3,897 FFs for 256 x 256 design. ASIC chip occupied 3 x 3 mm of core area and operates at a frequency of 253 MHz with power consumption of 161 mW.

关键词： Magnetic resonance imaging Pixel intensity deviation Modified Fuzzy C-Means field programmable gate arrays Block RAM

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Discrete Two-Heterogeneous-Neuron HNN and Chaos-Based Hardware Poisson Encoder

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IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS 2025年第2期21卷 1862-1871页

作者： Bao, Han Xi, Minqi Tang, Haigang Zhang, Xi Xu, Quan Bao, Bocheng Changzhou Univ Wang Zheng Sch Microelect Changzhou 213159 Peoples R China

Nonlinear activation function is the most essential factor that enables Hopfield neural networks (HNNs) to generate complex dynamics. However, less attention has been paid to the activation function. In this article, we propose a simple discrete model of self-connectionless HNN in which two heterogeneous neurons have different activation functions of sine and hyperbolic tangent. By theoretical and numerical methods, we explore coexisting bifurcation behaviors induced by Neimark-Sacker bifurcations and multifolded hyperchaotic attractors caused by multiple fixed points with different stability. We also evaluate the randomness of these multifolded hyperchaotic sequences and implement the discrete model on field programmable gate array (FPGA) hardware device. In brief, this discrete model with simple algebraic equations has the simplest connection structure under the two-heterogeneous-neuron HNN framework, but it can generate various multifolded hyperchaotic attractors with high randomness. Additionally, based on FPGA hardware device, a chaos-based hardware Poisson encoder is developed to implement the reconstruction of gray image.

关键词： Bifurcation Neurons Mathematical models Hardware Orbits field programmable gate arrays Brain modeling Informatics Encryption Data models Coexisting bifurcation behaviors discrete model fixed point Hopfield neural network (HNN) multifolded hyperchaotic attractor Poisson encoder

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Optimized Design of Phase Self-Correcting Lock-in Amplifier

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷

作者： Wang, Zhengguang Liu, Nan Ru, Zhanqiang Ding, Peng Cheng, Suzhen Gong, Jingwu Wu, Dongmin Yin, Zhizhen Song, Helun Univ Sci & Technol China Sch Nanotech & Nanob Hefei 230026 Peoples R China Chinese Acad Sci Suzhou Inst Nanotech & Nanob SINANO Suzhou 215123 Peoples R China

The output of a single-phase lock-in amplifier (LIA) is sensitive to the phase difference between the input and reference signals, which can significantly reduce detection sensitivity. This article proposes a simple, field-programmable gate array (FPGA)-based, phase self-correcting LIA (PSC-LIA) to address this issue. The PSC-LIA employs a phase segment estimation (PSE) function to determine the phase difference and a proportional-integral (PI) controller to generate a corrective phase control signal. A phase-adjustable square wave generator (P-A SWG), offering a phase adjustment range of -pi to pi , provides the reference signal. To simplify the design of the low-pass filter (LPF), a dedicated low-order high-pass filter (HPF) preprocesses the input signal. Simulations and experimental results validate the effectiveness of the proposed PSC-LIA. Furthermore, its efficacy in extracting error signals is evaluated by integrating it into a laser frequency stabilization system. The results demonstrate that the PSC-LIA exhibits excellent performance, a fast response time, and adaptability to a variety of applications.

关键词： Laser stability Signal resolution Laser feedback Amplifiers Accuracy Pump lasers Frequency modulation field programmable gate arrays PI control Nuclear magnetic resonance field-programmable gate array (FPGA) lock-in amplifier (LIA) phase segment estimation (PSE) phase self-correcting square wave

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Computational optical imaging: on the convergence of physical and digital layers

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OPTICA 2025年第1期12卷 113-130页

作者： Wang, Zhaoqiang Peng, Yifan Fang, Lu Gao, Liang Univ Calif Los Angeles Dept Bioengn Los Angeles CA 90095 USA Univ Hong Kong Dept Elect & Elect Engn & Comp Sci Hong Kong Peoples R China Tsinghua Univ Dept Elect Engn Beijing Peoples R China

Optical imaging has traditionally relied on hardware to fulfill its imaging function, producing output measures that mimic the original objects. Developed separately, digital algorithms enhance or analyze these visual representations, rather than being integral to the imaging process. The emergence of computational optical imaging has blurred the boundary between hardware and algorithm, incorporating computation in silico as an essential step in producing the final image. It provides additional degrees of freedom in system design and enables unconventional capabilities and greater efficiency. This mini-review surveys various perspectives of such interactions between physical and digital layers. It discusses the representative works where dedicated algorithms join the specialized imaging modalities or pipelines to achieve images of unprecedented quality. It also examines the converse scenarios where hardware, such as optical elements and sensors, is engineered to perform image processing, partially or fully replacing computer-based counterparts. Finally, the review highlights the emerging field of end-to-end optimization, where optics and algorithms are co-designed using differentiable models and task-specific loss functions. Together, these advancements provide an overview of the current landscape of computational optical imaging, delineating significant progress while uncovering diverse directions and potential in this rapidly evolving field. (c) 2025 Optica Publishing Group under the terms of the Optica

关键词： Computational imaging field programmable gate arrays Imaging systems Integral imaging Optical elements Systems design

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New Developments for the Trigger-Time-Event System for the W7-X Experiment

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 545-552页

作者： Schacht, J. Brockmann, T. Marquardt, M. Recknagel, J. Schroeder, T. Max Planck Inst Plasma Phys Inst Plasma Phys D-17491 Greifswald Germany Univ Rostock Inst Appl Microelect D-18059 Rostock Germany

Since the first plasma operation in 2015, the superconducting fusion experiment Wendelstein 7-X has successfully completed four experiment campaigns (OP1.1, OP1.2a, OP1.2b, and OP2.1). The machine maintenance phase was completed at the end of January 2024, followed by the commissioning of W7-X. The start of the scientific plasma operation phase OP2.2 is planned for September 2024. The trigger-time-event (TTE) system is used by the central control systems, the technical components, and the diagnostics of W7-X for their time synchronization, for processing events, and for generating and receiving trigger signals. These use cases make it necessary to adapt the TTE system to the changing requirements of users. After an introduction to the functions and structure of the TTE system, this contribution describes the current expansion status of the TTE system and the planned modifications and expansion of the hardware and software of the TTE system. Finally, the current status of the planned work on the TTE system for the upcoming W7-X operational phase OP2.2 is presented. The contribution ends with a summary.

关键词： Clocks Plasmas Optical switches Data acquisition Generators field programmable gate arrays Event distribution synchronization timing system trigger generation trigger generation

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Toward Universal Multiplexer Multiply-Accumulate Architecture in Stochastic Computing

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IEEE ACCESS 2025年 13卷 33874-33882页

作者： Lee, Yang Yang Halim, Zaini Abdul Ab Wahab, Mohd Nadhir Almohamad, Tarik Adnan Univ Sains Malaysia Sch Elect & Elect Engn Nibong Tebal 14300 Penang Malaysia Univ Sains Malaysia Sch Comp Sci Gelugor 11800 Penang Malaysia Karabuk Univ Fac Engn Dept Elect Elect Engn TR-78050 Karabuk Turkiye

Stochastic Computing (SC) has recently gained attraction due to its inherent error tolerance and extremely simple arithmetic hardware, making it particularly effective for accelerating modern applications such as neural networks on resource-constrained devices. Traditional SC architectures often adopt binary computing principles, relying on dedicated hardware, i.e. AND gates for multiplication and multiplexers (MUX) for addition. However, SC's mathematical foundation enables the fusion of complex operations into remarkably simple hardware. Several SC studies demonstrated the potential of MUX-based architectures to perform multiply-and-accumulate (MAC) operations, but existing designs face correlation complication, scaling problems, and limited application scope. This paper introduces an auxiliary logic block to address the complexity of MUX select inputs, significantly enhancing the scalability of MUX-based MAC operations. The proposed approach has been validated through SC image processing tasks, including grayscale conversion and Sobel edge detection, achieving up to 75% reduction in hardware resource utilization on field-programmable gate arrays (FPGAs) and up to 96% improvement in computational accuracy compared to traditional AND/XNOR-based SC multipliers.

关键词： Binary sequences Logic gates Hardware Arithmetic Correlation Logic Finite impulse response filters field programmable gate arrays Adders Accuracy Stochastic computing stochastic multiplier image processing field programmable gate array multiply-accumulate hardware

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Novel Hybrid Low-Resource field-programmable-gate-Array Time-to-Digital-Converter Architecture

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷

作者： Real, Diego Calvo, David Manzaneda, Mario Diaz, Antonio Rebecca Gozzini, Sara Zornoza, Juan de Dios Ricolfe-Viala, Carlos Lajara, Rafael Univ Valencia IFIC Inst Fis Corpuscular CSIC Paterna 46980 Spain Univ Granada Dept Comp Architecture & Technol CITIC Granada 18071 Spain Univ Politecn Valencia Automat Control & Ind Informat Inst Valencia 46022 Spain Univ Valencia Dept Ingn Elect ETSE Valencia 46100 Spain

Time measurements are challenging in electronics given their various applications. The main focus lies not in achieving greater precision, as conventional architectures have already reached picosecond levels. Instead, the challenge stems from the use of low resources and the substantial expansion in the number of channels. This study presents a novel architecture for the implementation of time-to-digital converters (TDCs) in applications where resources are constrained. The introduced field-programmable-gate-array (FPGA)-based TDC offers a resolution of 415.84 ps, a single-shot precision of 0.45 least significant bits (LSBs) (186 ps r.m.s.) while maintaining a minimal resource occupancy. Built upon a multishift phase counter, the TDC is extended with a tap delay using the input delay available in the FPGA hardware input, doubling the resolution of the TDC. The resource utilization is minimized when compared to low-resource state-of-the-art TDCs. The number of look-up tables (LUTs) has been reduced to 102, and the number of registers to 213. Furthermore, the presented TDC exhibits favorable differential nonlinearity (DNL) (0.2 LSBs) and integral nonlinearity (0.15 LSBs). The TDC has been successfully implemented on an Artix7-2 from Xilinx. This design provides a resource-effective solution for applications requiring high precision and low resource consumption.

关键词： Delays Clocks field programmable gate arrays Hardware Computer architecture Linearity Time-domain analysis Interpolation Delay lines Resource management Low resources multiphase shift-clock tapped delay line (TDL) time-to-digital converters (TDCs)

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TYLOR: TDC-Based Low-Overhead Synthesizable Power SCA Countermeasure on FPGAs

IEEE DESIGN & TEST

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IEEE DESIGN & TEST 2025年第3期42卷 94-102页

作者： Titti, Samarth Shivakumar Saurabh, Harshit Das, Debayan Indian Inst Sci Bengaluru 560012 India

Editor's notes: Side-channel attacks enable an adversary to retrieve secret key from a cryptographic hardware through statistical analysis of physical parameters, such as power. This article presents a low-cost robust defense against this attack using a novel power compensation mechanism. -Swarup Bhunia, University of Florida, USA

关键词： field programmable gate arrays Security Power demand Clocks Integrated circuit modeling Hardware design languages Fluctuations Voltage fluctuations Logic gates Logic Side-Channel Attacks (SCA) Correlational Power Attack (CPA) field programmable gate arrays (FPGA) Circuit Level Countermeasures

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HWSA: A High-Ratio Weight Sparse Accelerator for Efficient CNN Inference

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Dai, Xuejing Zhang, Jinze Wang, Zhongfeng Lin, Jun Nanjing Univ Sch Elect Sci & Engn Nanjing 210008 Peoples R China Sun Yat Sen Univ Sch Integrated Circuits Shenzhen 518107 Peoples R China Nanjing Univ Interdisciplinary Res Ctr Future Intelligent Chips Nanjing 210008 Peoples R China

Pruning has emerged as an effective technique for compressing convolutional neural networks (CNNs) by eliminating redundant weights, achieving lightweight models with negligible loss in inference accuracy. To leverage the sparsity for acceleration, many accelerators built for sparse CNNs have been developed. Existing hardware accelerators can perform well with structured or customized sparsity patterns. However, when facing the unstructured sparsity which can achieve higher compression rates, the corresponding hardware always suffers from insufficient utilization of computational resources, severe load balance between process elements, and significant overhead in logic resources, which results in a reduction of throughput, making it difficult to leverage high ratio sparsity for acceleration effectively. An efficient CNN inference accelerator that can handle both structured and unstructured sparse networks is proposed to address these issues. By flexibly employing multiple parallel computation methods combined with carefully developed sorting algorithms, the proposed architecture mitigates the hardware utilization inefficiencies caused by unstructured sparsity. Through a hardware-software methodology, new sparsity rules are introduced, nearly eliminating the load imbalance issue. The proposed Processing Element (PE) architecture can effectively select inputs for sparse networks while reducing the overhead of logic resources. The proposed architecture is implemented on the XCVU9P FPGA, achieving a frequency of 200 MHz. It achieves a computational throughput of 350.49 GOPs and 326.01 GOPs on ResNet-50 and ResNet-152, respectively, demonstrating a 1.2-2.1x DSP efficiency improvement compared to previous works.

关键词： Hardware Convolutional neural networks Accuracy Sorting Convolution Computer architecture Systolic arrays Parallel processing Kernel field programmable gate arrays Convolutional neural networks (CNNs) unstructured sparsity hardware accelerator field-programmable gate arrays (FPGAs)

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