检索结果-内蒙古大学图书馆

Custom Integrated Circuits Conference (CICC)

作者： B.K. Britton D.D. Hill W. Oswald Nam-Sung Woo S. Singh AT and T Bell Laboratories Inc. Allentown PA USA

The authors describe the optimized reconfigurable cell array (ORCA) field programmable gate array (FPGA) architecture, which incorporates support for large datapath circuits on a nibble wide basis, without diminishing the support for random logic control applications. This is accomplished by providing a programmable function unit which is equally adapted to both environments. The routing structure is similarly designed to allow nibbles of data to be moved around the chip efficiently, while not penalizing the individual connections that characterize typical control logic. The ORCA FPGA and its associated computer-aided design (CAD) system provide users with the opportunity of implementing datapath circuits as well as control circuits easily and efficiently.

关键词： field programmable gate arrays Routing programmable logic arrays Design automation programmable logic devices Logic arrays Logic circuits Logic design programmable control Adders

来源：评论

学校读者我要写书评

暂无评论

Efficient method for the field-programmable gate arrays calculation of Wigner-Ville distribution

引用

IET SIGNAL PROCESSING 2019年第6期13卷 589-595页

作者： Zhang, Xiao-Wei Zuo, Lei Huang, Wen-Zhun Guo, Jian-Xin Xijing Univ Sch Informat Engn Xian Shaanxi Peoples R China Xidian Univ Natl Lab Radar Signal Proc Xian Shaanxi Peoples R China

Various signals of finite length are often analysed by the Wigner-Ville distribution (WVD). Thus, this article deals with the implementation of their discrete WVDs on field-programmable gate arrays (FPGAs). For the discrete WVD, its calculation procedures are composed of the autocorrelation function and Fourier transform. Since the autocorrelation procedure is the most time-consuming step in the entire computation process, the authors analyse the calculation procedure of autocorrelation function in detail. Here the proposed efficient method just calculates partial non-zero elements of the autocorrelation matrices in order to reduce the computation complexity. The FFT (built-in FPGAs) is then utilised to acquire the discrete WVD. In addition, the idea of the fully-pipelined and parallelism is borrowed to reduce the running time but at the cost of recourses. Finally, the authors provide implementations of both authors proposed method and two other algorithms on different FPGAs. The experimental results show that the Intel Arria-10 FPGA families are the better choice in the floating point arithmetic and that authors method has the best performance.

关键词： fast Fourier transforms field programmable gate arrays Wigner distribution floating point arithmetic time-frequency analysis discrete WVD running time different FPGAs authors method efficient method field-programmable gate arrays calculation Wigner-Ville distribution finite length calculation procedure autocorrelation function autocorrelation procedure time-consuming step entire computation process nonzero elements autocorrelation matrices computation complexity

来源：评论

学校读者我要写书评

暂无评论

A digit-recurrence square root implementation for field programmable gate arrays

A digit-recurrence square root implementation for field prog...

引用

IEEE Workshop on FPGAs for Custom Computing Machines

作者： M.E. Louie M.D. Ercegovac Computer Science Department University of California Los Angeles CA USA

Creating efficient arithmetic processors requires a pairing of high speed arithmetic algorithms with optimal mapping strategies for a given technology. The authors propose bit reduction as key to an efficient pairing process for lookup table based field programmable gate arrays (FPGAs). Bit reduction simplifies the functions defining the original algorithm, thus permitting a mapping to fewer blocks and reducing the overall throughput delay. A mapping of a digit-recurrence square root algorithm to the Xilinx XC4010 FPGA illustrates the bit reduction process.< >

关键词： field programmable gate arrays Signal processing algorithms Digital arithmetic Table lookup Computer science Delay Costs Hardware Adaptive signal processing Adaptive filters

来源：评论

学校读者我要写书评

暂无评论

Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories

引用

IET COMPUTERS AND DIGITAL TECHNIQUES 2010年第3期4卷 211-226页

作者： Guillemenet, Y. Torres, L. Sassatelli, G. Univ Montpellier 2 LIRMM CNRS UMR F-34392 Montpellier 5 France

This study describes the integration of thermally assisted switching magnetic random access memories (TAS-MRAMs) in field-programmable gate array (FPGA) design. The non-volatility is achieved through the use of magnetic tunnelling junctions (MTJs) in an MRAM cell. A TAS scheme is used to write data in the MTJ device, which helps to reduce power consumption during a write operation in comparison with the conventional writing scheme used in MTJ devices. Furthermore, the non-volatility allows reducing both power consumption and configuration time required at each power-up of the circuit in comparison with classical static random access memory-based FPGAs. An innovative architecture furthermore provides run-time reconfigurable (RTR) support at minimum area overhead. A RTR FPGA element using TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.

关键词： MRAM devices Logic circuits nonvolatility Digital circuit design, modelling and testing field programmable gate arrays Logic design methods run time reconfigurable support switching magnetic random access memories logic design field programmable gate arrays structures Storage on stationary magnetic media magnetic tunnelling Logic and switching circuits magnetic tunnelling junctions MRAM cell Magneto-acoustic, magnetoresistive, magnetostrictive and magnetostatic wave devices

来源：评论

学校读者我要写书评

暂无评论

Design and Implementation of a Direct Torque Control of Induction Machine utilizing a Digital Signal Processor and the field programmable gate arrays

Design and Implementation of a Direct Torque Control of Indu...

引用

International Conference on Power Electronics and Drive Systems (PEDS)

作者： C.L. Toh N.R.N. Idris A.H.M. Yatim F. Patkar Department of Energy Conversion Universiti Teknologi Malaysia Johor Malaysia Faculty of Electrical Engineering Kolej Universiti Teknikal Kebangsaan Malaysia Malacca Malaysia

Employing both DSP and FPGA in motion control will give advantages of rapid prototyping and higher switching frequency in Direct Torque Control (DTC) drive. This paper presents a high performance DTC induction motor drive with constant switching frequency and low torque and flux ripples. The experimental results prove the feasibility of the proposed controllers, which is achieved using the combination of a DSP and an FPGA.

关键词： Signal design Torque control Induction machines Digital signal processors field programmable gate arrays Digital signal processing Switching frequency Motion control Prototypes Induction motor drives

来源：评论

学校读者我要写书评

暂无评论

ARCHITECTURE OF field-programmable gate arrays

引用

PROCEEDINGS OF THE IEEE 1993年第7期81卷 1013-1029页

作者： ROSE, J ELGAMAL, A SANGIOVANNIVINCENTELLI, A STANFORD UNIV DEPT ELECT ENGNSTANFORDCA 94305 UNIV CALIF BERKELEY DEPT ELECT ENGN & COMP SCIBERKELEYCA 94720

A survey of field-programmable gate Array (FPGA) architectures and the programming technologies used to customize them is presented. Programming technologies are compared on the basis of their volatility, size, parasitic capacitance, resistance, and process technology complexity. FPGA architectures are divided into two constituents: logic block architectures and routing architectures. A classification of logic blocks based on their granularity is proposed and several logic blocks used in commercially available FPGA's are described. A brief review of recent results on the effect of logic block granularity on logic density and performance of an FPGA is then presented. Several commercial routing architectures are described in the context of a general routing architecture modeL Finally, recent results on the tradeoff between the flexibility of an FPGA routing architecture its routability and density are reviewed.

关键词： field programmable gate arrays Switches Routing programmable logic arrays Logic programming Wire Logic devices Integrated circuit interconnections Computer architecture Delay

来源：评论

学校读者我要写书评

暂无评论

Implementation of a New Torque and Flux Controllers for Direct Torque Control (DTC) of Induction Machine Utilizing Digital Signal Processor (DSP) and field programmable gate arrays (FPGA)

Implementation of a New Torque and Flux Controllers for Dire...

引用

Annual IEEE Conference on Power Electronics Specialists (PESC)

作者： C.L. Toh N.R.N. Idris A.H.M. Yatim N.D. Muhamad M. Elbuluk Department of Energy Conversion Universiti Teknologi Malaysia Johor Malaysia Department of Electrical Engineering University of Akron OH USA

This paper presents the simulation and experimental results of a new torque and flux controllers for the direct torque control (DTC) of induction motor drives. The controllers provide a simple solution to the variable switching frequency and high torque ripples problems encountered in the hysteresis-based DTC drives. The controllers operate based on the comparison between the compensated error signals and the triangular waveforms. Implementation of these controllers using the combination of a digital signal processor (DSP) and a field programmable gate array (FPGA) device is presented. The simulation and experimental results showed that the controllers were capable of reducing the torque and flux ripples significantly. At the same time the switching frequency was fixed, independent of the operating conditions

关键词： Torque control field programmable gate arrays Induction machines Digital signal processors Digital signal processing Voltage Hysteresis Switching frequency Electric variables control Stators

来源：评论

学校读者我要写书评

暂无评论

LOGIC SYNTHESIS FOR field-programmable gate arrays

引用

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1994年第10期13卷 1280-1287页

作者： HWANG, TT OWENS, RM IRWIN, MJ WANG, KH PENN STATE UNIV DEPT COMP SCIUNIVERSITY PKPA 16802 NATL CHIAO TUNG UNIV DEPT COMP SCI & INFORMAT ENGNHSINCHU 30043TAIWAN

In this paper, we consider the problem of configuring field programmable gate arrays (FPGA's) so that some given function is computed by the device. Obtaining the information necessary to configure a FPGA entails both logic synthesis and logic embedding. Due to the very constrained nature of the embedding process, this problem differs from traditional multilevel logic synthesis in that the structure (or lack thereof) of the synthesized logic is much more important. Furthermore, a metric-like literal count is much less important. We present a communication complexity-based decomposition technique that appears to be more suitable for FPGA synthesis than other multilevel logic synthesis methods. The key is that our logic optimization technique based on reducing communication complexity is good enough to allow a simple technology mapping to work well for FPGA devices.

关键词： Logic arrays field programmable gate arrays Logic devices Circuit synthesis Table lookup programmable logic arrays Integrated circuit interconnections Very large scale integration Computer science Complexity theory

来源：评论

学校读者我要写书评

暂无评论

A modular 0.8 mu m technology for high performance dielectric antifuse field programmable gate arrays

A modular 0.8 mu m technology for high performance dielectri...

引用

International Symposium on VLSI Technology, Systems and Applications

作者： J. Chen S. Eltoukhy S. Yen R. Wang F. Issaq G. Bakker J.L. Yeh E. Poon D. Liu E. Hamdy Actel Corporation Sunnyvale CA USA Hewlett Packard Company Palo Alto CA USA

A high performance dielectric based antifuse field programmable gate array (FPGA) process has been developed using a standard 0.8 mu m double layer metal CMOS process. The process requires two additional self-contained modules to implement both the programmable interconnect element and the high voltage transistors required to program the antifuses. The antifuse is 8.4 nm ONO dielectrics. The high voltage transistors are 35 nm gate oxide with a novel S/D implant offset to field oxide edge and gate edge to achieve 20 volts programming voltage without disturbing the standard CMOS transistors. A family of FPGA's was developed using this technology yielding system-level performance of 75 MHz and 16 bit counter performance in excess of 125 MHz.< >

关键词： Dielectrics field programmable gate arrays CMOS process Implants CMOS technology Integrated circuit interconnections Breakdown voltage Logic programming Jacobian matrices Standards development

来源：评论

学校读者我要写书评

暂无评论

Fast Fault Tree Analysis for Hybrid Uncertainties Using Stochastic Logic Implemented on field-programmable gate arrays: An Application in Quantitative Assessment and mitigation of Welding Defects Risk

引用

QUALITY AND RELIABILITY ENGINEERING INTERNATIONAL 2017年第7期33卷 1367-1385页

作者： Shoar, Shahab Zarandi, Hamid R. Nasirzadeh, Farnad Cheshmikhani, Elham Univ Mehralborz Dept Project & Construct Management Tehran Iran Amirkabir Univ Technol Dept Comp Engn & Informat Technol Tehran Polytech Tehran Iran PNU Fac Engn Dept Civil Engn Tehran Iran

This paper presents a stochastic logic-based method for quantitative risk assessment using fault tree analysis (FTA) that can take into account both types of uncertainties including objective and subjective uncertainties. In the proposed method, each fault tree gate is translated to its corresponding stochastic logic template and then is implemented on a field programmable gate array (FPGA). Because the analysis does not utilize any transformation methods, the results of analysis are more accurate than those methods which are based on transformation from possibility to probability distributions or vice versa. Experimental results for a benchmark fault tree show that this method accelerates analysis time compared to conventional hybrid uncertainty analysis method and transformation methods. The efficiency of the proposed method is demonstrated by implementation in a real steel structure project. The quantitative risk assessment is performed for the incomplete penetration as one of the defects encountered in arc welding process, and its results are compared with transformation methods. The comparison results show the proposed hybrid uncertainty analysis method is also more accurate in comparison to the transformation-based approaches. Copyright (c) 2016 John Wiley & Sons, Ltd.

关键词： FTA objective uncertainty subjective uncertainty Quantitative risk assessment stochastic logic field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：