The following paper describes the results of ionizing dose rate investigations into upset, supply photocurrent, latch-up, and burnout susceptibility of the Xilinx Virtex IV XC4VFX12. All investigations were performed ...
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The following paper describes the results of ionizing dose rate investigations into upset, supply photocurrent, latch-up, and burnout susceptibility of the Xilinx Virtex IV XC4VFX12. All investigations were performed on a commercial version of the device. The maximum no-upset dose rate was 2.8times10 8 rad(Si)/s. Photocurrent amplitudes as a function of dose rate were recorded.
In real time process, multiple heterogeneous signals can be acquire with the help of data acquisition and processing (DAQP) and process them in real time process. The main objective of this technology is to monitor di...
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In real time process, multiple heterogeneous signals can be acquire with the help of data acquisition and processing (DAQP) and process them in real time process. The main objective of this technology is to monitor different levels of signals from different sensors without any additional usage of the hardware devices. The proposed system is design in system on chip via fieldprogrammablegate Array (FPGA) to check the speed of the acquired signals. Various modules of the conceptual designs are implemented and verified using LabVIEW graphical programming. The hardware testing is implemented with the help of NI-DAQ and NI-FPGA. This testing allows for high speed processing and also keeping the device cost less.
DSP based design approach for sinewave inverters are discussed in the past [N. Kularatna, et al., 1998; N. Kularatna, 2000; N. Kularatna, et al., 1999; N. Kularatna, et al., 2000; N. Kularatna, et al., 2001]. However,...
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DSP based design approach for sinewave inverters are discussed in the past [N. Kularatna, et al., 1998; N. Kularatna, 2000; N. Kularatna, et al., 1999; N. Kularatna, et al., 2000; N. Kularatna, et al., 2001]. However, due to generalized hardware in DSP chips, implementation of a control block of a sinewave inverter for precise RMS control and total harmonic distortion (THD) minimization may not be hardware efficient. As an alternative, special look-up table based FPGA approach for THD control is discussed in the paper, where no higher order harmonics are calculated individually.
This paper describes a Built-In Self-Test (BIST) approach designed to verify the integrity of the embedded multiplier cores in Altera Cyclone II field programmable gate arrays (FPGAs). This approach uses an architectu...
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This paper describes a Built-In Self-Test (BIST) approach designed to verify the integrity of the embedded multiplier cores in Altera Cyclone II field programmable gate arrays (FPGAs). This approach uses an architecture independent test algorithm implemented with parameterized VHDL to support all FPGAs in the Cyclone II family. The BIST is capable of detecting faults within all of the multiplier's modes of operation in three downloads and can identify the location of faulty multiplier(s).
Nowadays, in many high technological fields of research the classical Time-to-Digital-Converter (TDC) structure is no more satisfactory, since the architecture of one measuring unit connected to many sensors is no mor...
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ISBN:
(数字)9781728141640
ISBN:
(纸本)9781728141657
Nowadays, in many high technological fields of research the classical Time-to-Digital-Converter (TDC) structure is no more satisfactory, since the architecture of one measuring unit connected to many sensors is no more feasible because the not sufficient number of channels, the lack of flexibility or both. This is the case, for instance, of Positron Emission Tomography (PET) facilities of last generation. In the Nuclear Science Symposium 2018 we presented a "All-Digital Fully-Configurable Instrument for Multi-Channel Time Measurements at High Performance". The present contribution deals with the implementation of a distributed architecture of TDCs, i.e. an instrument that allows measuring timestamps on different devices but with the same relative time reference. This allows managing measures performed by different TDCs like if they were collected by a unique device, so providing a huge flexibility that opens the way for new advanced applications like PET network detectors. The realization of a network for TDCs poses two main issues: a high-performance data transfer mechanism in addition to a precise and reliable synchronization methodology. This contribution focuses on the latter issue that is the most critical and complex to address. The analysis is carried out both from theoretical and implementation point of view.
A redundancy scheme and circuitry for field programmable gate arrays (FPGAs) are proposed. The scheme requires the modification of the wiring resource segmentation and the addition of spare rows and selector circuits....
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A redundancy scheme and circuitry for field programmable gate arrays (FPGAs) are proposed. The scheme requires the modification of the wiring resource segmentation and the addition of spare rows and selector circuits. An improved yield gross product is quantitatively studied. The disadvantages caused by this architecture, such as an area overhead and speed degradation, are discussed. It is concluded that, in this redundancy scheme, the sufficient number of spare rows is one or two for practical cases and the gross yield product can be doubled at an early stage of production. The proposed scheme can be applicable to a wide range of FPGA architectures.
The design and construction of a hardware fast Fourier transform processor are presented. The hardware relies principally on field programmable gate arrays (FPGAs). The hardware architecture is based on Tukey-Cooley b...
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The design and construction of a hardware fast Fourier transform processor are presented. The hardware relies principally on field programmable gate arrays (FPGAs). The hardware architecture is based on Tukey-Cooley butterfly algorithms. It uses 218 configurable logic blocks (CLBs) and 42 input-output processors (IOBs) and implements a simple parallel processing architecture. The input of the processor is 16 real-value points and the output is complex. The execution time of the transform is estimated to be 0.736 ms.< >
This paper introduces the concept of "parallel genetic algorithms", to provide a solution for the placement problem for field programmable gate arrays, that complements routing to enhance the performance of ...
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This paper introduces the concept of "parallel genetic algorithms", to provide a solution for the placement problem for field programmable gate arrays, that complements routing to enhance the performance of the circuit implemented by the fieldprogrammablegate array. We propose to utilize the concept of parallelism to genetic algorithms to transform a set of initial populations of random placements to a final set of populations that contain solutions approximating the optimal one. The fundamental concept of this paper lies in sharing the good solutions among different processes, which may help the genetic algorithm to evolve its population in a more lucrative manner. In conjunction with the migration phase, we employ various genetic operators and the chosen fitness function, to expedite the transformation of the initial population towards the optimal solution. We have simulated the suggested method on a 64-node SGI Origin-2000 platform and the results are extremely encouraging, even for circuits with very large number of nets.
This paper establishes a handshake between the fields of "parallel genetic algorithms" and reconfigurable systems, to provide a solution for the routing problem for FPGAs, that attempts to enhance the perfor...
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This paper establishes a handshake between the fields of "parallel genetic algorithms" and reconfigurable systems, to provide a solution for the routing problem for FPGAs, that attempts to enhance the performance of the circuit implemented by the FPGA. We propose to solve the problem of routing for FPGAs in three phases, out of which the first two utilize the concept of genetic algorithms to transform an initial population of random suggested routings to a population that contains solutions approximating the optimal one.
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