An instrument-on-a-card (IAC) has been developed which uses monolithic microwave integrated circuit technology and field programmable gate arrays to provide a +or-20-dBm RF stimulus capability over the frequency range...
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An instrument-on-a-card (IAC) has been developed which uses monolithic microwave integrated circuit technology and field programmable gate arrays to provide a +or-20-dBm RF stimulus capability over the frequency range of 0.5 to 20.0 GHz. It is capable of being tuned in 0.15-Hz steps, in 200 mu s per step. The entire frequency range can be swept in less than 1 s. Pulse and arbitrary amplitude modulation capabilities are provided along with RF frequency agility. Within the IAC, enhanced electromagnetic interference (EMI) performance is achieved by isolating the RF circuitry from the rest of the VXI circuitry. This is accomplished, in the three-slot-wide C-size VXI module, by means of an RF-tight, shielded compartment.< >
This paper evaluates an architecture that implements a hierarchical routing structure for FPGAs, called a hierarchical FPGA (HFPGA). A set of new tools has been used to place and route several circuits on this archite...
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This paper evaluates an architecture that implements a hierarchical routing structure for FPGAs, called a hierarchical FPGA (HFPGA). A set of new tools has been used to place and route several circuits on this architecture, with the goal of comparing the cost of HFPGAs to conventional symmetrical FPGAs. The results show that HFPGAs can implement circuits with fewer routing switches, and fewer switches in total, compared to symmetrical FGPAs, although they have the potential disadvantage that they may require more logic blocks due to coarser granularity.< >
This paper presents a new general technique for testing field programmable gate arrays (FPGAs) by fully exploiting their programmable and configurable characteristics. A hybrid fault model is introduced based on a phy...
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This paper presents a new general technique for testing field programmable gate arrays (FPGAs) by fully exploiting their programmable and configurable characteristics. A hybrid fault model is introduced based on a physical and behavioral characterization; this permits the detection of a single fault, as either a stuck-at or a functional fault. A general approach which regards testing as can application for the reconfigurable FPGA, is then proposed. It is shown that different arrangements of disjoint one-dimensional arrays with unilateral horizontal connections and common vertical input lines provide a very good solution. A further feature that is considered for array testing, is the relation between the configuration of the logic blocks and the number of I/O pins in the chip. As an example, the proposed approach is applied for testing the Xilinz 4000 family of FPGAs.
New fast and highly complex field programmable gate arrays (FPGAs) allow the design of sophisticated decision logic within the trigger latency time of particle detectors. As an example we show the jet determination of...
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New fast and highly complex field programmable gate arrays (FPGAs) allow the design of sophisticated decision logic within the trigger latency time of particle detectors. As an example we show the jet determination of the Hera-Hl detector at DESY (Deutsches Elektronen Synchrotron) Hamburg. It has to calculate all existing localized energy depositions (jets) in the calorimeter and deliver the result, sorted according to energy. The system is implemented by a network of 3/spl times/440 high density FPGA's which have to deliver the results in less than 1 /spl mu/s. The computing power of the system is equivalent to 70 billion operations per second.
The authors present a new approach to technology mapping for area and delay for truth-table-based field programmable gate arrays. They view the area and delay optimizations during technology mapping as a case of cliqu...
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The authors present a new approach to technology mapping for area and delay for truth-table-based field programmable gate arrays. They view the area and delay optimizations during technology mapping as a case of clique partitioning for which an efficient heuristic was developed. Alternate decompositions were explored by using Shannon expansion. Experimental results are included that were obtained by this approach for area and delay optimization on a number of benchmark examples.< >
This paper presents the design and implementation of a hardware graphical display custom processor for generating and manipulating plots based on a given set of time varying input signals. The paper primarily focuses ...
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This paper presents the design and implementation of a hardware graphical display custom processor for generating and manipulating plots based on a given set of time varying input signals. The paper primarily focuses on the design to generate plots of two sampled sine waves of 5 KHz and 10 KHz respectively, along with horizontal and vertical axes with proper scaling. This was achieved by designing the custom processor in Verilog HDL. A provision is made such that the plots can be zoomed horizontally and vertically, independent of each other. There are two levels of zooming provided for each signal plot, both horizontal and vertical zooming. A legend box at the top right corner of the screen was included to provide the scale details of both horizontal and vertical axes, at any level of zooming. The display of the signal plots and the different levels of zooming are controlled by switches of the fieldprogrammablegate Array (FPGA) DE2 development board. The proposed design gives a compromise solution for flexibility and reconfigurability at the hardware level.
Most testing methods for fieldprogrammablegate Array (FPGA) on-chip memory are designed for Block RAM, which cannot detect all possible faults in UltraRAM due to its different structures and functions. To efficientl...
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ISBN:
(数字)9798331529161
ISBN:
(纸本)9798331529178
Most testing methods for fieldprogrammablegate Array (FPGA) on-chip memory are designed for Block RAM, which cannot detect all possible faults in UltraRAM due to its different structures and functions. To efficiently test all potential faults of UltraRAM, a test method with high fault coverage and reduced testing time needs to be designed. In this paper, a complete fault model for UltraRAM testing is established. Existing and new algorithms for testing this UltraRAM fault model are selected or proposed. The algorithms that have been modified or newly designed are tested by fault simulation, and 100% of the sampling faults are detected. The March MSS with DBS can be simplified to reduce the complexity by O(19N), and the complexity of the Byte-wide write enable testing algorithm can be reduced by O(N) when testing port A. By merging configurations to reduce the number of testing configurations, only nine configurations are required to test all the UltraRAMs in the Advanced Micro Devices Versal XCVE2302 device.
In our previous work, we have described a built-in self-test (BIST) approach for RAM-based field programmable gate arrays (FPGAs), which exploits the reprogrammability of the FPGA to create BIST logic only during off-...
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In our previous work, we have described a built-in self-test (BIST) approach for RAM-based field programmable gate arrays (FPGAs), which exploits the reprogrammability of the FPGA to create BIST logic only during off-line testing. The cost is additional external memory required to store the BIST reconfiguration data, leaving all FPGA logic resources available for system functions. In this paper, the memory requirements as well as the testing time are minimized by selecting a few BIST configurations which provide high fault coverage for inspection tests at board and system manufacturing as well as for efficient system diagnostics and field testing.
In this paper, we present some of the important design factors and performance issues in the development of field programmable gate arrays (FPGAs). Emphasis is placed on the design of logic blocks and interconnection ...
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In this paper, we present some of the important design factors and performance issues in the development of field programmable gate arrays (FPGAs). Emphasis is placed on the design of logic blocks and interconnection resources. We also discuss the possibility of using multiple-valued logic in the design of FPGA logic blocks.
In-system-programmable, SRAM-based field programmable gate arrays (FPGAs) can be used to create processors and coprocessors whose internal architecture as well as interconnections can be reconfigured to match the need...
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In-system-programmable, SRAM-based field programmable gate arrays (FPGAs) can be used to create processors and coprocessors whose internal architecture as well as interconnections can be reconfigured to match the needs of a given application. Exploiting the inherent speed and parallelism of a hardware solution, FPGA-based coprocessors can execute computationally-intensive tasks while maintaining the flexibility of a programmable solution. The successes of this approach have led to the introduction of the first FPGA devices designed for coprocessing applications; the XC6200 FPGA architecture features an SRAM control store, abundant registers, on-chip memory capability, support for high-speed full or partial reconfiguration, and a flexible, hierarchical routing scheme.
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