The paper presents problems related to implementation of control algorithms in FPGA. Proposed solution is based on System-on-programmable-Chip architecture with soft-processor that allows for mixed, hardware/software ...
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The paper presents problems related to implementation of control algorithms in FPGA. Proposed solution is based on System-on-programmable-Chip architecture with soft-processor that allows for mixed, hardware/software implementation and exploration of possible control algorithm realizations, and semi-automatic implementation of custom components in FPGA. The case study is a neural controller for 3-DOF parallel robot for milling. The controller is based on neural model of the inverse dynamics of the manipulator, trained on data collected with the use of a computed torque stabilizing controller. For comparison, both controllers were implemented in a system of the same.
In our previous work, we have described a built-in self-test (BIST) approach for RAM-based field programmable gate arrays (FPGAs), which exploits the reprogrammability of the FPGA to create BIST logic only during off-...
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In our previous work, we have described a built-in self-test (BIST) approach for RAM-based field programmable gate arrays (FPGAs), which exploits the reprogrammability of the FPGA to create BIST logic only during off-line testing. The cost is additional external memory required to store the BIST reconfiguration data, leaving all FPGA logic resources available for system functions. In this paper, the memory requirements as well as the testing time are minimized by selecting a few BIST configurations which provide high fault coverage for inspection tests at board and system manufacturing as well as for efficient system diagnostics and field testing.
In-system-programmable, SRAM-based field programmable gate arrays (FPGAs) can be used to create processors and coprocessors whose internal architecture as well as interconnections can be reconfigured to match the need...
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In-system-programmable, SRAM-based field programmable gate arrays (FPGAs) can be used to create processors and coprocessors whose internal architecture as well as interconnections can be reconfigured to match the needs of a given application. Exploiting the inherent speed and parallelism of a hardware solution, FPGA-based coprocessors can execute computationally-intensive tasks while maintaining the flexibility of a programmable solution. The successes of this approach have led to the introduction of the first FPGA devices designed for coprocessing applications; the XC6200 FPGA architecture features an SRAM control store, abundant registers, on-chip memory capability, support for high-speed full or partial reconfiguration, and a flexible, hierarchical routing scheme.
In this paper, we present some of the important design factors and performance issues in the development of field programmable gate arrays (FPGAs). Emphasis is placed on the design of logic blocks and interconnection ...
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In this paper, we present some of the important design factors and performance issues in the development of field programmable gate arrays (FPGAs). Emphasis is placed on the design of logic blocks and interconnection resources. We also discuss the possibility of using multiple-valued logic in the design of FPGA logic blocks.
Gamma irradiation and annealing of a large number of Actel FPGAs with in-situ current measurements were performed. Lot-to-lot, part-to-part, and burn in variations were measured. Findings include a catastrophic failur...
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Gamma irradiation and annealing of a large number of Actel FPGAs with in-situ current measurements were performed. Lot-to-lot, part-to-part, and burn in variations were measured. Findings include a catastrophic failure mechanism and minimal dose rate effects.
In this paper, a FPGA remote laboratory for students in digital electronics circuits is presented. The proposed system provides low-cost experiments by means of low network bandwidth consumption, effective user manage...
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In this paper, a FPGA remote laboratory for students in digital electronics circuits is presented. The proposed system provides low-cost experiments by means of low network bandwidth consumption, effective user management and low setup cost. The experiments on the remote laboratory are also carried out to demonstrate and evaluate the performance of the proposed system.
field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. One of the necessary requirements to effectively utilize the FPGA's resources is an efficie...
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field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. One of the necessary requirements to effectively utilize the FPGA's resources is an efficient placement and routing mechanism. This paper presents an optimization technique based on swarm intelligence for FPGA placement and routing. Mentor graphics technology mapping netlist file is used to generate initial FPGA placements and routings which are then optimized by particle swarm optimization (PSO). Results for the implementation of a binary coded decimal bidirectional counter and an arithmetic logic unit on a Xilinx FPGA show that PSO is a potential technique for solving the placement and routing problem.
The Fast Fourier Transform (FFT) is an important algorithm in the fields of science and engineering, where it is used in diverse areas such as communications, signal processing, instrumentation, image and video analys...
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The Fast Fourier Transform (FFT) is an important algorithm in the fields of science and engineering, where it is used in diverse areas such as communications, signal processing, instrumentation, image and video analysis, etc. The algorithm is essentially a fast implementation of the Discrete Fourier Transform which allows it to reduce the asymptotic complexity of the latter from O(n 2 ) to the former's O(n log n). In this paper, the radix-2 decimation in time FFT algorithm is implemented and investigated on field programmable gate arrays (FPGA) and Graphic Processing Units (GPU). The hardware descriptive language Verilog HDL (VHDL) is used for the FPGA, while the Open Computing Language (OpenCL) is used for the GPU. Both implementations are compared with various pre-installed IP-core modules of Xilinx and MATLAB for complex input of various sample sizes. From the results, it is concluded that the FPGA shows faster performance for a large number of FFT's of small sizes. On the other hand, the GPU is more promising for large number of FFT's of large sizes. The results also confirm that the FPGA based implementation is faster then the built-in IP-core modules of Xilinx. A hardware synthesis for FPGA is also provided.
Characteristic of a solar photovoltaic (PV) system changes due to the change in environmental conditions, such as light intensity and temperature. Output power of a PV system varies as these conditions change and suff...
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ISBN:
(数字)9781728101378
ISBN:
(纸本)9781728101385
Characteristic of a solar photovoltaic (PV) system changes due to the change in environmental conditions, such as light intensity and temperature. Output power of a PV system varies as these conditions change and suffers substantial power loss if the PV system is not operated at the maximum power point (MPP) of the power-voltage curve. This paper discusses the implementation and optimization of various MPPT algorithms using a low-cost Digilent Basys-3 FPGA. Fractional open circuit voltage (FOCV), perturb and observe (P&O), and incremental conductance (IC) algorithms were investigated. Algorithms were tested under various ambient conditions including abrupt irradiance changes using a programmable solar simulator and the system performances were evaluated. Data was recorded in a PC with the FPGA board interfaced using a custom-designed LabVIEW program. Our work will open-up the opportunity to employ FPGAs as a rugged solution for reliable PV system monitoring, control and power optimization replacing present day microcontrollers.
The proton induced SEU cross-sections of dynamic test designs implemented on Xilinx's Virtex-II and Spartan-3 FPGAs are presented. The cross-sections are used to estimate upset rates in the space radiation environ...
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The proton induced SEU cross-sections of dynamic test designs implemented on Xilinx's Virtex-II and Spartan-3 FPGAs are presented. The cross-sections are used to estimate upset rates in the space radiation environment.
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