Many new radar systems have processing requirements that exceed the capabilities of conventional embedded digital signal processing hardware and software. Certain processing functions, such as digital beamforming, are...
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Many new radar systems have processing requirements that exceed the capabilities of conventional embedded digital signal processing hardware and software. Certain processing functions, such as digital beamforming, are particularly demanding and were historically only feasible in custom designs built with custom application specific integrated circuits. Advances in the speed and size of field programmable gate arrays (FPGA) have allowed many high end signal processing applications to be solved in commercially available hardware. This paper provides an overview of the process of designing signal processing functions in FPGA, and highlights the design of several signal processing functions that have been prototyped using some common tools.
The relationship between the routability of a fieldprogrammablegate array (FPGA) and the flexibility of its interconnection structures is explored. A set of industrial circuits are implemented as FPGAs in a range of...
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The relationship between the routability of a fieldprogrammablegate array (FPGA) and the flexibility of its interconnection structures is explored. A set of industrial circuits are implemented as FPGAs in a range of routing structures with varying flexibility. Experiments indicate that high flexibility is essential for the connection box that joint the logic blocks to the routing channel, but a relatively low flexibility is sufficient for switch boxes at the junction of horizontal and vertical channels.< >
The paper discusses an implementation of a dual-microphone phase-based speech enhancement technique. By using the phases of the incoming sound signals, we mask frequencies with low signal-to-noise ratio (SNR) between ...
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The paper discusses an implementation of a dual-microphone phase-based speech enhancement technique. By using the phases of the incoming sound signals, we mask frequencies with low signal-to-noise ratio (SNR) between the two microphones. Phase-based filtering can achieve high SNR gains with just two microphones, making it ideal for hand-held devices. However, these devices have a limited battery life and lack the processing power needed for a software based implementation. The paper presents a fieldprogrammablegate array (FPGA) implementation that was designed specifically for low-power operation. The FPGA based implementation is compared, with respect to processing capabilities and power utilization, with an off-the-shelf low-power digital signal processor (DSP) implementation.
At present, the relevancy to image processing is increasing and applications of image processing are developing. Also “field programmable gate arrays (FPGA)” is gaining in popularity nowadays. FPGAs are strong in pa...
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At present, the relevancy to image processing is increasing and applications of image processing are developing. Also “field programmable gate arrays (FPGA)” is gaining in popularity nowadays. FPGAs are strong in parallel computation and then can work too fast. Because of these advantages, they are preferred in applications which has complex calculation and needs high speed. In this work, basic image processing applications were implemented on FPGA hardware. Real-time motion video was used for these applications and results of applications were given at the result part of work. Also, the performance of hardware for advanced level of image processing applications was explained.
Concatenations of inner low-density parity-check (LDPC) codes and outer Reed-Solomon (RS) codes were evaluated in magnetic recording channel models by simulations using field programmable gate arrays (FPGAs). Fixed in...
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Concatenations of inner low-density parity-check (LDPC) codes and outer Reed-Solomon (RS) codes were evaluated in magnetic recording channel models by simulations using field programmable gate arrays (FPGAs). Fixed inner LDPC codes were used and the optimal code rates for the outer RS code were obtained. It is observed that the outer RS codes do not always improve sector error rates for a fixed user bit density. The effect of various parameters on the sector error rates was evaluated and discussed.
Radiation results from modern SRAM-based reconfigurable FPGAs are presented. The 65nm Xilinx Mil/Aero Virtex-5, SiliconBlue iCE65, and 40nm Altera Stratix-IV are evaluated for SEE.
Radiation results from modern SRAM-based reconfigurable FPGAs are presented. The 65nm Xilinx Mil/Aero Virtex-5, SiliconBlue iCE65, and 40nm Altera Stratix-IV are evaluated for SEE.
High density programmable logic devices require dedicated synthesis algorithms to maximize the utilization of the device resources. The authors discuss the impact of device architectures on logic synthesis algorithms,...
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High density programmable logic devices require dedicated synthesis algorithms to maximize the utilization of the device resources. The authors discuss the impact of device architectures on logic synthesis algorithms, and show how device specific optimization allows designers to design for multiple architectures from a common design description. The Exemplar Logic synthesis system combines industry standard design entry methods with architecture specific optimization algorithms. This power lets designers easily migrate PLD, FPGA, or ASIC designs to FPGAs or ASICs, and gives designers using top-down design techniques the flexibility to explore speed versus area tradeoffs between FPGAs and ASICs early in the design cycle.< >
The large capacity of field programmable gate arrays (FPGAs) with dynamic reconfigurabilities opens new possibilities in acceleration of the image synthesis. A special computing system, based on FPGA and design to imp...
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The large capacity of field programmable gate arrays (FPGAs) with dynamic reconfigurabilities opens new possibilities in acceleration of the image synthesis. A special computing system, based on FPGA and design to implement the algorithms typically used in image synthesis, has been built at the Faculty of Computer Science and Information Systems, Technical University of Szczecin (Poland). For instance, the 3DDDA algorithm has previously been used for ray tracing and implemented in a dynamic FPGA processor, called PSWO. PSWO processor provides an experimental basis for implementing procedures and algorithms applied in the image synthesis. The results of tests and simulations conducted on a large Power Challenge Computer of SGL were further verified through implementation in an actual PSWO processor. An increase of the speed from several dozen to hundred times was achieved in the test cases.
field programmable gate arrays (FPGAs) are suitable choices for demanding real-time control applications including CNC machine tools, robotics, advanced automation, aviation, automotive systems. Logic-level design cap...
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field programmable gate arrays (FPGAs) are suitable choices for demanding real-time control applications including CNC machine tools, robotics, advanced automation, aviation, automotive systems. Logic-level design capabilities of FPGAs allow engineers to develop efficient yet flexible methods for motion control applications. In fact, certain properties of FPGAs (parallelism, layout management, logic optimization, etc.) can be exploited to reduce the resources used on the FPGA without sacrificing the performance. This paper focuses on this aspect and presents novel implementation methods for motion controllers using FPGAs. The presented methods are applied to a full-state space controller utilizing a Luenberger-type state observer. This controller topology, which can be easily tailored to any application, is implemented on an Altera Cyclone II FPGA chip utilizing the methods elaborated in the paper. Furthermore, the control performances of the resulting systems are investigated through a hardware in the loop simulation (HILS) of a nonlinear system (inverted pendulum) using MATLAB.
Historically, whenever a unique digital interface was needed, a unique piece of hardware was created. In the field of loaders/verifiers this has often led to large, heavy, and expensive equipment to support aircraft p...
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Historically, whenever a unique digital interface was needed, a unique piece of hardware was created. In the field of loaders/verifiers this has often led to large, heavy, and expensive equipment to support aircraft platforms. field programmable gate arrays (FPGAs) can be used to create many different interfaces without the need for unique hardware. This paper explores the techniques used to develop interfaces using FPGAs and provides examples of how FPGAs have reduced the size, weight, and cost of flight line test equipment over the last nine years. FPGAs may also be used to implement some standard interfaces such as IEEE-488, RS-422 and PC parallel ports. The benefits and risks of using FPGAs for these standard interfaces are evaluated.
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