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检索条件"主题词=Field Programmable Gate Arrays"

共 41524 条记录，以下是191-200 订阅

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The use of field programmable gate arrays for reusable interfaces

The use of field programmable gate arrays for reusable inter...

引用

International Automatic Testing Conference, AUTOTESTCON

作者： N. Stong Ogden Air Logistics Center UT USA

Historically, whenever a unique digital interface was needed, a unique piece of hardware was created. In the fieid of program loaders/verifiers this often led to large, heavy and expensive equipment to support aircraft platforms such as the F-16 and F-15. field programmable gate arrays (FPGAs) can be used to create many different interfaces without the need for unique hardware. This paper explores the techniques used to develop interfaces using FPGAs and provide examples of how FPGAs have reduced the size, weight and cost of flight line test equipment over the last 9 years. New uses of FPGAs for future applications are explored, showing additional benefits and further cost savings. FPGAs may also be used to implement some standard interfaces such as IEEE-488, RS-422 and PC parallel ports. The benefits and risk of using FPGAs for these standard interfaces are evaluated.

关键词： field programmable gate arrays programmable logic arrays Manufacturing processes Electronic equipment manufacture Application specific integrated circuits Logic devices Hardware Electronics industry Semiconductor device manufacture Logic design

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System development using Actel field programmable gate arrays

System development using Actel field programmable gate array...

引用

IEEE Compcon

作者： D. McCarty Actel Corporation

A new way to reduce risk and time in system-level development while retaining a high level of logic integration lies in the use of field-programmable gate arrays (FPGAs). An FPGA is an application-specific IC (ASIC) that is configurable by the designer at his or her desk. FPGAs are one-time programmable devices that are developed using a standard computer-aided-engineering (CAE) system and Actel software. As in any technology, a design is captured and functionality simulated. After the net list is translated and package pins assigned, the design must be mapped to the physical device and a file for programming the device must be created. The use of FPGAs provides benefits during all the stages of development. During prototyping the devices provide working hardware rapidly without the cost and delay of wire-wrapped standard device technology, whether for a prototype or emulation of masked gate arrays. Software development can begin as soon as a device is programmed. The design of a simple microprocessor-based computer system is considered as an example of how FPGAs can be used throughout the development cycle.< >

关键词： field programmable gate arrays programmable logic arrays Logic arrays Application specific integrated circuits Software prototyping Prototypes Logic devices Software standards Standards development Computer aided engineering

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Real time texture classification using field programmable gate arrays

Real time texture classification using field programmable ga...

引用

Applied Imagery Pattern Recognition Workshop (AIPR)

作者： G. Wall F. Iqbal J. Isaacs Xiuwen Liu S. Foo Applied Vision Imaging Sciences Florida State University Tallahassee FL USA Machine Intelligence Laboratory FAMU and FSU College of Engineering Tallahassee FL USA

In this paper we present a novel hardware/software approach to implement a highly accurate texture classification algorithm. We propose the use of field programmable gate arrays (FPGAs) to efficiently compute multiple convolutions in parallel that is required by the spectral histogram representation we employ. The combination of custom hardware and software allows us to have a classifier that is able to achieve results of over 99% accuracy at a rate of roughly 6000 image classifications per second on a challenging real texture dataset.

关键词： field programmable gate arrays Histograms Hardware Filters Filtering Software algorithms Computer vision Pixel Kernel Machine intelligence

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An artificial neural network guided parallel genetic approach to the routing problem for field programmable gate arrays

An artificial neural network guided parallel genetic approac...

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International Conference on Neural Information Processing

作者： A. Muthukaruppan S. Suresh B.S.N. Rao V. Kamakoti Digital Circuits and VLSI Laboratory Department of Computer Science and Engineering Indian Institute of Technology Chennai India

This paper introduces the concept of "artificially intelligent parallel genetic algorithms", in the form of an artificial neural network, to provide a solution for the routing problem for FPGAs.

ISBN: (纸本)9810475241

This paper introduces the concept of "artificially intelligent parallel genetic algorithms", in the form of an artificial neural network, to provide a solution for the routing problem for FPGAs.

关键词： Artificial neural networks Genetics Routing field programmable gate arrays Switches Delay Logic arrays Digital circuits Very large scale integration Laboratories

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Testing of Uncustomized Segmented Channel field programmable gate arrays

Testing of Uncustomized Segmented Channel Field Programmable...

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Proceedings of the ACM International Symposium on field-programmable gate arrays, FPGA

作者： Tong Liu Wei Kang Huang F. Lombardi Department of Computer Science Texas A and M University College Station TX USA Department of Electronic Engineering Fudan University Shanghai China

This paper presents a methodology for production-time testing of (uncustomized) segmented channel field programmable gate arrays (FPGAs) such as those manufactured by Actel. The principles of this methodology are based on configuring the uncommitted modules (made of sequential and combinational logic circuits) of the FPGA as a set of disjoint one-dimensional arrays similar to iterative logic arrays (ILAs). These arrays can then be tested by establishing appropriate conditions such as constant testability (C-testability). A design approach is proposed. This approach is based on adding a small circuitry (consisting of two transistors) between each pair of uncustomized modules in a row for establishing the ILA configuration as a one-dimensional unilateral array. It also requires the addition of a further primary pin. Features such as number of test vectors and hardware requirements (measured by the number of additional transistors and primary input/output pins) are analyzed; it is shown that the proposed design approach requires a considerably smaller number of test vectors (a reduction of more than two orders of magnitude) and hardware overhead for the testing circuitry (a reduction of 13.6%) than the original FPGA configuration of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale]. The proposed approach requires 8+2n_f vectors for testing the uncommitted FPGA of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale], where nf is the number of flip-flops (equal to the number of sequential modules for the FPGA of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale]) in a row of the FPGA.

关键词： field programmable gate arrays Circuit testing programmable logic arrays Logic arrays Books Combinational circuits Hardware Pulp manufacturing Iterative methods Sequential circuits

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A novel realtime time-domain EMI measurement system based on field programmable gate arrays

A novel realtime time-domain EMI measurement system based on...

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International Zurich Symposium on Electromagnetic Compatibility (EMC Zurich)

作者： S. Braun M. Al-Qedra P. Russer Institute for High-Frequency Engineering Munich University of Technology Munich Germany

In the past and now measurements are carried out by EMI-receivers operating in frequency-domain. By a time-domain EMI (TDEMI) measurement system the measurement time can be reduced by several orders of magnitude. In this paper a novel real-time TDEMI measurement system that uses a direct hardware implementation of the short time fast Fourier transform (STFFT) and the detector modes is described. The hardware implementation on field programmable gate arrays (FPGAs) allows to process the input signal in realtime. By the continuous processing via the STFFT the IF-signal for selectable frequency can be provided as requested by CISPR 16-1-1. By simulations on a proposed FPGA it is shown that the measurement time can be reduced by a factor of about 2000 in comparison to conventional EMI receivers. The dynamic range of a fixed point FFT has been investigated and it has been shown that a 16-bit fixed point arithmetic is sufficient to fulfill the requirements according to the international EMC standards. EMI signals have been recorded and processed by a hardware model. The results have been compared with measurements obtained with a conventional EMI receiver in the frequency range 30 MHz - 1 GHz

关键词： Time domain analysis Electromagnetic interference field programmable gate arrays Time measurement Hardware Frequency measurement Signal processing Real time systems Fast Fourier transforms Detectors

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A one gigaFLIPS fuzzy logic control chip using only combinational logic and field programmable gate arrays

A one gigaFLIPS fuzzy logic control chip using only combinat...

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IEEE Region 5 Annual Technical Conference

作者： Lars Terum Brian Hernmelman ElisAS Norway Electrical and Computer Engineering Dept. South Dakota School of Mines and Technology Rapid City SD

A real-time fully parallelized fuzzy logic control chip has been designed and implemented in a Xillinx Spartan IIe field programmable gate Array. The current design handles two inputs and one output. Five membership functions are used to fuzzify each input signal, and five membership functions are used to defuzzify the output. Mamdani fuzzy inference is used to evaluate the 25 rules in the rule matrix. Two defuzzification schemes, weighted average and Hemmelman's average have been implemented and evaluated. Fuzzification, rule evaluation, and defuzzification are all performed in a parallel architecture that utilizes only combinational logic. Testing indicates a worst case delay of approximately 25 ns, although typical propagation delays are approximately 18 ns. The worst case delay corresponds to an effective throughput of one billion fuzzy logic inferences per second (one gigaFLIPS).

关键词： Fuzzy logic programmable logic arrays programmable control field programmable gate arrays Propagation delay Performance evaluation Parallel architectures Testing Delay effects Throughput

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Routability prediction for field programmable gate arrays with a routing hierarchy

Routability prediction for Field Programmable Gate Arrays wi...

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International Conference on VLSI Design

作者： Zhibin Dai D.K. Banerji Visual Insights Inc. Toronto ONT Canada Department of Computing & Information Science University of Guelph Guelph ONT Canada

ISBN: (纸本)0769518680

field programmable gate arrays (FPGAs) have emerged as the key technology for rapidly implementing digital circuits in VLSI. Much research has been done on their architecture and applications. One particularly important area of study is their routing implementation, which is greatly affected by the routing architecture and routing resources. This paper explores the effective utilization of a routing hierarchy that is present in the currently available commercial FPGAs. A stochastic model is adopted to investigate the routability on symmetrical FPGAs containing a routing resource hierarchy. The performance of our model is compared to that of an FPGA without a routing hierarchy. Experimental methods are used to determine the switch consumption of various routing resources. Results show that integrating a routing resource hierarchy into FPGAs causes a design to consume fewer routing resources. Consequently, the speed of designs implemented in such FPGAs can be greatly improved.

关键词： field programmable gate arrays Routing Switches Wires Logic Wiring Electronic mail Very large scale integration Circuits Pins

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Technology mapping and circuit depth optimization for field programmable gate arrays

Technology mapping and circuit depth optimization for field ...

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Custom Integrated Circuits Conference (CICC)

作者： Shih-Chieh Chang M. Marek-Sadowska Electrical and Computer Engineering Department University of Wisconsin Santa Barbara CA USA Electrical and Computer Engineering Department University of New Mexico Santa Barbara CA USA

A two-step technology mapping algorithm for lookup-table-type FPGAs (field programmable gate arrays) is proposed. In the first step, the technology mapper attempts to minimize the total number of TLUs (table look-ups) used and the same time to keep the length of the critical path short. Then, it is followed by a rule-based postprocessor which maximally decreases the depth of a circuit. The good results obtained are attributed to the fact that the partitioning approach employed is tightly coupled with the size of the target TLU blocks.

关键词： field programmable gate arrays Delay Prototypes Timing Boolean functions Design engineering Table lookup Large scale integration Circuit testing System testing

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Technology Mapping for field programmable gate arrays using Content-Addressable Memory (CAM)

Technology Mapping for Field Programmable Gate Arrays using ...

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Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： A.K. Jones I.S. Kourtev R. Hoare J.M. Lucas Dept. of Electr. & Comput. Eng. Pittsburgh Univ. PA

This paper describes LURU, a methodology for FPGA combinational technology mapping through the parallel search capability of content-addressable memory (CAM). An overview was shown. First, a circuit is partitioned into a set of subcircuits. Topologies of these subcircuits are described using textual string representations. A precomputed set of strings for the circuit topologies that can be contained in a LUT of K or fewer inputs can be matched against the circuit representation in parallel using the CAM . By using CAM, the search space is increased over traditional technology mapping algorithms. A final mapping is produced for an FPGA device consisting of a heterogeneous network of LUT's of K or fewer inputs

关键词： field programmable gate arrays Computer aided manufacturing CADCAM

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