This article describes a method of reducing power consumption for configuration SRAM cells. Modification of the SRAM cell is performed taking into account special characteristics of FPGA configuration memory. Characte...
详细信息
This article describes a method of reducing power consumption for configuration SRAM cells. Modification of the SRAM cell is performed taking into account special characteristics of FPGA configuration memory. Characteristics of the cells are summarized.
Future large-scale complex computing environments present challenges to the real-time intrusion detection systems (IDSs). In this paper, we design a prototype with hybrid software-enabled detection engine on the basis...
详细信息
Future large-scale complex computing environments present challenges to the real-time intrusion detection systems (IDSs). In this paper, we design a prototype with hybrid software-enabled detection engine on the basis of our improved block-based neural network (BBNN), and integrate it with a high-frequency FPGA board to form a real-time intrusion detection system. The established prototype can seamlessly feed the large-scale NetFlow data obtained from Cisco routers directly into the improved BBNN based IDS. The corresponding BBNN structure and parameter settings have been improved and experimentally tested. Experimental performance comparisons have been conducted against four major schemes of Support Vector Machine (SVM) and Naive Bayes algorithm. The results show that the improved BBNN outperforms other algorithms with respect to the classification and detection performances. The false alarm rate is successfully reduced as low as 5.14% while the genuine detection rate 99.92% is still maintained.
field programmable gate arrays have the main features required for interesting wafer scale systems: high flexibility with potential large number of applications, a repeatable cell, and a built in need for switchable f...
详细信息
field programmable gate arrays have the main features required for interesting wafer scale systems: high flexibility with potential large number of applications, a repeatable cell, and a built in need for switchable flexible routing. Wafer scale work must involve routing around defective cells to build the large system. However, it is important to minimize signal delays so the bypassing of the defective cells is invisible. Experiments on a small test FPGA shows defect avoidance routing using laser link structures produces delays which are about half those produced by the active switches required for the FPGA's operation.
Billions of internet end-users and device to device connections contribute to the significant data growth in recent years, large scale, unstructured, heterogeneous data and the corresponding complexity present challen...
详细信息
ISBN:
(纸本)9781479942732
Billions of internet end-users and device to device connections contribute to the significant data growth in recent years, large scale, unstructured, heterogeneous data and the corresponding complexity present challenges to the conventional real-time online fraud detection system security. With the advent of big data era, it is expected the data analytic techniques to be much faster and more efficient than ever before. Moreover, one of the challenges with many modern algorithms is that they run too slowly in software to have any practical value. This paper proposes a fieldprogrammablegate Array (FPGA) -based intrusion detection system (IDS), driven by a new coupled metric learning to discover the inter- and intra-coupling relationships against the growth of data volumes and item relationship to provide a new approach for efficient anomaly detections. This work is experimented on our previously published NetFlow-based IDS dataset, which is further processed into the categorical data for coupled metric learning purpose. The overall performance of the new hardware system has been further compared with the presence of conventional Bayesian classifier and Support Vector Machines classifier. The experimental results show the very promising performance by considering the coupled metric learning scheme in the FPGA implementation. The false alarm rate is successfully reduced down to 5% while the high detection rate (=99.9%) is maintained.
Digital signal processing (DSP) applications commonly depend on multiplication and inner product operations in varying precisions. Creating application-specific integrated circuits (ASICs) for these operations can be ...
详细信息
Digital signal processing (DSP) applications commonly depend on multiplication and inner product operations in varying precisions. Creating application-specific integrated circuits (ASICs) for these operations can be too expensive or too time consuming while off-the-shelf programmable DSP chips may have insufficient performance. As an alternative solution for application-specific designs, field programmable gate arrays (FPGAs) offer hardware reconfigurability with the ease of software programming. This paper explores variable precision multiplication and inner product computations with the Xilinx XC4010 FPGA. We present a modular approach that is easily tailored to any precision.
The dynamically reconfigurable Plessey ERA (electrically reconfigurable array), by supporting the paging of full and partial sets of configuration data at system clock speed, allows silicon multitasking and introduces...
详细信息
The dynamically reconfigurable Plessey ERA (electrically reconfigurable array), by supporting the paging of full and partial sets of configuration data at system clock speed, allows silicon multitasking and introduces the concept of the hardware subroutine. The ERA requires 2.5 times less data per equivalent gate as compared to the established industry standard devices. In addition, loading the data in parallel bytes at clock speeds up to 25 MHz reduces the time taken for the complete configuration of a 10000 equivalent gate array to less than 140 mu s.< >
Irradiations and subsequent failure analyses were performed to investigate single event dielectric rupture (SEDR) in Actel FPGAs as a function of ion LET (linear energy transfer), angle, bias, temperature, feature siz...
详细信息
Irradiations and subsequent failure analyses were performed to investigate single event dielectric rupture (SEDR) in Actel FPGAs as a function of ion LET (linear energy transfer), angle, bias, temperature, feature size, and device type. The small cross sections imply acceptably low risk for most spacecraft uses.
Recompiling a large circuit after making a few logic changes is a time-consuming process. We present an incremental placement algorithm for FPGAs that is focused on extremely fast runtime for changes which can be loca...
详细信息
Recompiling a large circuit after making a few logic changes is a time-consuming process. We present an incremental placement algorithm for FPGAs that is focused on extremely fast runtime for changes which can be localized. It is capable of handling multiple changes across large regions of an FPGA. This is especially useful when used with a floorplan where a modified subcircuit is instantiated several times in the design hierarchy or where several subcircuits are modified. The algorithm is simpler and faster than past approaches because its insertion and legalization steps are based on CPU-efficient shifting steps which do not continuously evaluate the impact of each move on costs. Instead, any lost quality is recovered by a fast, low-temperature anneal at the end. When 35,000 out of 50,000 LUTs are modified, the incremental placement (including fast anneal) is 7 times faster than VPR's "fast placement" from scratch with only 2% quality degradation. The key concepts utilized in the incremental placement algorithm include uses of floor-planning constraints, CPU-efficient CLB shifting, super placement grid and a tuned annealing refinement process.
field programmable gate arrays (FPGAs) are becoming increasingly popular for use in high-integrity safety related and safety critical systems. FPGAs offer a number of potential benefits over traditional microprocessor...
详细信息
field programmable gate arrays (FPGAs) are becoming increasingly popular for use in high-integrity safety related and safety critical systems. FPGAs offer a number of potential benefits over traditional microprocessor based software systems, such as predictable timing performance, the ability to perform highly parallel calculations, predictable emulation of obsolete components, and (in the case of SRAM based FPGAs) the ability to reconfigure to avoid hardware failures. However these abilities do not come for free and often designers are forced to make pessimistic safety and reliability assumptions leading to conservative overall system designs. In this paper a modular, and hence more scalable approach, to performing FPGA safety analysis is presented.
Reconfigurable field programmable gate arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turn application specific integrated circuit (ASIC) from Altera were subjected to single-event testing using heavy io...
详细信息
Reconfigurable field programmable gate arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turn application specific integrated circuit (ASIC) from Altera were subjected to single-event testing using heavy ions. Both Altera devices (Stratix II and HardCopy II) exhibited a low latchup threshold (below an LET of 3 MeV-cm 2 /mg) and thus are not recommended for applications in the space radiation environment. The flash-based Actel ProASIC Plus device did not exhibit latchup to an effective LET of 75 MeV-cm 2 /mg at room temperature. In addition, these tests did not show flash cell charge loss (upset) or retention damage. Upset characterization of the design-level flip-flops yielded an LET threshold below 10 MeV-cm 2 /mg and a high LET cross section of about 1times10 -6 cm 2 /bit for storing ones and about 1times10 -7 cm 2 /bit for storing zeros. Thus, the ProASIC device may be suitable for critical flight applications with appropriate triple modular redundancy mitigation techniques
暂无评论