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检索条件"主题词=Field Programmable Gate Arrays"

共 41522 条记录，以下是211-220 订阅

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Heavy ion and proton see characterization of COTS 0.22/spl mu/m field programmable gate arrays

Heavy ion and proton see characterization of COTS 0.22/spl m...

引用

IEEE Workshop on Radiation Effects Data

作者： R. Koga K. Crawford P. Yu J. George S. Crain M. Zakrzewski J.J. Wang Aerospace Corporation El Segundo CA USA Actel Corporation Mountain View CA USA

Single event effect vulnerabilities of currently available commercial-off-the-shelf (COTS) field programmable gate arrays (FPGAs) have been measured. They are compared with those observed in older COTS devices as well... 详细信息

关键词： Protons field programmable gate arrays Clocks Testing Shift registers Counting circuits Frequency Radiation hardening Space technology Foundries

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Some modular adders and multipliers for field programmable gate arrays

Some modular adders and multipliers for field programmable g...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： J.-L. Beuchat Laboratoire de I'Informatique du Parallélisme CNRS ENSL INRIA Lyon France

This paper is devoted to the study of number representations and algorithms leading to efficient implementations of modular adders and multipliers on recent field programmable arrays. Our hardware operators take advantage of the building blocks available in such devices: carry-propagate adders, memory blocks, and sometimes embedded multipliers. The first part of the paper describes three basic methodologies to carry out a modulo m addition and presents in more details the design of modulo (2/sup n/ /spl plusmn/ 1) adders. The major result is a novel modulo (2/sup n/ + 1) addition algorithm leading to an area-time efficient implementation of this arithmetic operation on FPGAs. The second part describes a modulo m multiplication algorithm involving small multipliers and memory blocks, and modulo (2/sup n/ + 1) multipliers based on Ma's algorithm. We also suggest some improvements of this operator in order to perform a multiplication in the group (Z*/sub 2n+1/,.).

关键词： field programmable gate arrays Arithmetic Adders Logic devices Hardware programmable logic arrays Read-write memory Cryptography Algorithm design and analysis Circuits

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A highly reliable metal-to-metal antifuse for high-speed field programmable gate arrays

A highly reliable metal-to-metal antifuse for high-speed fie...

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International Electron Devices Meeting (IEDM)

作者： M.T. Takagi I. Yoshii N. Ikeda H. Yasuda K. Hama Semiconductor Device Engineering Laboratory Toshiba Corporation Kawasaki Japan Semiconductor Device Engineering Laboratory Toshiba Microelectronics Corporation Kawasaki Japan

This paper describes a novel metal-to-metal antifuse technology for field programmable gate arrays which achieves very high performance and reliability while maintaining full CMOS compatibility. Plasma-CVD SiN with Si/N=1 and Al covered with TiN are used as an antifuse dielectric and electrodes, respectively. This structure allows a desirable characteristics for high-speed FPGAs with off-state reliability of 1.7/spl times/10/sup 5/ years.< >

关键词： field programmable gate arrays Virtual manufacturing Guidelines Semiconductor device reliability Fuses Electrodes Capacitance Dielectric devices Circuit optimization Breakdown voltage

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Realization of a soft output Viterbi equalizer using field programmable gate arrays

Realization of a soft output Viterbi equalizer using field p...

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IEEE Conference on Vehicular Technology (VTC)

作者： P. Jung J. Blanz Research Group for RF Communications University of Kaiserslautern Kaiserslautern Germany

The authors discuss the microelectronic realization of a Viterbi equalizer with soft decision outputs (SOVE, soft output Viterbi equalizer) using XILINX XC4000 series logic cell arrays (LCAs), a special type of field programmable gate array. LCAs are chosen because of their high flexibility and their low price. They are well suited for prototyping. The most advantageous features of the presented SOVE are real-valued signal processing in the intermediate frequency domain and flexibility due to the calculation of the metric increments by using ROM look-up tables.

关键词： Viterbi algorithm Equalizers field programmable gate arrays programmable logic arrays Additive white noise Tail GSM Gaussian noise Electronic mail Microelectronics

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Creating digital fingerprints on commercial field programmable gate arrays

Creating digital fingerprints on commercial field programmab...

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IEEE International Conference on field-programmable Technology (FPT)

作者： James W. Crouch Hiren J. Patel Yong C. Kim J. Todd McDonald Tony C. Kim Department of Electrical & Computer Engineering Air Force Institute of Technology OH USA Air Force Research Laboratory OH USA

In this paper, we discuss the method of creating a circuit identifier, or digital fingerprint, for field programmable gate arrays (FPGAs). The proposed digital fingerprint is a function of the natural variations in the semiconductor manufacturing process that cannot be duplicated or forged. The proposed digital fingerprint allows the use of any arbitrary of nodes internal to the circuit or the circuit outputs as monitoring locations. Changes in the signal on a selected node or output can be quantified digitally over a period of time or at a specific instance of time. Two monitoring methods are proposed, one using cumulative observation of the nodes and the other samples the nodes based on a signal transition. Two monitoring methods were validated on a small sample of twenty Xilinx reg Virtex-II Pro FPGAs, where both methods successfully created unique identifiers for each FPGA. In addition, the effects of temperature and voltage fluctuations are also discussed.

关键词： Fingerprint recognition field programmable gate arrays Circuits Monitoring Sampling methods Shift registers Signal processing Manufacturing processes Temperature Hardware

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A development system for creating real-time machine vision hardware using field programmable gate arrays

A development system for creating real-time machine vision h...

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： T.H. Drayer J.G. Tront R.W. Conners P.A. Araman Bradley Department of Electrical Engineering Virginia Polytechnic Institute and State University Blacksburg VA USA United States Forest Service Brooks Forest Products Center Virginia Polytechnic Institute and State University Blacksburg VA USA

In this paper, we introduce a new development system for creating real-time image processing hardware using custom computing machines with multiple field programmable gate Array (FPGA) chips. Three distinct processes are accomplished within the development system: design entry, verification, and translation. A library of modules that implement common low-level machine vision functions is used to create complex designs based on a dataflow graph representation. The library's low-level image processing modules contain both gate-level and chip-level hardware components, of which the gate-level components are compiled into the functionality of available FPGA chips. Standard interfaces are established for input/output of the modules, allowing for the creation of sophisticated software support tools. Experimental results verify the utility of this development system for easily creating real-time machine vision hardware using multiple FPGA-based custom computing machines.

关键词： Real time systems Machine vision Hardware Image processing Computer architecture field programmable gate arrays Process design programmable logic arrays Logic arrays Printed circuits

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Real-Time Detection of Solder-Joint Faults in Operational field programmable gate arrays

Real-Time Detection of Solder-Joint Faults in Operational Fi...

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IEEE Conference on Aerospace

作者： James P. Hofmeister Pradeep Lall Edgar Ortiz Douglas Goodman Justin Judkins Ridgetop Group Inc. Tucson AZ USA Mechanical Engineering Aubum University Auburn AL USA

In this paper we present two sensors for real-time detection of solder-joint faults in programmed, operational field programmable gate arrays (FPGAs), especially those FPGAs in ball grid array (BGA) packages. The first sensor uses a method in-situ within the FPGA and the second sensor uses a method external to the FPGA. Initial testing indicates the first method is capable of detecting high-resistance faults of 100 Omega or lower and which last one-half a clock period or longer. A prototype of the second method detected high-resistance faults of at least 150 Omega that lasted as low as 25 ns.

关键词： Fault detection field programmable gate arrays Circuit faults Circuit testing Soldering Sensor arrays Built-in self-test Condition monitoring Electronics packaging Prototypes

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Evolutionary Digital Circuit Design with Fast Candidate Solution Establishment in field programmable gate arrays

Evolutionary Digital Circuit Design with Fast Candidate Solu...

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IEEE International Conference on Evolvable Systems

作者： Roland Dobai Kyrre Glette Jim Torresen Lukas Sekanina Faculty of Information Technology Brno University of Technology Brno Czech Republic Department of Informatics University of Oslo Blindern Oslo Norway

field programmable gate arrays (FPGAs) are a popular platform for evolving digital circuits. FPGAs allow to be reconfigured partially which provides a natural way of establishing candidate solutions. Recent research focuses on the hardware implementation of evolutionary design platforms. Several approaches have been developed for effective establishment and evaluation of candidate solutions in FPGAs. In this paper a new mutation operator is proposed for evolutionary algorithms. The chromosome representing the candidate solution is mutated in such a way that only one configuration frame is required for establishing the mutated candidate solution in hardware. The experimental results confirm that the reduced number of configuration frames and mutations at lower level of granularity ensure faster evolution, generation of more candidate solutions in a given time as well as solutions with better quality.

关键词： field programmable gate arrays Biological cells Table lookup Sociology Statistics Training Digital circuits

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Chortle: a technology mapping program for lookup table-based field programmable gate arrays

Chortle: a technology mapping program for lookup table-based...

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Design Automation Conference

作者： R.J. Francis J. Rose K. Chung Department of Electrical Engineering University of Toronto ONT Canada

An algorithm is described for technology mapping of combinational logic into field programmable gate arrays that use lookup table memories to realize combinational functions. It is difficult to map into lookup tables using previous techniques because a single lookup table can perform a large number of logic functions and prior approaches require each function to be instantiated separately in a library. The new algorithm, implemented in a program called Chortle, uses the fact that a K-input lookup table can implement any Boolean function of K inputs and so does not require a library-based approach. Chortle takes advantage of this complete functionality to evaluate all possible decompositions of the input Boolean network nodes. It can determine the optimal (in area) mapping for fanout-free trees of combinational logic. In comparison with the MIS II technology mapper, on MCNC-89 LOGIC Synthesis benchmarks Chortle achieves superior results in significantly less time.< >

关键词： Table lookup field programmable gate arrays programmable logic arrays Logic devices Libraries Boolean functions Logic functions Vegetation mapping Logic design Network synthesis

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Evolutionary based techniques for fault tolerant field programmable gate arrays

Evolutionary based techniques for fault tolerant field progr...

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IEEE International Conference on Space Mission Challenges for Information Technology, SMC-IT

作者： G.V. Larchev J.D. Lohn NASA Ames Research Center University Affiliated Research Center Moffett Field CA USA NASA Ames Research Center Moffett Field CA USA

The use of SRAM-based field programmable gate arrays (FPGAs) is becoming more and more prevalent in space applications. Commercial-grade FPGAs are potentially susceptible to permanently debilitating single-event latchups (SELs). Repair methods based on evolutionary algorithms may be applied to FPGA circuits to enable successful fault recovery. This paper presents the experimental results of applying such methods to repair four commonly used circuits (quadrature decoder, 3-by-3-bit multiplier, 3-by-3-bit adder, 4-to-7 decoder) into which a number of simulated faults has been introduced. The results suggest that evolutionary repair techniques can improve the process of fault recovery when used instead of, or as a supplement to triple modular redundancy (TMR), which is currently the predominant method for mitigating FPGA faults

关键词： Fault tolerance field programmable gate arrays Circuit faults Evolutionary computation Redundancy NASA Decoding Adders Circuit simulation Manufacturing

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