An algorithm, Xmap, is presented for mapping from multilevel logic to field-programmablegatearrays based on table-lookup, such as those used in the Xilinx chip. The algorithm is based on an if-then-else DAG represen...
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ISBN:
(纸本)0897913957
An algorithm, Xmap, is presented for mapping from multilevel logic to field-programmablegatearrays based on table-lookup, such as those used in the Xilinx chip. The algorithm is based on an if-then-else DAG representation for the functions. The technology mapper differs from previous mappers in that the circuit is not decomposed into fan-out-free trees. The Xmap algorithm uses 7% fewer cells than Chortle, 11% fewer than misII, and 14% fewer than mis-pga, and is 4.5 times faster than Chortle, 17 times faster than misII, and at least 150 times faster than mis-pga.
This paper describes a new detailed routing algorithm, specially designed for those architectures that are found in most recent generations of field-programmablegatearrays (FPGAs). The algorithm also brings a soluti...
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ISBN:
(纸本)0780344553
This paper describes a new detailed routing algorithm, specially designed for those architectures that are found in most recent generations of field-programmablegatearrays (FPGAs). The algorithm also brings a solution for those architectures where multiplexed switches are used in order to decrease the chip area like the recently proposed FIPSOC FPGA [1]. The algorithm, called RAISE, can be applied to a broad range of optimizations problems and has been used for detailed routing of symmetrical FPGAs, whose routing architecture consists of rows and columns of logic cells interconnected by routing channels, with or without the use of multiplexed switches. RAISE (Router using Adaptive Simulated Evolution) searches not just for a possible solution, but tries to find the one with minimum delay. Excellent routing results have been obtained over a set of several benchmark circuits getting solutions close to the minimum number of tracks.
This study examined high-current events observed in Xilinx field-programmablegatearrays irradiated with heavy ions. A probable cause and proposed changes to the test methodology to prevent these high-current events ...
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ISBN:
(纸本)9781509060818
This study examined high-current events observed in Xilinx field-programmablegatearrays irradiated with heavy ions. A probable cause and proposed changes to the test methodology to prevent these high-current events is described.
Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmablegatearrays (FPGAs). In this paper, we use the negotiation-based paradigm to pa...
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Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmablegatearrays (FPGAs). In this paper, we use the negotiation-based paradigm to parallelize placement. Our new FPGA placer, NAP (Negotiated Analytical Placement), uses an analytical technique for coarse placement and the negotiation paradigm for detailed placement. We describe the serial algorithm and report results. We also report findings related to parallelizing NAP under a multicast networking and multi-threaded operating system environment;the parallel placer is tolerant to multicast packet loss as well as out-of-order packet delivery. Our parallel placer exhibits little performance degradation while attaining speedups of 2 using 3 processors.
This paper describes how the massive parallelism of the rapidly reconfigurable Xilinx XC6216 FPGA (in conjunction with Virtual Computing's H.O.T. Works board) can be exploited to accelerate the time-consuming fitn...
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ISBN:
(纸本)9780897919784
This paper describes how the massive parallelism of the rapidly reconfigurable Xilinx XC6216 FPGA (in conjunction with Virtual Computing's H.O.T. Works board) can be exploited to accelerate the time-consuming fitness measurement task of genetic algorithms and genetic programming. This acceleration is accomplished by embodying each individual of the evolving population into hardware in order to perform the fitness measurement task. A 16-step sorting network for seven items was evolved that has two fewer steps than the sorting network described in the 1962 O'Connor and Nelson patent on sorting networks (and the same number of steps as a 7-sorter that was devised by Floyd and Knuth subsequent to the patent and that is now known to be minimal). Other minimal sorters have been evolved.
FPGAs are a useful and flexible alternative to custom design chips, but can suffer from severe interconnection delay. The 3D-FPGA is an alternative to the two-dimensional architecture that has been proposed to reduce ...
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ISBN:
(纸本)0769501044
FPGAs are a useful and flexible alternative to custom design chips, but can suffer from severe interconnection delay. The 3D-FPGA is an alternative to the two-dimensional architecture that has been proposed to reduce these delay problems. Here we present Spiffy - the first tool specifically designed for the placement and global routing of 3D-FPGAs. Spiffy produces some of the best results in the literature, and using Spiffy we can show that when mapped to the 3D-FPGA architecture, circuits tend to have considerably shorter net-length, making this new chip an improvement over the standard architecture.
In this paper analytical models for predicting interconnect requirements in field-programmablegatearrays (FPGAs) are presented, and opportunities for 3-D implementation of FPGAs are examined. The analytical models f...
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ISBN:
(纸本)1581133154
In this paper analytical models for predicting interconnect requirements in field-programmablegatearrays (FPGAs) are presented, and opportunities for 3-D implementation of FPGAs are examined. The analytical models for 2-D FPGAs are calibrated by routing and placement experiments with benchmark circuits and extended to 3-D FPGAs. Based on system-level modeling, we find that in FPGAs with 20K 4-input look-up tables, the reduction in channel width, interconnect delay, and power dissipation can be over 50% by 3-D implementation.
With the growing importance of energy efficiency, heterogeneous computing has become more popular in recent years, field~programmablegate array (FPGA) devices are no exception: offering highly parallel execution at l...
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With the growing importance of energy efficiency, heterogeneous computing has become more popular in recent years, field~programmablegate array (FPGA) devices are no exception: offering highly parallel execution at low power, they are an option worth considering for many tasks, and increasingly more available for users through cloud computing services. While FPGA devices offer a lower barrier to entry to logic design than integrated circuit design, they are still difficult to design for compared with instruction set processors. While tools exist for translating 2: high-level language description of an algorithm into an FPGA design, they still require expertise most software designers do not have. One way around this problem is building soft processors onto the programmable logic as a programmability layer for sofware designers. Transport-triggered architectures (TTAS) are a promising avenue of research in this area for their simple implementation and inherently parallel programming model. This thesis presents FPGA-centric optimizations for transport-triggered architectures and evaluation of these optimizations through synthesis. Together, these optimizations yielded between 20 and 30 percent reduction in logic utilization in the tested architectures while having little effect on the clock frequency. Additionally, the scalability of TTAs for more parallel workloads is evaluated with various configurations of a TTA vector processor as well as a convolutional neural network processor case study.
The proceedings contains 24 papers from the ACM/SIGDA international symposium on field programmable gate arrays - FPGA 2004. The topics discussed include: exploration of pipelined FPGA interconnect structures;evaluati...
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The proceedings contains 24 papers from the ACM/SIGDA international symposium on field programmable gate arrays - FPGA 2004. The topics discussed include: exploration of pipelined FPGA interconnect structures;evaluation of low leakage design techniques for field programmable gate arrays;reducing leakage energy in FPGAs using region constrained placement;an embedded true random number generator for FPGAs;a synthesis oriented omniscient manual editor;nanowire-based sublithographic programmable logic arrays;and highly pipelined asynchronous FPGAs.
The proceedings contains 26 papers from the FPGA 2002 Tenth ACM International Symposium on field-programmablegatearrays. Topics discussed include: interconnect enhancements for a high-speed PLD architecture;FPGA swi...
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The proceedings contains 26 papers from the FPGA 2002 Tenth ACM International Symposium on field-programmablegatearrays. Topics discussed include: interconnect enhancements for a high-speed PLD architecture;FPGA switch block layout and evaluation;a faster distributed arithmetic architecture for FPGAs;efficient circuit clustering for area and power reduction in FPGAs and integrated retiming and placement for field programmable gate arrays.
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