Rapid system prototyping is one of the main applications for field-programmablegatearrays (FPGAs). At the stage of rapid system prototyping, design specifications can often be changed since they cannot always be det...
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Rapid system prototyping is one of the main applications for field-programmablegatearrays (FPGAs). At the stage of rapid system prototyping, design specifications can often be changed since they cannot always be determined completely. In this paper, layout design change is focused on and a layout reconfiguration algorithm is proposed for FPGAs. In layout reconfiguration, the main problem is to add LUTs to initial layouts. Our algorithm consists of two steps: For given placement and global routing of LUTs, Step 1 places an added LUT with allowing that the position of the added LUT may overlap that of a preplaced LUT;Then Step 2 moves preplaced LUTs to their adjacent positions so that the overlap of the LUT positions can be resolved. Global routes are updated corresponding to reconfiguration of placement. The algorithm keeps routing congestion small by evaluating global routes directly both in Steps 1 and 2. Especially in Step 2, if the minimum number of preplaced LUTs are moved to their adjacent positions, our algorithm minimizes routing congestion. Experimental results demonstrate the effectiveness and efficiency of the algorithm.
This paper examines various activity estimation techniques in order to determine which are most appropriate for use in the context of field-programmablegatearrays (FPGAs). Specifically, the paper compares how differ...
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This paper examines various activity estimation techniques in order to determine which are most appropriate for use in the context of field-programmablegatearrays (FPGAs). Specifically, the paper compares how different activity estimation techniques affect the accuracy of FPGA power models and the ability of power-aware FPGA CAD tools to minimize power. After comparing various existing techniques, the most suitable existing techniques are combined with two novel enhancements to create a new activity estimation tool called ACE-2.0. Finally, the new publicly available tool is compared to existing tools to validate the improvements. Using activities estimated by ACE-2.0, the power estimates and power savings were both within 1% of the results obtained using simulated activities
We show that the FPGA technology mapping problem can be efficiently implemented as a mixed integer linear programming (MILP) problem which generates truly optimal mappings. The MILP approach can handle a wide variety ...
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We show that the FPGA technology mapping problem can be efficiently implemented as a mixed integer linear programming (MILP) problem which generates truly optimal mappings. The MILP approach can handle a wide variety of FPGA logic block architectures. We present a compact MILP formulation for logic blocks based on lookup tables (LUTs) or multiplexes. We also show that the MILP formulation can be easily modified to optimize area delay, or a combination of both. We demonstrate that moderately large benchmark circuits can be mapped in a reasonable time using the MILP approach directly. For larger circuits, we propose a technique of partitioning a circuit prior to mapping, which drastically reduces the computation time with little or no loss in optimality.
programmable routing and logic in field-programmablegatearrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the high logic value, causing the pMOS tran...
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programmable routing and logic in field-programmablegatearrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the high logic value, causing the pMOS transistor of the downstream buffer to not turn fully off, this approach suffers from static power consumption and reduced noise margins. The standard pMOS transistor pull-up in an active feedback of an inverter reduces the static power consumption, but degrades the switching time and/or active power consumption. We propose a circuit technique to build level-restoring buffers, which improves the propagation delay or active power consumption at a tiny area penalty. Our main idea is to replicate the nMOS element of the downstream buffer, where each replica is driven by a signal that originates from earlier stages of the nMOS-tree multiplexer. This way, when passing high logic values, signals from earlier stages directly drive the downstream buffer improving the delay or the slope of the transition edge. The passing of low logic values is still performed in the original way by the nMOS tree and the pMOS element of the downstream buffer. The simulations indicate an average improvement of the composite metric area-delay-energy product of 25% versus the standard approach across 180 nm, 130 nm, and 90 nm technologies.
This paper presents a performance-oriented placement and routing tool for field-programmablegatearrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strateg...
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This paper presents a performance-oriented placement and routing tool for field-programmablegatearrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wire-length. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route a number of industrial benchmarks.
A description is given of system design and implementation using desktop-programmable, user-configurable gatearrays. The device's innovative antifuse architecture provides the density and performance benefits of ...
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A description is given of system design and implementation using desktop-programmable, user-configurable gatearrays. The device's innovative antifuse architecture provides the density and performance benefits of a masked gate array. Implementing a 2901 bit-slice processor using the Actel ACT 1010 and the Action Logic System is also discussed.< >
The flexibility of field-programmablegatearrays (FPGAs) encourages design reuse and can greatly enhance the upgradability of digital systems. This flexibility is particularly useful in the design of highly flexible ...
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The flexibility of field-programmablegatearrays (FPGAs) encourages design reuse and can greatly enhance the upgradability of digital systems. This flexibility is particularly useful in the design of highly flexible video encoding systems that can accommodate a multitude of existing standards as well as the rapid emergence of new standards. In this paper, we investigate the use of FPGAs in the design of a highly scalable variable block size motion estimation (VBSME) architecture for the H.264/AVC video encoding standard. The scalability of the architecture allows one to incorporate the system into low cost single FPGA solutions for low resolution encoding applications as well as into high performance multi-FPGA solutions targeting high-resolution video encoding applications. To overcome the performance gap between FPGAs and application specific integrated circuits (ASICs), our algorithm intelligently increases its parallelism as the design scales while minimizing the use of memory bandwidth. The core computing unit of the architecture is implemented on FPGAs and its performance is reported in this paper. It is shown that the computing unit is able to achieve real-time 40 fps performance for 640times480 resolution VGA video while incurring only 4% device utilization on a Xilinx XC5VLX330 (Virtex-5) FPGA. With 8 computing units (at 36% device utilization), the architecture is able to achieve real-time 45 fps performance for encoding full 1920times1088 progressive HDTV video.
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