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检索条件"主题词=Field Programmable Gate Arrays"

共 41626 条记录，以下是251-260 订阅

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The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays

The effect of sparse switch patterns on the area efficiency ...

引用

International Conference on field programmable Logic and Applications

作者： Ping Chen Andy Ye Department of Electrical and Computer Engineering Ryerson University Toronto ONT Canada

The increased use of multi-bit processing elements such as digital signal processors, multipliers, multi-bit addressable memory cells, and CPU cores has presented new opportunities for field-programmable gate Array (FPGA) architects to utilize the regularity of multi-bit signals to increase the area efficiency of FPGAs. In particular, configuration memory sharing has been traditionally used to exploit multi-bit regularity for area. We observe that the process of creating configuration memory sharing routing resources often leads to the use of much sparser switch patterns for connecting multi-bit elements to their routing tracks. In this work, we empirically evaluate the effect of these sparse switch patterns on the area efficiency of FPGAs. It is shown that the sparse switch patterns alone contribute significantly to the area reduction observed in configuration memory sharing FPGAs. In particular, our experiments show that, without configuration memory sharing, sparse switch patterns can reduce the implementation area of multi-bit routing resources by 10.4% while configuration memory sharing contributes to an additional 1.2% in area savings. The observation holds over a wide range of connection block flexibility values and demonstrates that efficient switch pattern designs can be effectively used to increase the area efficiency of FPGA routing resources.

关键词： Routing field programmable gate arrays Pins Switches Memory architecture Memory management Logic gates

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Mathematical Model of Transposition Chaotic Encryption System Based on field-programmable gate arrays for Multimedia Data

Mathematical Model of Transposition Chaotic Encryption Syste...

引用

International Scientific-Practical Conference Problems of Infocommunications Science and Technology

作者： Yaroslav Krainyk Yevhen Davydenko Petro Mohyla Black Sea National University Mykolaiv Ukraine

ISBN: (数字)9781728141848

ISBN: (纸本)9781728141855

In the paper, the mathematical model of memory consumption and through-put parameter estimation of a cryptographic system that employs transposition chaotic maps is investigated. The target platform for the system implementation is field-programmable gate Array (FPGA) devices. The proposed mathematical model takes into account limitations of FPGA circuits and can be used to assess usage of FPGA memory resources preliminary and to evaluate throughput efficiency of the encryption system. First, expressions for memory consumption are introduced. The second part is devoted to analysis of the system throughput. Different architectures for memory organization have been considered in the paper as well as all stages of the cipher pipeline. The architectures are characterized by the different level of parallelism on the level of message processing that results in variations in throughput value. The work presents generalized expression for throughput estimation for all the considered cipher architectures. It allows the designer of the system to select an FPGA die that fulfills the basic requirements for cryptographic system implementation.

关键词： field programmable gate arrays Memory management Parallel processing Throughput Streaming media Encryption

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A detailed router for field-programmable gate arrays

A detailed router for field-programmable gate arrays

引用

IEEE International Conference on Computer-Aided Design

作者： S. Brown J. Rose Z. Vranesic Department of Electrical Engineering University of Toronto ONT Canada

The course graph expansion (CGE) detailed routing algorithm is presented for FPGAs (field-programmable gate arrays). The algorithm has the ability to resolve routing conflicts by considering the side-effects of one connection on another, and can be used over a wide range of FPGA interconnection architectures. CGE has been used to obtain excellent routing results for several industrial circuits with various FPGA routing architectures. The results show that CGE is able to route relatively large FPGAs in the absolute minimum number of tracks as determined by global routing, and that CGE has a linear run-time over circuit size.< >

关键词： field programmable gate arrays Routing Wiring Switches Application specific integrated circuits programmable logic arrays Logic arrays Integrated circuit interconnections Runtime Integrated circuit manufacture

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An incremental placement and global routing algorithm for field-programmable gate arrays

An incremental placement and global routing algorithm for fi...

引用

Asia and South Pacific Design Automation Conference

作者： N. Togawa K. Hagi M. Yanagisawa T. Ohtsuki Department of Electronics Information and Communication Engineering Waseda University Tokyo Japan NEC Limited USA

Rapid system prototyping is one of the main applications for field-programmable gate arrays (FPGAs). At the stage of rapid system prototyping, design specifications can often be changed since they cannot always be determined completely. In this paper, layout design change is focused on and a layout reconfiguration algorithm is proposed for FPGAs. In layout reconfiguration, the main problem is to add LUTs to initial layouts. Our algorithm consists of two steps: For given placement and global routing of LUTs, Step 1 places an added LUT with allowing that the position of the added LUT may overlap that of a preplaced LUT; Then Step 2 moves preplaced LUTs to their adjacent positions so that the overlap of the LUT positions can be resolved. Global routes are updated corresponding to reconfiguration of placement. The algorithm keeps routing congestion small by evaluating global routes directly both in Steps 1 and 2. Especially in Step 2, if the minimum number of preplaced LUTs are moved to their adjacent positions, our algorithm minimizes routing congestion. Experimental results demonstrate the effectiveness and efficiency of the algorithm.

关键词： Routing field programmable gate arrays Table lookup Algorithm design and analysis Prototypes Reconfigurable logic Logic design Design engineering Delay Data structures

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Three-dimensional field-programmable gate arrays

Three-dimensional field-programmable gate arrays

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Annual IEEE International Conference and Exhibit ASIC

作者： M.J. Alexander J.P. Cohoon J.L. Colflesh J. Karro G. Robins Dlepartment of Computer Science University of Virginia Charlottesville VA USA

Motivated by improving FPGA performance, we propose a new three-dimensional (3D) FPGA architecture, along with a fabrication methodology. We analyze the expected manufacturing yield, and raise several physical-design issues in the new 3D paradigm. Our techniques also have good implications for resource utilization, physical size, and power consumption.

关键词： field programmable gate arrays Logic arrays Integrated circuit interconnections Switches Fabrication Logic design Computer science Manufacturing Power generation economics Costs

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Area-Speed Tradeoffs for Hierarchical field-programmable gate arrays

Area-Speed Tradeoffs for Hierarchical Field-Programmable Gat...

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Proceedings of the ACM International Symposium on field-programmable gate arrays, FPGA

作者： Vi Cuong Chan D.M. Lewis Department of Electrical and Computer Engineering University of Toronto Canada

This paper investigates area-speed trade-offs for Hierarchical FPGA (HFPGA) architectures. Using a set of new CAD tools, we measured the timing performance of HFPGAs and conventional symmetrical FPGAs using data gathered from experiments on a subset of benchmark circuits from the Microelectronics Centre of North Carolina (MCNC). Experiments were also performed to determine the effect of timing optimized placements on routing channel requirements. These experiments demonstrate that HFPGAs can achieve both better area and speed than symmetrical FPGA architectures.

关键词： field programmable gate arrays Table lookup Switches Logic arrays Routing Computer architecture Pins Delay Software tools Topology

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A scalable computing and memory architecture for variable block size motion estimation on field-programmable gate arrays

A scalable computing and memory architecture for variable bl...

引用

International Conference on field programmable Logic and Applications

作者： Theepan Moorthy Andy Ye Department of Electrical and Computer Engineering Ryerson University Toronto ONT Canada

ISBN: (纸本)9781424419606

In this paper, we investigate the use of field-programmable gate arrays (FPGAs) in the design of a highly scalable variable block size motion estimation architecture for the H.264/AVC video encoding standard. The scalability of the architecture allows one to incorporate the system into low cost single FPGA solutions for low-resolution video encoding applications as well as into high performance multi-FPGA solutions targeting high-resolution applications. To overcome the performance gap between FPGAs and application specific integrated circuits, our algorithm intelligently increases its parallelism as the design scales while minimizing the use of memory bandwidth. The core computing unit of the architecture is implemented on FPGAs and its performance is reported. It is shown that the computing unit is able to achieve 28 frames per second (fps) performance for 640x480 resolution VGA video while incurring only 4% device utilization on a Xilinx XC5VLX330 FPGA. With 8 computing units at 37% device utilization, the architecture is able to achieve 31 fps performance for encoding full 1920x1088 progressive HDTV video.

关键词： Pixel Computer architecture field programmable gate arrays Clocks Bandwidth Motion estimation Pins

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Fast Inverse Compensation of Preisach-Type Hysteresis Operators Using field-programmable gate arrays

Fast Inverse Compensation of Preisach-Type Hysteresis Operat...

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2008 American Control Conference (ACC), vol.6

作者： Xiaobo Tan Omar Bennani Smart Microsystems Laboratory Department of Electrical and Computer Engineering Michigan State University East Lansing MI USA

Preisach-type operators model hysteresis via weighted superposition of a large (and even infinite) number of basic hysteretic elements (called hysterons), and they have proven capable of capturing various complicated hysteretic behaviors. While inverse compensation is an effective approach to control of hysteretic systems, inversion of Preisach-type operators is a bottleneck in demanding, high-speed applications due to the high computational cost. In this paper a novel and general framework is proposed for fast inversion of a wide class of Preisach-type operators, by exploiting the massive parallelism offered by field-programmable gate arrays (FPGAs) to process the inherently parallel hysteresis operators. The theory, algorithm, and implementation of the inversion are presented. The inversion output is computed iteratively with guaranteed convergence (up to machine precision) provided the hysteresis operator is piecewise monotone and Lipschitz continuous. For an operator consisting of m hysterons, the proposed approach shows a computational complexity of O(log m), in contrast to O(m) for methods using general DSPs. The effectiveness of the fast inversion approach is demonstrated by implementation results on open-loop tracking of kHz reference signals, based on inversion of a Krasnosel'skii-Pokrovskii operator.

关键词： Hysteresis field programmable gate arrays Control systems Nonlinear dynamical systems Computational efficiency Parallel processing Convergence Digital signal processing Systems engineering and theory Biological system modeling

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Third-generation architecture boosts speed and density of field-programmable gate arrays

Third-generation architecture boosts speed and density of fi...

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Annual IEEE International Conference and Exhibit ASIC

作者： R.B. Ravel Xilinx Inc. San Jose CA USA

A third-generation family of field-programmable gate arrays (FPGAs) that utilizes a combination of architectural and process improvements and features up to twice the density and speed of currently available FPGA devices is discussed. The architecture allows complete and efficient automated design implementation of FPGA-based designs, as well as maximum density and performance. User-configurable on-chip static memory resources further contribute to the high integration levels available to users of the third-generation devices.< >

关键词： field programmable gate arrays Logic devices Logic arrays Signal generators Boolean functions Logic programming Routing Power generation CMOS logic circuits Clocks

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RAISE: a detailed routing algorithm for SRAM based field-programmable gate arrays using multiplexed switches

RAISE: a detailed routing algorithm for SRAM based field-pro...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： V. Baena-Lecuyer M.A. Aguirre A. Torralba L.G. Franquelo J. Faura Dept. de Ingenieria Electron. Escuela Superior de Ingenieros Sevilla Spain Departmento de Ingenieria Electronica Escuela Superior de Ingenieros Seville Spain

This paper describes a new detailed routing algorithm, specially designed for those architectures that are found in most recent generations of field-programmable gate arrays (FPGAs). The algorithm also brings a solution for those architectures where multiplexed switches are used in order to decrease the chip area like the recently proposed FIPSOC FPGA. The algorithm, called RAISE, can be applied to a broad range of optimization problems and has been used for detailed routing of symmetrical FPGAs, whose routing architecture consists of rows and columns of logic cells interconnected by routing channels, with or without the use of multiplexed switches. RAISE (Router using Adaptive Simulated Evolution) searches not just for a possible solution, but tries to find the one with minimum delay. Excellent routing results have been obtained over a set of several benchmark circuits getting solutions close to the minimum number of tracks.

关键词： Routing Random access memory field programmable gate arrays Switches Delay Algorithm design and analysis Integrated circuit interconnections Circuit simulation Logic design Decoding

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