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DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2025年第2期44卷 540-553页

作者： Dai, Kui Xie, Zheren Liu, Shuanglong Hunan Normal Univ Sch Phys & Elect Key Lab Low Dimens Quantum Struct & Quantum Contro Minist Educ Changsha 410081 Peoples R China

Convolutional neural networks (CNNs) have demonstrated outstanding accuracy among a range of machine learning tasks. However, the huge computational overhead limits their deployability in real-time applications. For this reason, parallel computing has been extensively employed to accelerate CNNs in parallel computing devices, such as GPUs and field programmable gate arrays (FPGAs), by unrolling multiple loop operations of convolutional layers. Nevertheless, existing CNN accelerators can hardly exploit different parallelisms offered by the CNN algorithms efficiently, since their degrees of parallelism are fixed at different dimensions and layers. In this article, we propose the DCP-CNN, an FPGA-based CNN accelerator which implements the CNN with Dynamic Computing Parallelism degrees. DCP-CNN employs a parallel computing architecture which dynamically allocates the computing resources between different data dimensions of each layer based on layer size, to ensure that all computing units are working to full capacity and thus achieve optimal compute efficiency (CE). Furthermore, in order to boost the performance of throughput, we propose a design space exploration (DSE) framework based on the simulated annealing method, which automatically generates the parallelism degrees between different dimensions of the network layers, according to the resource constraints and CNN structure. On Intel Stratix 10 GX650 FPGA, the proposed DCP-CNN achieves the throughput of more than 800 Gop/s and the CE of 72%-98%, which outperforms the existing state-of-the-art FPGA-based CNN accelerators.

关键词： Parallel processing Kernel Convolutional neural networks field programmable gate arrays Convolution Convolutional codes Computer architecture Convolutional neural networks (CNNs) field programmable gate arrays (FPGAs) hardware accelerator loop unrolling parallel computing

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General-Purpose Data Streaming FPGA TDC Synchronized by SerDes-Based Clock Synchronization Technique

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 614-622页

作者： Honda, Ryotaro Ikeno, Masahiro Lin, Che-Sheng Shoji, Masayoshi High Energy Accelerator Res Org Inst Particle & Nucl Studies Tsukuba 3050801 Japan Osaka Univ Res Ctr Nucl Phys Osaka Ibaraki 5670047 Japan

This study proposes a clock synchronization protocol using the functionalities of IDELAYE2 and IOSERDESE2 primitives of an AMD Xilinx field-programmable gate array (FPGA) to serve as a general-purpose data-streaming type time-to-digital converter (TDC) for particle and nuclear physics experiments. A clock synchronization protocol called local area common clock protocol (LACCP) was developed as the upper layer protocol of a proprietary link (MIKUMARI), which was defined prior to this work by a community of users from the experimental physics field in Japan. Clock synchronization is realized using a round-trip time measurement with the system clock period and a fine offset time estimation, which corresponds to the clock signal phase difference between the primary and secondary FPGAs. The fine offset measurement is based on information from the IDELAYE2 and ISERDESE2 primitives utilized as the physical layer of the MIKUMARI link. No extra component is used. The LACCP can be implemented in an FPGA using general IO pin pairs for serial transmission and reception. A streaming high-resolution TDC (Str-HRTDC) was developed based on a tapped-delay-line (TDL) built from CARRY4 primitives in the AMD Xilinx Kintex-7 FPGA. It continuously measures the timing with 19.5-ps intrinsic resolution in sigma and provides unique timestamp information over 2.4 h by introducing the time frame structure defined and synchronized by LACCP. The clock synchronization accuracy and the timing resolution were evaluated by connecting four modules with optical fibers up to 100 m in length. No cable length dependence was confirmed. The obtained synchronization accuracy was approximately 300 ps. The timing resolution between two synchronized modules was 23.1 ps in sigma.

关键词： Clocks Synchronization field programmable gate arrays Protocols Delays Heart beat Data acquisition Logic Signal resolution Nuclear physics Clock synchronization field-programmable gate array (FPGA) serializer-deserializer (SerDes) streaming readout time-to-digital converter (TDC)

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Real-Time 5.7-5.8 GHz 32-Beam Approximate Discrete Fourier Transform Spectrum Sensor for RF Perception on Xilinx Sx475T

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Madanayake, Arjuna Kumarasiri, Umesha Sivasankar, Sivakumar Lawrance, Keththura Gayanath, Buddhipriya Silva, Hiruni Mandal, Soumyajit Cintra, Renato J. Florida Int Univ Dept Elect & Comp Engn Miami FL 33199 USA Brookhaven Natl Lab Dept Elect & Comp Engn New York NY 11973 USA UFPE Dept Technol Signal Proc Grp BR-55014900 Caruaru Brazil

The radio spectrum in the sub-6 GHz (FR1) band is crowded and contested, and is sought after by commercial, scientific and defense users. Situational awareness through spectrum sensing, and AI/ML-enabled perception that recognizes behaviors, patterns, modulations, devices and waveforms is a crucial need for emerging autonomous/cognitive radio systems. This work describes measurable progress in the use of extremely low complexity approximate DFT algorithms as multi-beam beamformers in the digital domain for multibeam spatial RF beamforming. The paper begins with a longterm vision for intelligent spectrum awareness across wide bands and multi-directions with multi-chiplet system in package hardware acceleration of both beamforming, Fourier and AI/ML algorithms, followed by a focus account of specific progress with digital architectures and real-time prototype implementations across the 5.7-5.8 GHz band for 32 RF beams. A real-time temporal frequency resolution of 100 kHz across 100 MHz of baseband bandwidth is achieved, across 32 simultaneous fully-digital RF-beams, using a Xilinx Sx475 FPGA implementation. Details of multiplierless approximate DFT beamformers, automated modulation recognition algorithms using AI/ML, analog channelization, spectrum sensing and perception architectures are also discussed. Over-the-air experiments using the RadioML.2018.a dataset confirmed both single source accuracy (better than 97%) and impact of multi-beams on AI/ML performance for multiple strong RFI sources.

关键词： Discrete Fourier transforms Radio frequency Complexity theory Real-time systems Sensors Array signal processing Approximation algorithms Sparse matrices field programmable gate arrays Fast Fourier transforms Spectrum sensing FFT radio frequency wireless AI approximation Fourier integrated circuits FPGA chiplets

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Front-End Electronics Design for the Transition Radiation Detector Prototype in the HERD

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 653-660页

作者： Zhu, Jieyu Yang, Haibo Su, Yangzhou Liu, Xiwen Chen, Ran Wang, Hui Wei, Ping Dai, Cong Xie, Haoqing Liu, Hongbang Hu, Huijun Zhao, Chengxin Chinese Acad Sci Inst Modern Phys Lanzhou 730000 Peoples R China Univ Chinese Acad Sci Sch Nucl Sci & Technol Beijing 100049 Peoples R China Adv Energy Sci & Technol Guangdong Lab Huizhou 516003 Peoples R China Guangxi Univ Sch Phys Sci & Technol Guangxi Key Lab Relativist Astrophys Nanning 530004 Peoples R China Cent China Normal Univ Key Lab Quark & Lepton Phys MOE PLAC Wuhan 430079 Peoples R China

The high-energy cosmic radiation detection facility (HERD) is a part of the Chinese Cosmic Lighthouse Program in China space station (CSS), which is planned for launch in 2027. The HERD is expected to operate for ten years in orbit, and it will be able to indirectly detect dark matter, measure cosmic rays, and observe high-energy gamma rays. As a subdetector of the HERD, a transition radiation detector (TRD) has the main scientific goal of calibrating the electromagnetic calorimeter (CALO) at the TeV energy range, improving the measurement accuracy of the CALO, and detecting astronomical phenomena of high-energy gamma rays. In this work, we designed the front-end electronics (FEEs) as a standard readout unit for the TRD prototype in the HERD. The FEE uses four SAMPA application-specific integrated circuits (ASICs) for 128 detector signal readouts, realizing a high-speed, low-power, and high-reliability data acquisition system. The FEE receives trigger signals and serial commands from the back-end electronics (BEEs) using the universal asynchronous receiver transmitter (UART) protocol via an RS-422 bus and replies to the BEE, providing appropriate remote environmental and field-programmable gate array (FPGA) status parameters. In addition, the FEE sends detector scientific data and clock signals via a low-voltage differential signaling (LVDS) bus at 80 Mb/s with a dual-channel hot backup. According to the results of the electrical tests on the electronics, the channel's root mean square (rms) noise is less than 1.7 fC, and the linearity is better than 0.2%. In addition, a beam test is performed on the super proton synchrotron (SPS) and proton synchrotron (PS) terminals of the European Organization for Nuclear Research (CERN) to verify the electronic performance of the proposed system. The results show that the proposed FEE can meet the readout requirements of the TRD prototype and can accurately obtain the energy spectrum of muons and electrons.

关键词： Detectors Circuits Cosmic rays Photonics Radiation detectors Prototypes Physics field programmable gate arrays Protons Monitoring Front-end electronics (FEEs) high-energy cosmic radiation detection facility (HERD) SAMPA transition radiation detector (TRD)

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Mixed-Level Emulation of Asynchronous Circuits on Synchronous FPGAs

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2025年第4期44卷 1516-1528页

作者： Dashkin, Ruslan Manohar, Rajit Yale Univ Comp Syst Lab New Haven CT 06520 USA

Delivering an FPGA-based emulation model to the software and hardware development teams is one of the crucial steps in the chip design process. The parallelism available on the FPGA gives a performance boost necessary to speed up development and verification processes and benefits both hardware and software engineers. However, this step is challenging in the asynchronous circuits design flow due to the limitations of the commercially available FPGA platforms and electronic design automation (EDA) tools. We present a comprehensive solution to the problem of asynchronous design emulation on synchronous FPGAs by extending prior work for emulating gate-level asynchronous designs (Hoare, 1978). Our framework supports asynchronous designs described at the behavioral level in the communicating hardware processes language, the gate level, and hybrid designs that combine the two. We also support designs where parts of the system use natively synchronous logic. We show that our model for behavioral emulation is up to $3\times 10<^>{5}$ faster than CPU-based simulation and up to $1.96\times $ faster than the gate-level emulation model of the same design. We evaluate our toolchain using three real-world asynchronous design examples. We present a case study where we use our flow to emulate an asynchronous CPU on the synchronous FPGA and use this hardware to boot a real-time operating system, Zephyr RTOS. In this example, FPGA I/O interfaces use synchronous Verilog IP, and the RISC-V core model is generated from the asynchronous design.

关键词： field programmable gate arrays Cogeneration Logic gates Emulation Hardware Protocols Logic Integrated circuit modeling Syntactics Synchronization Asynchronous VLSI FPGA prototyping

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Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application

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IEEE ACCESS 2025年 13卷 50394-50410页

作者： De Castro, Manuel Osorio, Roberto R. Andujar, Francisco J. Carratala-Saez, Rocio Torres, Yuri Llanos, Diego R. Univ Valladolid Dept Comp Sci Campus Miguel Delibes Valladolid 47011 Spain Univ A Coruna CITIC Comp Architecture Grp Campus Elvina S-N La Coruna 15008 Spain Univ Valencia Dept Informat Valencia 46010 Spain

With the growing popularity of FPGA-based accelerators in HPC applications, new challenges have emerged, particularly in terms of programming and portability. This paper provides an overview of the current state of FPGA tools and their limitations. This study evaluates the performance and portability of two frameworks, SYCL and OpenCL, for developing HPC FPGA solutions. The case of porting a highly-parallel application to FPGAs is studied. First, na & iuml;ve, low-development-effort implementations are presented using both ND-range and single-task types of kernels, and their performance is evaluated. Subsequently, an optimized FPGA-centric approach is presented and assessed using metrics from the compilation framework. Finally, the different approaches presented are implemented using OpenCL and SYCL and their performance is evaluated. Results reveal that ND-range kernels offer high portability for highly parallel applications, while single-task codes exhibit significantly lower portability. Additionally, SYCL struggles to generate efficient hardware architectures for this kind of application when described as single-task codes, although its performance when following the ND-range approach is surprisingly high.

关键词： field programmable gate arrays Kernel Programming Codes Instruction sets Hardware Fluid dynamics Pipeline processing Europe Computational modeling Data parallelism FPGA HLS OpenCL portability SYCL

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High-Level Synthesis for FPGAs-A Hardware Engineer's Perspective

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IEEE ACCESS 2025年 13卷 28574-28593页

作者： Lahti, Sakari Hamalainen, Timo D. Tampere Univ Fac Informat Technol & Commun Sci Tampere 33720 Finland

The recent decades have witnessed unprecedented advances in the complexity of digital hardware systems, yet their design methods are still mostly based on manual register-transfer level (mRTL) languages such as VHDL and Verilog, introduced in the 1980s. While allowing exact system description, these languages have low productivity and require special expertise. High-level synthesis (HLS) promises to increase the productivity of hardware design by allowing system description from abstract, timeless source code, which is synthesized into optimized RTL code by an HLS tool according to technological constraints. However, HLS is still seen as somewhat immature technology with a non-consolidated offering of tools with varying features. Furthermore, the quality of results (QoR) of HLS is seen to be worse than with mRTL methods. This study sheds light on the status of HLS today. The emphasis is on field-programmable gate arrays (FPGAs) that allow fast development cycles. The study briefly covers the history of HLS, describes the HLS design flow, and lists the benefits and remaining challenges. The offering of current commercial and academic HLS tools is surveyed along with their features. A literature survey covering academic articles published between 2017 and 2024 on the QoR and productivity of HLS is presented. The results show that a gap of some margin still exists between the QoR of the HLS and mRTL methods. However, in productivity, HLS clearly outcompetes mRTL. Based on the study, several recommendations are made for HLS tool developers to close the QoR gap and accelerate the adoption of the method.

关键词： Design tools field programmable gate arrays high-level synthesis high-level synthesis productivity productivity quality- of-results quality- of-results

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All-Digital Device-Compatible Real-Time Physical Layer Secure Transmission Based on Delta-Sigma Modulation

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JOURNAL OF LIGHTWAVE TECHNOLOGY 2025年第3期43卷 1238-1249页

作者： Zhong, Linsheng Zhao, Ruiyan Qiu, Tian Wang, Yuanxiang Luo, Hanwen Dai, Xiaoxiao Cheng, Mengfan Deng, Lei Liu, Deming Wang, Shixiang Gao, Kailin Peng, Yang Zhang, Bin Fan, Zhiwen Du, Ping Mei, Liang Xu, Junbo Wang, Yaqin Yang, Qi Huazhong Univ Sci & Technol Sch Opt & Elect Informat SOEI Wuhan 430074 Peoples R China Bianfu Optoelec Technol Co Ltd Wuhan 430074 Peoples R China Huazhong Univ Sci & Technol Sch Cyber Sci & Engn Wuhan 430074 Peoples R China Fiberhome Telecommun Technol Co Ltd Wuhan 430074 Peoples R China

A novel physical layer digital encryption optical transmission method based on delta-sigma modulation is proposed and implemented using field programmable gate arrays (FPGA) for real-time transceivers. This approach converts ultra-high-order ciphertext, encrypted by a first-layer pseudorandom matrix, into 2-level signals via delta-sigma modulator (DSM), enabling all-digital transceiver operation with commercial optical transmission network. By employing a dynamically perturbed parameter matrix, the quantization noise introduced by the DSM is randomized, achieving a secondary masking of the ultra-high-order ciphertext. This method shares conceptual security principles with quantum noise stream cipher (QNSC) but focuses on enhancing device compatibility for physical layer secure optical transmission systems and removes the necessity for additional clock links often required by QNSC and most digital domain secure transmission technologies. In the experiment, the proposed system demonstrated bidirectional quantization noise masking physical layer secure transmission on a coarse wavelength division multiplexing (CWDM) grid, achieving a plaintext capacity of 8 x 10 Gb/s. Subsequently, real-time long-haul transmission was achieved using commercial coherent optical terminal unit (OTU4E) modules. In a 1000 km link, a 96-grid system covering the entire C-band was employed, with 9 grids measured at equal intervals across the band. Each measured grid occupied 50 GHz frequency range and achieved a plaintext transmission rate of 24.88 Gbps. This demonstrates that a potential capacity-distance product of 2.4 Pb/skm can be achieved.

关键词： Real-time systems Encryption Noise Transceivers Physical layer Optical noise High-speed optical techniques field programmable gate arrays Quantization (signal) Optical network units Delta-sigma modulation field programmable gate arrays (FPGA) noise masking physical layer secure real-time

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L1Topo: The Level-1 Topological Processor for ATLAS Phase-I Upgrade and Its Firmware Evolution for Use Within the Phase-II Global Trigger

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 392-399页

作者： Filimonov, Viacheslav Johannes Gutenberg Univ Mainz Inst Phys D-55128 Mainz Germany

The increased instantaneous luminosity of the Large Hadron Collider (LHC) in Run 3 brings the need for the upgrade of the A Toroidal LHC Apparatus (ATLAS) trigger system. The newly commissioned Phase-I L1Topo system, which replaces its Phase-0 predecessor, processes data from the feature extractors (FEXes) and the upgraded muon to central trigger processor interface (MUCTPI) to perform topological and multiplicity triggers. The L1Topo system consists of three ATCA modules, each hosting two processor field programmable gate arrays (FPGAs) (Xilinx Ultrascale+9P). The L1Topo firmware is composed of a large number of sort/select, decision, and multiplicity algorithms, that are automatically assembled and configured based on the provided trigger menu. For the high-luminosity LHC (HL-LHC), the Phase-I L1Topo system will be replaced by a Global Trigger, a time-multiplexed system, which concentrates the data of a full event into a single FPGA. In order to match the new operational environment, the fully synchronous, very low latency (new data arriving every 25 ns), parallel implementation [similar to 2.5M look-up tables (LUTs)] of the Phase-I topological firmware is being adapted to a significantly higher latency budget (new data arriving every 1.2 mu s) and a substantially tighter resource budget (similar to 100k LUTs). The main challenge is to allow for multiple working points of the utilized resources and latency for each algorithm. A detailed overview of the Phase-I L1Topo hardware and firmware is provided. Preliminary performance results achieved by the Phase-I L1Topo together with a description of the challenges found during the commissioning process are included. Phase-II-related firmware adaptations are also discussed.

关键词： Microprogramming field programmable gate arrays Hardware Optical fibers Detectors Software algorithms Mesons A Toroidal LHC Apparatus (ATLAS) field programmable gate array (FPGA) Large Hadron Collider (LHC) topological trigger

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Radar-aided reconfigurable intelligent surface for vehicular wireless communication

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OPTICS EXPRESS 2025年第5期33卷 11996-12011页

作者： Wang, Kun Tian, Yuze Yan, Tai Wang, Bo Shi, Xintong Xiong, Jie Yu, Wen Jin, Jing Lin, Hai Tang, Wenxuan Cent China Normal Univ Coll Phys Sci & Technol Wuhan 430079 Peoples R China South China Univ Technol Sch Future Technol Guangzhou 510641 Peoples R China Southeast Univ State Key Lab Millimeter Waves Nanjing 210096 Peoples R China Southeast Univ Inst Electromagnet Space Nanjing 210096 Peoples R China

In the intricate traffic environment of modern cities, challenges like insufficient wireless signal coverage and obstructed propagation links between base stations (BS) and vehicles are prevalent. Meanwhile, reconfigurable intelligent surface (RIS) offers what we believe to be a novel solution relying on its robust real-time control over electromagnetic (EM) waves, providing a new approach to achieving intelligent transportation and vehicle connectivity. In this paper, we propose a radar-aided intelligent wireless communication system for dynamic beam tracking. The system leverages frequency-modulated continuous wave (FMCW) radar to detect the location information of the surrounding vehicles, a pre-trained artificial neural network (ANN) combined with control boards to generate the voltage coding sequence of the desired deflection direction, and the dual-polarized RIS to realize intelligent beam tracking and wireless communication. We design a 3-bit dual-polarized RIS, consisting of 256 (16 x 16) independently controllable units, running at 3.5 GHz, and develop a high-speed control board to ensure real-time refresh of the voltage coding sequence. Comparative experiments are conducted in three different environments. The experiments consistently demonstrate that, with the assistance of the radar, the RIS can achieve dynamic beam tracking without manual intervention. The system can effectively improve wireless signal strength and communication stability, providing a new viable approach for the development of intelligent vehicular networking. (c) 2025 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement

关键词： Deep learning field programmable gate arrays Machine vision Neural networks Phase shift Visible light communications

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