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FPGA Implementation of Staged Projection Refining Multiple Orthogonal Matching Pursuit Algorithm for Compressed Sensing

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第5期33卷 1334-1347页

作者： Liu, Sujuan Liang, Yichen Zhang, Zixing Wan, Peiyuan Beijing Univ Technol Coll Microelect Beijing 100124 Peoples R China

Reconstruction algorithms are an integral part of compressed sensing (CS) theory, which can reliably reconstruct the original signal from the low-dimensional compressed signal. The orthogonal matching pursuit (OMP) algorithm has been widely studied and extensively selected in hardware implementations. However, the low reconstruction success rate of the OMP algorithm under high sparsity conditions has led to the proposal and application of more reconstruction algorithms in hardware implementations. In this article, a staged projection refining multiple OMP (SPR-MOMP) algorithm is proposed based on the OMP algorithm. This algorithm improves the reconstruction accuracy by refining the support set using a staged backtracking strategy. It also employs a multiple-atom selection strategy for parallel expansion of the support set, ensuring reconstruction efficiency. The reconstruction simulation demonstrates that the SPR-MOMP algorithm achieves a higher reconstruction success rate than the OMP algorithm, with fewer iterations. A hardware architecture applying the SPR-MOMP algorithm is designed and implemented on a Virtex UltraScale+ field-programmable gate array (FPGA) with N = 1024, M = 256, and K = 36. The proposed architecture achieves a reconstruction signal-to-noise ratio (RSNR) of 44.27 dB, with 20-bit data width and 15-bit fractional width. The maximum clock frequency of the architecture is 200 MHz, enabling reconstruction within 276.6 mu s. The proposed architecture achieves a lower dynamic power consumption of 1929 mW.

关键词： Computer architecture Matching pursuit algorithms Hardware field programmable gate arrays Image reconstruction Heuristic algorithms Backtracking Reconstruction algorithms Signal processing algorithms Sensors Compressed sensing (CS) field-programmable gate array (FPGA) hardware reconstruction orthogonal matching pursuit (OMP) QR decomposition (QRD)

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Discrete Two-Heterogeneous-Neuron HNN and Chaos-Based Hardware Poisson Encoder

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IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS 2025年第2期21卷 1862-1871页

作者： Bao, Han Xi, Minqi Tang, Haigang Zhang, Xi Xu, Quan Bao, Bocheng Changzhou Univ Wang Zheng Sch Microelect Changzhou 213159 Peoples R China

Nonlinear activation function is the most essential factor that enables Hopfield neural networks (HNNs) to generate complex dynamics. However, less attention has been paid to the activation function. In this article, we propose a simple discrete model of self-connectionless HNN in which two heterogeneous neurons have different activation functions of sine and hyperbolic tangent. By theoretical and numerical methods, we explore coexisting bifurcation behaviors induced by Neimark-Sacker bifurcations and multifolded hyperchaotic attractors caused by multiple fixed points with different stability. We also evaluate the randomness of these multifolded hyperchaotic sequences and implement the discrete model on field programmable gate array (FPGA) hardware device. In brief, this discrete model with simple algebraic equations has the simplest connection structure under the two-heterogeneous-neuron HNN framework, but it can generate various multifolded hyperchaotic attractors with high randomness. Additionally, based on FPGA hardware device, a chaos-based hardware Poisson encoder is developed to implement the reconstruction of gray image.

关键词： Bifurcation Neurons Mathematical models Hardware Orbits field programmable gate arrays Brain modeling Informatics Encryption Data models Coexisting bifurcation behaviors discrete model fixed point Hopfield neural network (HNN) multifolded hyperchaotic attractor Poisson encoder

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Autofocus Algorithm for Real-Time Correction of Residual RCM Based on ANCPS

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IEEE TRANSACTIONS ON GEOSCIENCE AND REMOTE SENSING 2025年 63卷

作者： Xie, Yi Chen, Longyong Zhang, Fubo Xu, Yihao Yang, Ling Chinese Acad Sci Aerosp Informat Res Inst Natl Key Lab Microwave Imaging Beijing 100190 Peoples R China Univ Chinese Acad Sci Sch Elect Elect & Commun Engn Beijing 100049 Peoples R China Beijing Inst Elect Syst Engn Beijing 100854 Peoples R China

With synthetic aperture radar (SAR) systems being developed with miniaturization, lightweight, low-cost, high-resolution, and real-time capabilities, the scope of their application has expanded to some lightweight platforms that cannot carry a high-precision position and orientation system (POS) and whose trajectories are susceptible to interference. This often results in residual range cell migration (RCM) exceeding several or even dozens of range resolution cells, which notably degrades the performance of traditional autofocus algorithms and seriously affects the quality of real-time imaging. Considering this, we propose a real-time residual RCM correction scheme based on the autocorrelated normalized cross-power spectrum (ANCPS). First, the range-compressed image is segmented into blocks based on the azimuth and range. The ANCPS is then used to estimate the optimal residual RCM for each subblock. Second, the optimal segment is selected from the residual RCM curve fragments estimated by various subblocks. Finally, the residual RCM fragments are spliced and filtered to correct the complete data. When the algorithm is deployed on a GPU platform, it only takes 1.39 s to process an 8 x 40 K high-resolution original SAR image, and the calculation time is reduced by 94.6% compared with only using a CPU for calculation. The experimental results demonstrate that the proposed residual RCM correction scheme has good convergence, can achieve subpixel residual RCM compensation without iteration and interpolation, has a simple calculation process, is efficient, and has strong parallelism. It is thus suitable for deployment in GPUs and is conducive to realizing real-time SAR autofocus at a low cost and with a high resolution.

关键词： Image segmentation Imaging Graphics processing units Radar imaging Apertures Real-time systems Robustness Trajectory Synthetic aperture radar field programmable gate arrays Autocorrelated normalized cross-power spectrum (ANCPS) correction of range cell migration (RCM) parallel computing synthetic aperture radar (SAR) real-time autofocus

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Design of a Common High-Performance Data Acquisition System for Physics Experiments at HIAF

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 713-719页

作者： Zhang, Honglin Yang, Haibo Liu, Chengcheng Sun, Wenchao Liao, Shun Li, Xianqin Zhu, Jieyu Ran, Hu Zhao, Chengxin Chinese Acad Sci Inst Modern Phys Lanzhou 730000 Peoples R China Adv Energy Sci & Technol Guangdong Lab Huizhou 516003 Peoples R China Univ Chinese Acad Sci Sch Nucl Sci & Technol Beijing 100049 Peoples R China Liaoning Acad Mat Shenyang 110167 Peoples R China Lanzhou Univ Sch Informat Sci Engn Lanzhou 730000 Peoples R China Chengdu Univ Technol Coll Math & Phys Chengdu 610059 Peoples R China

In this article, a common high-performance data acquisition (DAQ) system for High Intensity heavy-ion Accelerator Facility (HIAF) centered with a new common data acquisition unit (CDAU) is introduced. The system includes eight fiber optic transmission channels connected to front-end (FE) electronics, delivering data bandwidth up to 10 Gbps per channel, along with highly scalable FPGA mezzanine card (FMC) and general-purpose input/output (GPlO) interfaces. Moreover, a peripheral component interconnect Express 2.0x8 protocol (bandwidth up to 40 Gbps) is implemented to facilitate data exchange with the data center. Laboratory characterization revealed that the bit error rate (BER) of the fiber optic transmission channel is relatively low, at 5.8 x 10(-16) at a 10-Gbps transmission rate. In addition, the read/write rates of the PCI Express (PCIe) interface demonstrated stability, with the read speed consistently maintained at 3400 MB/s and an error rate as low as 2.09 x 10(-15) , while the write speed is stable at 3420 MB/s, with an error rate reaching 2.14 x 10(-15) . Subsequent experiments involved measuring 137Cs radiation source and cosmic ray spectra using various scintillator detectors, achieving the energy resolution of 1.12% and 21.34%. Overall, the DAQ system proved robust and stable in practical scenarios in HIAF. This article examines the DAQ system's design and performance.

关键词： Data acquisition field programmable gate arrays Physics Engines Clocks Bandwidth Table lookup Software Protocols Nuclear physics Data acquisition (DAQ) system field-programmable gate array (FPGA) High Intensity heavy-ion Accelerator Facility (HIAF) high-speed data transmission peripheral component interconnect Express (PCIe) scintillator detector

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Front-End Electronics Design for the Transition Radiation Detector Prototype in the HERD

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 653-660页

作者： Zhu, Jieyu Yang, Haibo Su, Yangzhou Liu, Xiwen Chen, Ran Wang, Hui Wei, Ping Dai, Cong Xie, Haoqing Liu, Hongbang Hu, Huijun Zhao, Chengxin Chinese Acad Sci Inst Modern Phys Lanzhou 730000 Peoples R China Univ Chinese Acad Sci Sch Nucl Sci & Technol Beijing 100049 Peoples R China Adv Energy Sci & Technol Guangdong Lab Huizhou 516003 Peoples R China Guangxi Univ Sch Phys Sci & Technol Guangxi Key Lab Relativist Astrophys Nanning 530004 Peoples R China Cent China Normal Univ Key Lab Quark & Lepton Phys MOE PLAC Wuhan 430079 Peoples R China

The high-energy cosmic radiation detection facility (HERD) is a part of the Chinese Cosmic Lighthouse Program in China space station (CSS), which is planned for launch in 2027. The HERD is expected to operate for ten years in orbit, and it will be able to indirectly detect dark matter, measure cosmic rays, and observe high-energy gamma rays. As a subdetector of the HERD, a transition radiation detector (TRD) has the main scientific goal of calibrating the electromagnetic calorimeter (CALO) at the TeV energy range, improving the measurement accuracy of the CALO, and detecting astronomical phenomena of high-energy gamma rays. In this work, we designed the front-end electronics (FEEs) as a standard readout unit for the TRD prototype in the HERD. The FEE uses four SAMPA application-specific integrated circuits (ASICs) for 128 detector signal readouts, realizing a high-speed, low-power, and high-reliability data acquisition system. The FEE receives trigger signals and serial commands from the back-end electronics (BEEs) using the universal asynchronous receiver transmitter (UART) protocol via an RS-422 bus and replies to the BEE, providing appropriate remote environmental and field-programmable gate array (FPGA) status parameters. In addition, the FEE sends detector scientific data and clock signals via a low-voltage differential signaling (LVDS) bus at 80 Mb/s with a dual-channel hot backup. According to the results of the electrical tests on the electronics, the channel's root mean square (rms) noise is less than 1.7 fC, and the linearity is better than 0.2%. In addition, a beam test is performed on the super proton synchrotron (SPS) and proton synchrotron (PS) terminals of the European Organization for Nuclear Research (CERN) to verify the electronic performance of the proposed system. The results show that the proposed FEE can meet the readout requirements of the TRD prototype and can accurately obtain the energy spectrum of muons and electrons.

关键词： Detectors Circuits Cosmic rays Photonics Radiation detectors Prototypes Physics field programmable gate arrays Protons Monitoring Front-end electronics (FEEs) high-energy cosmic radiation detection facility (HERD) SAMPA transition radiation detector (TRD)

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Computational optical imaging: on the convergence of physical and digital layers

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OPTICA 2025年第1期12卷 113-130页

作者： Wang, Zhaoqiang Peng, Yifan Fang, Lu Gao, Liang Univ Calif Los Angeles Dept Bioengn Los Angeles CA 90095 USA Univ Hong Kong Dept Elect & Elect Engn & Comp Sci Hong Kong Peoples R China Tsinghua Univ Dept Elect Engn Beijing Peoples R China

Optical imaging has traditionally relied on hardware to fulfill its imaging function, producing output measures that mimic the original objects. Developed separately, digital algorithms enhance or analyze these visual representations, rather than being integral to the imaging process. The emergence of computational optical imaging has blurred the boundary between hardware and algorithm, incorporating computation in silico as an essential step in producing the final image. It provides additional degrees of freedom in system design and enables unconventional capabilities and greater efficiency. This mini-review surveys various perspectives of such interactions between physical and digital layers. It discusses the representative works where dedicated algorithms join the specialized imaging modalities or pipelines to achieve images of unprecedented quality. It also examines the converse scenarios where hardware, such as optical elements and sensors, is engineered to perform image processing, partially or fully replacing computer-based counterparts. Finally, the review highlights the emerging field of end-to-end optimization, where optics and algorithms are co-designed using differentiable models and task-specific loss functions. Together, these advancements provide an overview of the current landscape of computational optical imaging, delineating significant progress while uncovering diverse directions and potential in this rapidly evolving field. (c) 2025 Optica Publishing Group under the terms of the Optica

关键词： Computational imaging field programmable gate arrays Imaging systems Integral imaging Optical elements Systems design

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Real-Time Intra-Symbol Two-Stage Bit-Class Distribution Matcher-Based PS-64QAM DMT Transceiver for W-Band Wireless Transmission

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JOURNAL OF LIGHTWAVE TECHNOLOGY 2025年第4期43卷 1759-1772页

作者： Zhang, Long Yu, Jianjun Wang, Kaihui Zhu, Zonghui Yang, Xiongwei Jiang, Luhan Liu, Jiaxuan Sang, Bohan Wang, Chen Long, Jianyu Sun, Xinda Meng, Yuanxiao Gou, Yumeng Tan, Jingwen Wang, Yikai Chen, Yu Ding, Junjie Zhao, Li Zhou, Wen Zhu, Min Yu, Jianguo Fudan Univ State Key Lab AS & Syst Key Lab Informat Sci Electromagnet Waves MoE Shanghai 200433 Peoples R China Fudan Univ Sch Informat Sci & Technol Shanghai 200433 Peoples R China Southeast Univ Purple Mt Labs Nanjing 211111 Peoples R China Nanjing Univ Posts & Telecommun Nanjing 210003 Peoples R China Beijing Univ Posts & Telecommun Beijing 100191 Peoples R China

The utilization of probabilistic shaping (PS) techniques effectively mitigates the average power of the transmitted signal by optimizing modulation mapping schemes, which helps to improve the resistance of the wireless transmission system to the nonlinear effect induced by envelope detection. In this work, we have experimentally demonstrated FPGA-based real-time photonics-assisted W-band with envelope detection 23 Gb/s PS 64-ary quadrature amplitude modulation (64QAM) discrete multi-tone (DMT) signals over 40.5-m wireless link. In addition, an intra-symbol two-stage bit-weighted distribution matching-based PS-64QAM scheme was implemented based on FPGA to alleviate nonlinear damage caused by envelope detector. This PS-64QAM scheme has the advantages of no complex multiplication, division operations and low hardware implementation complexity. According to experimental results, by adopting our proposed PS-64QAM scheme, the receiver sensitivity can be significantly improved. This study demonstrates the attainment of the greatest wireless range to date through FPFA-based real-time photonics millimeter wave envelope detection for wireless communication. The results underscore the feasibility of integrating millimeter wave photonics, electronics, and advanced DSP algorithms to accomplish high-speed wireless communication over long distances in real time. This will provide important assistance for our future work in real-time photonics- assisted millimeter wave wireless communication.

关键词： Wireless communication Photonics Wireless sensor networks Symbols Real-time systems field programmable gate arrays Optical receivers High-speed optical techniques Quadrature amplitude modulation Probability distribution DMT envelope detection FPGA-based real-time intra-symbol two-stage bit-weighted distribution matching W-band

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FPGA Based MRI Brain Tumor Segmentation Using Modified FCM Method

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2025年 1-20页

作者： Deepesh, B. Latha, T. St Xaviers Catholic Coll Engn Dept Elect & Commun Engn Nagercoil India

Detecting brain tumors with Magnetic resonance imaging (MRI) is vital for early diagnosis, giving patients a better chance for effective treatment by helping doctors pinpoint and understand the tumor. MRI technology is crucial for identifying tumor growth, enabling patients to receive timely treatment whether the growth is malignant or not. This work proposes an optimized FPGA version of a modified Fuzzy C-Means (FCM) algorithm with three clusters segmenting the brain tumors based on their pixel intensity deviation. The modification involves moving the cluster centers and varying the cluster weights with the mean intensity of the cluster of all the pixels, improving the accuracy. Block RAM of the FPGA device is utilized to store the input, intermediate, and output data to improve timing performance. A pipeline architecture is adopted for all units, including membership calculation, division unit, and centroid updating unit. Pipelining enables these units to work in parallel and thus reduce delays and allow a constant stream of data, which enhances the FCM design performance. The hardware implementation and verification are carried out on the Xilinx XC3S500E-4FG320 FPGA and Zynq UltraScale + ZCU104 platforms, while the Application-Specific Integrated Circuit (ASIC) implementation is performed using 45 nm technology library. The modified FCM technique outperforms conventional methods with a 108.271 MHz operating frequency, 0.859W power consumption, and hardware utilization of 8471 LUTs, 70 DSPs, and 3,897 FFs for 256 x 256 design. ASIC chip occupied 3 x 3 mm of core area and operates at a frequency of 253 MHz with power consumption of 161 mW.

关键词： Magnetic resonance imaging Pixel intensity deviation Modified Fuzzy C-Means field programmable gate arrays Block RAM

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Lightweight AES Design for IoT Applications: Optimizations in FPGA and ASIC With DFA Countermeasure Strategies

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IEEE ACCESS 2025年 13卷 22489-22509页

作者： Ahmed, Salman Ahmad, Nabihah Shah, Nasir Ali Abro, Ghulam E. Mustafa Wijayanto, Ardhi Hirsi, Abdinasir Altaf, Abdul Rehman Univ Tun Hussein Onn Malaysia Fac Elect & Elect Engn Parit Raja 86400 Johor Malaysia Univ Tun Hussein Onn Malaysia Fac Elect & Elect Engn VLSI & Embedded Technol VEST Focus Grp Parit Raja 86400 Johor Malaysia Politecn Torino Dept Elect & Telecommun DET I-10129 Turin Italy King Fahd Univ Petr & Minerals KFUPM Interdisciplinary Res Ctr Aviat & Space Explorat I Dhahran 31261 Saudi Arabia Univ Sebelas Maret Informat Dept Surakarta 57126 Indonesia Johns Hopkins Aramco Healthcare JHAH Dhahran 34465 Saudi Arabia

With the increasing interconnectivity of devices, the Internet of Things (IoT) has revolutionized the industry and daily life. However, the proliferation of IoT devices has also increased security risks, which requires robust protection mechanisms for sensitive data and critical infrastructure. The Advanced Encryption Standard (AES) remains the benchmark for securing IoT systems while balancing low power consumption, minimal area usage, and moderate throughput with high security. This paper offers a comprehensive review of the latest lightweight AES architectural designs, including optimizations to the Substitution Box (S-Box), Sub-Bytes, Shift Rows, Mix Columns, and Add Round Key steps, assessing their impact on gate count, area, maximum frequency, power consumption, and throughput in field programable gate arrays (FPGA) and Application-specific integrated circuit (ASIC) implementations. In addition, this study addresses vulnerabilities in lightweight AES cryptographic hardware to side-channel attacks (SCA), specifically focusing on Differential Fault Analysis (DFA). In addition, the analysis explores fault scenarios, rounds, and injection positions to assess the severity of the fault. In addition, the study reviews DFA countermeasures that highlight fault detection methods, error detection levels, protection positions, and associated design overheads such as area, frequency, and throughput penalties, with special consideration for resource-constrained IoT devices. This study identifies critical gaps in lightweight AES and security challenges while discussing countermeasures that balance security with design efficiency. Finally, this study provides valuable insights for finding research directions to strengthen the robustness of AES in lightweight IoT environments.

关键词： Internet of Things field programmable gate arrays Security Optimization Hardware Encryption Surveys Cryptography Circuit faults Standards Advanced encryption standard (AES) application specific integrated circuits (ASIC) differential fault analysis (DFA) field programmable gate arrays (FPGA) Galois field (GF) Internet of Things (IoT) lightweight cryptography mix column optimization S-box shift rows optimization

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Design and implementation of on-board high reliability FPGA on-orbit reconfiguration

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MEASUREMENT & CONTROL 2025年

作者： Yu, Longkun Yang, Shuai Wen, Xiangyang Liu, Jiacong Yan, Jiarong Li, Xinqiao Xiong, Shaolin Lu, Zhigang Gong, Ke Liu, Yaqing An, Zhenghua Zhang, Dali Liu, Xiaojing Zhao, Xiaoyun Zhang, Fan Wang, Jinzhou Gao, Min Xu, Yanbing Sun, Xilei Wang, Hui Zheng, Chao Feng, Peiyi Wang, Chenwei Zhang, Yanqiu Zhang, Peng Ding, Zhiqiang Li, Yongye Zhang, Chenxing Wang, Jing Chen, Li Nanchang Univ Sch Informat Engn Nanchang Jiangxi Peoples R China Nanchang Univ Sch Adv Mfg Nanchang Jiangxi Peoples R China Chinese Acad Sci Inst High Energy Phys Key Lab Particle Astrophys 19B Yuquan Rd Beijing 100049 Peoples R China Univ Chinese Acad Sci Chinese Acad Sci Beijing Peoples R China Chengdu Univ Technol Coll Nucl Technol & Automat Engn Chengdu Peoples R China Tongji Univ Coll Elect & Informat Engn Shanghai Peoples R China

The electronic system of the multi-chip combined control architecture satellites often requires an on-orbit reconfiguration capability for field programmable gate arrays (FPGAs). The purpose is to provide program backup and rapid on-orbit reconfiguration of the FPGA once suffering single particle event. Spacecrafts in low Earth orbit (LEO) are subject to the South Atlantic Anomaly (SAA), while deep space spacecrafts operate in an environment constrained by high levels of particles and radiation, intermittent communications, and limited resources, which together pose a significant challenge to the reliable operation of spacecraft electronics. Multi-chip flash process control is an effective solution to this challenge. In this work, we propose and implement a design for the GTM payload onboard the deep space DRO-A satellite, using an MCU, an FPGA, and flash memory, where the MCU is used to communicate with external data, write the FPGA bitstream frames to the flash, and serves as the control core for the data interaction between the off-chip flash memory and the FPGA via SPI. This configuration ensures the independence of the data interaction since the FPGA is not physically connected to the flash. The software uses a three-mode redundancy system, file CRC checksums, and data sending/receiving checksums to increase reliability. Prior to the launch of the DRO-A satellite, the program was comprehensively tested on the GTM payload. This design is important for extending the spacecraft and payload operational life under extremely harsh conditions.

关键词： Aerospace electronics field programmable gate arrays SPI slave reconfiguration data handling

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