检索结果-内蒙古大学图书馆

FPGA Implementation of a Multi-PRNG Based on a Multiscroll Chaotic Hopfield Neural Network

IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS 2025年第4期21卷 3097-3106页

作者： Gonzalez, Jeferson Andres Garzon Rangel-Magdaleno, Jose de Jesus Munoz-Pacheco, Jesus Manuel Natl Inst Astrophys Opt & Elect INAOE Elect Dept Digital Syst Grp Puebla 72840 Mexico Benemerita Univ Autonoma Puebla Fac Elect Sci Puebla 72570 Mexico

Pseudorandom number generators (PRNGs) are fundamental components in cryptographic algorithms. The new concept of multi-PRNG introduced in this article consists of a unique generator capable of producing multiple streams of pseudorandom numbers. Multiscroll chaotic systems are known for generating multiple scrolls within a single attractor. With the aforementioned this article introduces a novel field-programmable gate array (FPGA) implementation of a multi-PRNG based on a multiscroll chaotic memristive Hopfield neural network (MHNN). The main contribution of this work is the generation of multiple spatially dependent PRNG streams from a chaotic multiscroll system by dividing the phase space of the attractor into sub-phase spaces. Each scroll in the multiscroll attractor functions as an independent PRNG. This innovative approach to generating multiple PRNGs from multiscroll chaotic systems is unprecedented in the existing literature. The 5-D MHNN chaotic model used in this work employs hyperbolic tangent and sine functions, which were implemented through a hardware-efficient CORDIC approach. Besides, The FPGA implementation to produce the chaotic time series leverages the Euler method with 32-bit fixed-point arithmetic, selected for its simplicity and low resource utilization. Finally, The randomness of the binary sequences produced by the multi-PRNG is rigorously validated using the NIST SP 800-22a and TestU01 suites, confirming their potential for cryptographic applications.

关键词： field programmable gate arrays Chaotic communication NIST Hardware Trajectory Throughput Memristors Generators Informatics Heuristic algorithms Cordinate rotation digital computer (CORDIC) chaotic systems field-programmable gate array (FPGA) hopfield memristive multi-pseudo-random number generator (PRNG) multiscroll neural networks

来源：评论

学校读者我要写书评

暂无评论

MTJ/CMOS-Based CLB Design for Low-Power and CPA-Resistant Secure Nonvolatile FPGA

引用

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第5期33卷 1361-1372页

作者： Nasab, Milad Tanavardi Thapliyal, Himanshu Rose, Garrett S. Univ Tennessee Dept Elect Engn & Comp Sci Knoxville TN 37996 USA

Modern applications such as the Internet of Things (IoT) devices, AI, and automotive applications widely use field-programmable gate arrays (FPGAs). However, many of these applications have limited power resources. Also, the existing FPGAs are vulnerable to side-channel attacks (SCAs) such as correlation-based power analysis (CPA) attacks. Therefore, designing low-power, CPA-resistant, and secure-by-design FPGA is required. In this article, two low-power and CPA-resistant hybrid CMOS/magnetic tunnel junction (MTJ) logic-in-memory-based configurable logic blocks (CLBs) have been proposed and compared to a state-of-the-art counterpart. The first proposed design is single output, and the second one is multioutput. The simulation results show that compared to the state-of-the-art secure CLB counterpart secured CLB (sCLB) by Zooker et al. (2020), the proposed CLB designs have 42% and 33% lower delay, 85% and 18% lower power consumption, and 86% and 63% fewer equivalent transistors. To implement one round of the PRESENT algorithm, the first and second designs have 85% and 77% fewer transistors, 42% and 33% lower delay, and 86% and 50% lower power consumption compared to their silicon-proven secure counterpart. Also, to implement convolution layers of binarized neural network (BNN), compared to this counterpart, the first and second proposed designs have 85% and 90% fewer equivalent transistors, 42% and 33% lower delay, and 86% and 79% lower power consumption. Also, the resiliency of the proposed designs against power analysis attacks has been investigated by exhaustive simulations and performing CPA attacks on PRESENT and Advanced Encryption Standard (AES) SBOX. Also, this resiliency has been investigated for different tunnel magnetoresistance ratios (TMRs) and supply voltages.

关键词： field programmable gate arrays Magnetic tunneling Table lookup Power demand Security Multiplexing Resistance Magnetic separation Logic gates Logic Configurable logic block (CLB) low-power secure field-programmable gate array (FPGA) magnetic tunnel junction (MTJ) power analysis attack spintronic

来源：评论

学校读者我要写书评

暂无评论

Realization of Zero Measurement Dead Time on FPGA-Based Time-to-Digital Converters

引用

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷

作者： Qi, Xinren Zhang, Jianfeng Wang, Yonggang Univ Sci & Technol China Dept Modern Phys State Key Lab Particle Detect & Elect Hefei 230026 Peoples R China

Although the time-to-digital converters (TDCs) implemented on field programmable gate arrays (FPGAs) have achieved considerably high measurement resolution and precision in recent years, achieving zero measurement dead time is still a challenge for some applications. The goal of this article is to design an FPGA-based TDC with zero measurement dead time without compromising other performance. Based on the conventional tapped delay line (TDL) TDC structure, the idea of our method is to enable the continuous flow of trigger signals onto the TDL and propose a powerful encoder with the capability of recognizing all trigger edges within a system clock period. Considering the inherent "bubble" problem in the TDL, the latched TDL status is first decomposed into 16 divisions, all of which identify all the trigger edges in parallel. Through a specific coincident mechanism, the trigger edges on all the divisions are matched and their positions on the TDL are encoded for output. To overcome the significant integral nonlinearity (INL) error caused by large delay deviations of delay units, online calibration tables are established to convert the positions of trigger edges into fine timestamps so that the original resolution and precision of the TDC can be maintained. The proposed TDC is implemented on a Xilinx Zynq UltraScale+ FPGA for performance evaluation. In addition to verifying the TDC function and online calibration tables, the TDC resolutions for the rising and falling edges are measured as 1.82 and 1.92 ps, respectively. By inputting the trigger signals with a higher frequency than the TDC system clock, all the rising and falling edges of trigger signals are detected with the root-mean-square (rms) measurement precisions ranging from 2 to 4.5 ps, which confirms the achievement of zero measurements dead time.

关键词： Clocks field programmable gate arrays Pulse measurements Flip-flops Delays Calibration Image edge detection Signal resolution Frequency measurement Quantization (signal) field programmable gate array (FPGA) resolution and precision tapped delay line (TDL) time-to-digital converter (TDC) zero dead time

来源：评论

学校读者我要写书评

暂无评论

A Heterogeneous and Adaptive Architecture for Decision-Tree-Based ACL Engine on FPGA

引用

IEEE TRANSACTIONS ON COMPUTERS 2025年第1期74卷 263-277页

作者： Xin, Yao Jia, Chengjun Li, Wenjun Rottenstreich, Ori Xu, Yang Xie, Gaogang Tian, Zhihong Li, Jun Guangzhou Univ Cyberspace Inst Adv Technol Guangzhou 510530 Peoples R China Guangzhou Univ Huangpu Res Sch Guangzhou 510530 Peoples R China Huawei Technol Co Ltd Beijing 100095 Peoples R China Peng Cheng Lab Shenzhen 518055 Peoples R China Technion IL-3200003 Haifa Israel Fudan Univ Sch Comp Sci Shanghai 200433 Peoples R China Chinese Acad Sci Comp Network Informat Ctr Beijing 100083 Peoples R China Tsinghua Univ Dept Automat Beijing 100084 Peoples R China

Access Control Lists (ACLs) are crucial for ensuring the security and integrity of modern cloud and carrier networks by regulating access to sensitive information and resources. However, previous software and hardware implementations no longer meet the requirements of modern datacenters. The emergence of FPGA-based SmartNICs presents an opportunity to offload ACL functions from the host CPU, leading to improved network performance in datacenter applications. However, previous FPGA-based ACL designs lacked the necessary flexibility to support different rulesets without hardware reconfiguration while maintaining high performance. In this paper, we propose HACL, a heterogeneous and adaptive architecture for decision-tree-based ACL engine on FPGA. By employing techniques such as tree decomposition and recirculated pipeline scheduling, HACL can accommodate various rulesets without reconfiguring the underlying architecture. To facilitate the efficient mapping of different decision trees to memory and optimize the throughput of a ruleset, we also introduce a heterogeneous framework with a compiler in CPU platform for HACL. We implement HACL on a typical SmartNIC and evaluate its performance. The results demonstrate that HACL achieves a throughput exceeding 260 Mpps when processing 100K-scale ACL rulesets, with low hardware resource utilization. By integrating more engines, HACL can achieve even higher throughput and support larger rulesets.

关键词： field programmable gate arrays Hardware Computer architecture Throughput Engines Decision trees Pipelines Clocks Multicore processing Computers ACL SmartNIC FPGA pipeline parallel processing

来源：评论

学校读者我要写书评

暂无评论

A Novel Security Threat Model for Automated AI Accelerator Generation Platforms

引用

IEEE ACCESS 2025年 13卷 61237-61249页

作者： Guo, Chao Shi, Youhua Waseda Univ Grad Sch Fundamental Sci & Engn Dept Elect & Phys Syst Tokyo 1698050 Japan

In recent years, the design of Artificial Intelligence (AI) accelerators has gradually shifted from focusing solely on standalone accelerator hardware to considering the entire system, giving rise to a new AI accelerator design paradigm that emphasizes full-stack integration. Systems designed based on this paradigm offer a user-friendly, end-to-end solution for deploying pre-trained models. While previous studies have identified vulnerabilities in individual hardware components or models, the security of this paradigm has not yet been thoroughly evaluated. This work, from an attacker's perspective, proposes a threat model based on this paradigm and reveals the potential security vulnerabilities of systems by embedding malicious code in the design flow, highlighting the necessity of protection to address this security gap. In exploration and generation, it maliciously leverages the exploration unit to identify sensitive parameters in the model's intermediate layers and insert hardware Trojan (HT) into the accelerator. In execution, malicious information is concealed within the control instructions, triggering the HT. Experimental results demonstrate that the proposed method, which manipulates sensitive parameters in a few selected kernels across the middle convolutional layers, successfully misclassifies input images into specified categories with high misclassification rates across various models: 97.3% in YOLOv8 by modifying only three parameters per layer in three layers, 99.2% in ResNet-18 by altering four parameters per layer in three layers and 98.1% for VGG-16 by changing seven parameters per layer in four layers. Additionally, the area overhead introduced by the proposed HT occupies no more than 0.39% of the total design while maintaining near-original performance as in uncompromised designs, which clearly illustrates the concealment of the proposed security threat.

关键词： Hardware AI accelerators Security Trojan horses Threat modeling Full stack field programmable gate arrays Focusing Closed box Analytical models Full-stack AI accelerator design deep neural networks (DNNs) hardware Trojan (HT) security threats

来源：评论

学校读者我要写书评

暂无评论

SAFE: A Scalable Homomorphic Encryption Accelerator for Vertical Federated Learning

引用

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2025年第5期44卷 1662-1675页

作者： Chen, Zhaohui Gu, Zhen Lu, Yanheng Ren, Xuanle Zhong, Ruiguang Lu, Wen-Jie Zhang, Jiansong Zhang, Yichi Wu, Hanghang Zheng, Xiaofu Liu, Heng Chu, Tingqiang Hong, Cheng Wei, Changzheng Niu, Dimin Xie, Yuan Alibaba Grp DAMO Acad Hangzhou 310023 Peoples R China Hupan Lab Hangzhou 310023 Peoples R China Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China Ant Grp Hangzhou 310000 Peoples R China

Privacy preservation has become a critical concern for governments, hospitals, and large corporations. Homomorphic encryption (HE) enables a ciphertext-based computation paradigm with strong security guarantees. In emerging cross-agency data cooperation scenarios like vertical federated learning (VFL), HE protects the data interaction from exposure to counterparts. However, computation on ciphertext has significant performance challenges due to increased data size and substantial overhead. Related work has been proposed to accelerate HE using parallel hardware, such as GPUs, FPGAs, and ASICs. However, many existing hardware accelerators target specific HE operations, such as number theoretic transform (NTT) and key switching, providing limited performance improvement for end-to-end applications. Others support bootstrapping, which requires quite a large ASIC design. To better support existing VFL training applications, we propose SAFE, an HE accelerator for scalable homomorphic matrix-vector products (HMVPs), which is the performance bottleneck. SAFE adopts a coefficient-wise encoded HMVP algorithm, despite a vanilla mode, we further explore the compressed and concatenated modes, which can fully utilize the polynomial encoding slots. The proposed hardware architecture, customized for HMVP dataflow, supports spatial and temporal parallelization of function units. The most costly polynomial function, NTT, is implemented with a low-area constant geometry unit which improves efficiency by 2.43x. SAFE is implemented as a CPU-FPGA heterogeneous acceleration system, unleashing the multithread potential. The evaluation demonstrates an up to 36x speed-up in end-to-end federated logistic regression training.

关键词： Polynomials Vectors Hardware Encoding Arithmetic Switches field programmable gate arrays Training Noise Federated learning hardware acceleration homomorphic encryption (HE) number theoretic transform (NTT) privacy-preserving computing

来源：评论

学校读者我要写书评

暂无评论

Research and Development of a Commercial Passive Fast Neutron Multiplicity Counting Device for Nuclear Material Accounting

引用

IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第4期72卷 1631-1636页

作者： Liu, Yuezhuang Zhang, Shaodong Lin, Xurun Zhou, Zhibo Li, Duohong Zhou, Xingyu Li, Mengyuan Jin, Baoliang Ma, Lin Li, Meng Zhang, Qi Li, Da Wu, Zhaohui Zhang, Xiaodong North China Elect Power Univ Sch Nucl Sci & Engn Beijing 102206 Peoples R China State Nucl Secur Technol Ctr Beijing 102401 Peoples R China Shenzhen Univ Coll Phys & Optoelect Engn Inst Adv Study Nucl Energy & Safety Shenzhen Key Lab Nucl & Radiat Safety Shenzhen 518060 Peoples R China

A commercial passive fast neutron multiplicity counting (FNMC) device has been developed by our group. The device mainly consists of 32 self-developed EJ-301 liquid scintillation detectors arranged in a spherically symmetrical configuration. These detectors are read out by a 32-channel electronics system equipped with an online field-programmable gate array (FPGA) neutron-gamma discrimination function. In addition, the device integrates a self-designed graphical user interface (GUI), enabling interactive operations such as control and monitoring of the readout electronics and high-voltage power supply. The one-parameter calibration and three-parameter assay methods are used for data analysis to estimate the mass of various 252Cf neutron sources. The results show that the device can accurately measure the mass of 252Cf neutron sources (with an equivalent 240Pueff mass range of 7.84-1929.15 g). Additionally, the three-parameter assay method is used to estimate the 240Pueff mass of four PuO2 samples, and the relative deviations (RDs) between estimated and true 240Pueff mass and relative uncertainties are all less than +/- 4.5% and 2.75%, respectively.

关键词： Neutrons Calibration Detectors Graphical user interfaces Logic gates Liquids field programmable gate arrays Uncertainty Readout electronics Crosstalk Fast neutron multiplicity counting (FNMC) liquid scintillation detectors online field-programmable gate array (FPGA) neutron-gamma discrimination

来源：评论

学校读者我要写书评

暂无评论

Design and HDL Implementation of Pulse-Arrival-Time Estimation Using XGBoost Regression With Tree-Recycling Architecture

引用

IEEE ACCESS 2025年 13卷 27596-27609页

作者： Choi, Hyo-Jeong Um, Ji-Yong Kumoh Natl Inst Technol Dept Med IT Convergence Engn Gumi Si 39253 South Korea

This paper presents a pulse-arrival-time (PAT) estimation scheme using Extreme Gradient Boosting (XGBoost) regression and its implementation with hardware description language (HDL). PAT is a significant metric for the estimation of pulse wave velocity (PWV) and blood pressure. We leverage morphological features of single photoplethysmogram (PPG) waveforms and subject-specific parameters to estimate PAT values through a decision tree ensemble regression model. XGBoost regression is adopted for PAT estimation through a comparative study conducted in software. To enable the integration of the regression model into a single chip, we propose a tree-recycling architecture for an area-efficient implementation of the decision tree ensemble model. The proposed PAT estimation has been implemented on a field-programmable gate array (FPGA, Artix7, Xilinx) for real-time verification using a dataset. Additionally, the active area of the proposed scheme in an integrated circuit was estimated after the place-and-route (PnR) procedure, resulting in an area of 1.44 mm2. We utilized the Vital Signs DataBase (VitalDB) for training and testing the proposed PAT estimation in a software-hardware co-design framework. Validation on 80 subjects yielded a determination coefficient (R2) of 0.983 in the linear regression analysis after implementing the HDL on an FPGA.

关键词： Estimation Hardware Biomedical monitoring Regression tree analysis field programmable gate arrays Elasticity Hardware design languages Computer architecture Boosting Training Pulse arrival time decision tree ensemble model extreme gradient boosting regression field programmable gate array tree-recycling architecture hardware description language

来源：评论

学校读者我要写书评

暂无评论

Prototype of Hi'Beam-SEE: A Real-Time High-Resolution Single-Event Effects Locating Device for Heavy-Ion Facilities

引用

IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 684-691页

作者： Liao, Jianwei Jia, Yanhao Liao, Shun Du, Jiangyong Yang, Haibo Huang, Ju Zhang, Honglin Wei, Xianglun Zhao, Peixiong Li, Xianqin Niu, Xiaoyang Han, Weijia He, Rui Zou, Chaojie Sun, Wenchao Peng, Xiangwei Zhao, Chengxin Chinese Acad Sci Inst Modern Phys Lanzhou 730000 Peoples R China Adv Energy Sci & Technol Guangdong Lab Huizhou 516003 Peoples R China Univ Chinese Acad Sci Sch Nucl Sci & Technol Beijing 100049 Peoples R China Liaoning Acad Mat Shenyang 110167 Peoples R China Guangxi Univ Sch Phys Sci & Technol Nanning 530004 Peoples R China

Integrated circuits (ICs) are widely used in spacecraft and are concerned with the probability of single-event effects (SEEs). To accurately locate the SEE-sensitive area of ICs, we have designed Hi'Beam-SEE for the SEE experiment terminal at heavy-ion facilities. The Hi'Beam-SEE consists of three subsystems: the heavy-ion positioning system (HIP) is responsible for locating the position of each particle in the beam, the single-event detection (SED) system detects the SEEs that occurred in the device under test (DUT), and the online tracking algorithm extracts and reconstructs the position of each particle that triggers SEEs. The beam test with Kr-84(18+) particles demonstrates that the HIP can achieve a spatial resolution of 4 mu m in measuring every single particle's position. Also, the SED system can identify SEEs correctly and issue triggers with good timing accuracy. The online tracking algorithm can process 172 frames that contain tracks per second and extract the positions with an accuracy of 3.2 mu m . In addition, it attains a rejection factor of 93.6% while keeping the signal efficiency of 99%. This article will discuss the design and performance characterization of the Hi'Beam-SEE.

关键词： Ions Circuits field programmable gate arrays Event detection Position measurement Particle beams Clocks Pins Monitoring Location awareness Integrated circuits (ICs) neural network readout electronics silicon pixel sensor single-event effect (SEE)

来源：评论

学校读者我要写书评

暂无评论

Hardware Self-Organizing Map With Dithered Step Neighborhood Function

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Hikawa, Hiroomi Kansai Univ Dept Sci & Engn Suita Osaka 5648680 Japan

In this paper, a hardware-based SOM architecture with a dithered step (DS) neighborhood function is introduced. In the DS function, dithering is added to a conventional step neighborhood function, and the dithering endows the step function with nonlinear characteristics. The nonlinear characteristics given by the dithering are found to lead to better quantization performance, while the simple structure of the step function, which remains the basis of the proposed function, maintains a low hardware cost. Here, the characteristics of the dithered function were theoretically analyzed before clustering experiments utilizing the proposed SOM implemented on a field-programmable gate array (FPGA) were conducted to evaluate the extent to which the proposed neighborhood function improves the performance of the resulting SOM. The experimental results show that the proposed DS neighborhood function decreases the circuit size and power consumption by 13.86% and 17.61%, respectively. In addition, the DS neighborhood function was used to create a hardware-based SOM with 4.33% greater throughput.

关键词： Self-organizing feature maps Vectors Hardware Neurons Training Quantization (signal) Circuits field programmable gate arrays Power demand Costs Self-organizing map neighborhood function dithering clustering FPGA

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：