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Optimized Algorithms for FPGA Implementation of PDCCH Chain for 5G-NR Base Station

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Rudramuniyappa, Harsha Soujanya, Samudrala Singh, Prem Sharma, Ekant IIIT Bangalore ECE Dept Bengaluru 560100 India IIT Roorkee ECE Dept Roorkee 247667 India

The physical layer in a cellular network base station typically runs on a field programmable gate array (FPGA) to enable reconfigurability and adaptability to meet future demands of the network with sufficient computational power. This work proposes a novel architecture and algorithms for the FPGA implementation of the fifth-generation (5G) new radio (NR) physical downlink control channel (PDCCH) using the 3GPP procedures for downlink control information (DCI) processing, including sub-block interleaver, bit selection, scrambling, golden sequence generation, and modulation. The proposed algorithms are optimized to meet 5G-NR frame timings for DCI processing with minimum power consumption and hardware resource utilization. We perform rigorous testing including all corner cases to benchmark our designs in i) standalone mode, and ii) integrated fashion for the end-to-end PDCCH processing. The PDCCH implementation, with maximum DCI payload, using the proposed architecture and algorithms achieves 1.5 mu s latency, 1.98% hardware resource utilization, 1.2$ Gbps throughput and 10 Gbps/W power efficiency. With a subcarrier spacing Delta f=30 KHz, it can multiplex DCI to schedule up to 20 and 40 users for one orthogonal frequency division multiplexing (OFDM) and two OFDM symbols long PDCCH respectively.

关键词： field programmable gate arrays Hardware Physical layer OFDM 3GPP Signal processing algorithms Encoding 1/f noise Throughput Symbols 5G-NR hardware implementation DCI PDCCH FPGA AXI-stream

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Area and Delay Trade-Offs in Three-Way Toom-Cook Large Integer Multipliers Implemented on FPGAs

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第2期72卷 600-609页

作者： Das, Monalisa Jajodia, Babita Indian Inst Informat Technol Guwahati Dept Elect & Commun Engn Gauhati 781015 India

The demand for efficient large integer polynomial multiplications in present day crypto-systems is the need of the hour. Toom-Cook multiplication algorithm being one of the most efficient multiplication algorithm is discussed in this work. The limitations of large integer polynomial multiplications using three-way Toom-Cook (Toom-3) multiplication algorithm and the methods to overcome it are presented in this paper. This is done by implementing two different division-free methods for symmetric Toom-3 multiplication as well as for asymmetric Toom-3 multiplication based on the input operand size (N). Hardware implementations of the proposed multiplication methods are done using Virtex-7 field programmable gate Array (FPGA) device in Xilinx ISE platform. The trade-off between hardware utilization and speed is noted, and the overall performance of the proposed design methods are measured by calculating Area-Time-Product (ATP). Practically, it has been observed that both the proposed Toom-3 multiplication methods performs better compared to the existing state-of-the-art designs.

关键词： Hardware field programmable gate arrays Polynomials Logic gates Interpolation Design methodology Accuracy Toom-3 Toom-Cook multiplication post-quantum cryptography polynomial multiplication large integer multiplication

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Implementation of Linear Differential Equations Using Pulse-Coupled Oscillators With an Ultra-Low Power Neuromorphic Realization

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第1期72卷 14-24页

作者： Shamsi, Jafar Nicola, Wilten Univ Calgary Hotchkiss Brain Inst Calgary AB T2N 1N4 Canada Univ Calgary Dept Cell Biol & Anat Calgary AB T2N 1N4 Canada

Pulse-coupled oscillators (PCOs) are used as models for oscillatory systems in diverse fields such as biology, physics, and engineering. When correctly coupled, PCOs can display sophisticated emergent dynamics for a large number of oscillators. Here, we propose an algorithm and hardware implementation of PCOs to emulate arbitrary systems of linear differential equations (DEs) with inputs, which are similar to the equations used in feedback control laws or linearizations of nonlinear systems. We show that $m$ populations of oscillators can solve a set of $m$ -dimensional linear DEs with simple coupling schemes, and crucially, without the matrix multiplications required in Euler integration. The emergence of linear dynamical systems in networks of PCOs occurs when the number of oscillators within a population becomes large, as demonstrated through an analytically exact mean-field derivation. In addition, a hardware architecture of PCOs for digital implementation is proposed and realized on an ultra-low power FPGA as a proof of concept. These results show that there are simple coupling schemes for pulse-coupled oscillator networks that collectively compute complex dynamical systems. These PCO networks also have an immediate implementation as low power neuromorphic edge devices.

关键词： Oscillators Hardware Differential equations Neurons Neuromorphics Mathematical models Linear systems field programmable gate arrays Couplings Low power electronics Pulse coupled oscillators linear differential equations Fokker-Planck approximation neuromorphic FPGA

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An Efficient Sparse CNN Inference Accelerator With Balanced Intra-and Inter-PE Workload

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第5期33卷 1278-1291页

作者： Guo, Jianbo Xu, Tongqing Wu, Zhenyang Xiao, Hao Hefei Univ Technol Sch Microelect Hefei 230601 Peoples R China

Sparse convolutional neural networks (SCNNs) which can prune trivial parameters in the network while maintaining the model accuracy has been proved to be an attractive approach to alleviate the heavy computation of convolutional neural networks (CNNs). However, the invalid data resulting from sparse patterns leads to unnecessary and irregular computation workload, which challenges the efficiency of the underlying hardware accelerators. Therefore, this article proposes an SCNN inference accelerator, which can deal with the imbalanced workload both intra-and interprocessing element (PE). A valid weight encoding (VWE) scheme is proposed to compress sparse weights into dense ones to alleviate the load imbalance intra-PE. Leveraging the VWE scheme, a randomized load rearrangement (RLR) method is proposed to dynamically schedule convolution kernels with similar sparsity into the same computation batch to alleviate the load imbalance inter-PEs. In addition, to reduce off-chip memory accesses, a recurrent weight stationary (RWS) dataflow is proposed, which adopts a small-batch and multichannel strategy to stack data from multiple channels within one off-chip access and let them compute simultaneously thereby enabling efficient reuse of on-chip data. Based on the proposed scheme, an efficient SCNN inference accelerator has been designed and verified on the field-programmable gate array (FPGA). Compared with state-of-the-art works, our design achieves 1.16 x to 2.77 x higher digital signal processors (DSPs) efficiency and 1.75 x to 15 x higher logic efficiency.

关键词： Kernel Computational efficiency Accuracy Engines Convolutional neural networks Convolution Indexes Hardware field programmable gate arrays Encoding Accelerator field-programmable gate array (FPGA) load imbalance memory accesses sparse convolutional neural networks (SCNNs)

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Unified Security Framework Using Device-Specific Fingerprint: Mitigating Hardware Trojans and Authenticating Firmware Updates

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IEEE ACCESS 2025年 13卷 26897-26914页

作者： Hemavathy, S. Jagadeesh, Kokila Bhaaskaran, V. S. Kanchana Vellore Inst Technol Sch Elect Engn Chennai campus Chennai 600127 India Indian Inst Informat Technol IIIT Dept Comp Sci & Engn Tiruchirappalli 620012 India Vellore Inst Technol Vellore 632014 India

System-on-Chips (SoCs) are ubiquitously used as smart devices with heterogeneous components embedded within them. The effective functioning of a system depends on Intellectual Property (IP) and firmware updates, which enhance performance and reliability and rectify vulnerabilities throughout the lifespan of any SoC. However, malicious logic intrusion by intruders can compromise the system's efficacy at the design phase of Internet of Things (IoT) applications. The proposed robust unified security framework efficiently streamlines the identification of hardware Trojans and secure firmware updates of the IPs in all intricate and heterogeneous SoCs without the need for the golden reference model. In the post-silicon validation technique, the authentication protocol utilizes the device-specific fingerprint of a Physical Unclonable Function (PUF) to authenticate the IPs. An enhanced Balanced Anderson Arbiter PUF (BAA-PUF) integrating two sources of randomness is physically implemented in ZCU104 MPSoC to generate 256 bits. The parameters of BAA-PUF are determined by majority voting and are close to the ideal value. The average execution time for identifying the Trojan with the proposed framework is found to be 40.184 ms. Two metrics have been introduced to demonstrate the efficacy of the proposed framework, namely, utilization scale, which illustrates the impact of Trojans on the resource utilized and digest uniqueness, which demonstrates the presence of Trojans and ranges from 45.3% to 55%. The performance of the authentication protocol is also validated based on computation and communication costs. The authentication protocol is analyzed using the formal technique, employing Burrows-Abadi-Needham (BAN) logic and informal methods to confirm its robustness against hardware-based attacks.

关键词： IP networks Trojan horses Security Microprogramming Authentication Table lookup Hardware field programmable gate arrays Logic gates Fingerprint recognition Authentication protocol digest uniqueness to detect trojans hardware trojans PUF-based device-specific fingerprint secure firmware update utilization scale

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ViTeGNN: Towards Versatile Inference of Temporal Graph Neural Networks on FPGA

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2025年第3期36卷 502-519页

作者： Zhou, Hongkuan Zhang, Bingyi Kannan, Rajgopal Busart, Carl Prasanna, Viktor K. Univ Southern Calif Los Angeles CA 90007 USA DEVCOM Army Res Off Los Angeles CA 90089 USA DEVCOM Army Res Lab Adelphi MD 20783 USA

Temporal Graph Neural Networks (TGNNs) are powerful models to capture temporal, structural, and contextual information on temporal graphs, outperforming other methods in many high-impact downstream tasks. However, achieving high-performance TGNN inference in production environments is challenging because TGNN models suffer from high computation complexity and intrinsic temporal data dependency that hinders data parallelism. In addition, real-world TGNN applications have different latency and throughput requirements. This work presents ViTeGNN, a versatile TGNN inference solution for memory-based TGNNs on FPGAs. ViTeGNN performs algorithm-model-architecture co-design to meet the latency and throughput requirements of real-world TGNN applications. Besides the vanilla inference mode ViTeGNN-bal that updates embeddings for nodes interacting with others, we propose ViTeGNN-lat and ViTeGNN-thpt, optimized for latency and throughput. Our model optimizations include a lightweight method to compute attention scores and a related temporal neighbor pruning strategy to reduce computation and memory accesses. These are holistically coupled with key hardware optimizations that leverage the FPGA hardware. We propose a novel hardware module to execute the complex neighbor update process efficiently. To ensure similar accuracy vis-a-vis the original model, the simplified models are trained using the knowledge distillation technique. We propose a unified hardware design that supports all of these three inference modes without FPGA reconfiguration. Enabled by our flexible hardware architecture, we further propose ViTeGNN-auto, which automatically selects the best inference mode at runtime based on latency and throughput requirements, guided by our accurate performance model. We evaluate the performance of the proposed hardware accelerator on five real-world datasets. ViTeGNN-bal reduces the computation complexity by an average of 62% and memory accesses by an average of 36% with only

关键词： Computational modeling field programmable gate arrays Throughput Inference algorithms Optimization Accuracy Parallel processing Heuristic algorithms Graph neural networks Vectors FPGA hardware architecture temporal graph neural network

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AXI Hardware Accelerator for McEliece on FPGA Embedded Systems

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IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING 2025年第2期22卷 1477-1490页

作者： Canto-Navarro, Enrique Lopez-Garcia, Mariano Univ Rovira I Virgili Elect Elect & Automatic Dept Tarragona 43007 Spain Univ Politecn Cataluna Dept Elect Vilanova I La Geltru 08800 Spain

This article presents a McEliece hardware accelerator designed to be attached to an AXI infrastructure, addressing the efficient implementation of a flexible post-quantum cryptoprocessor on FPGA-based embedded systems. The complexity of the arithmetic circuits, combined with the adaptability to different applications by configurable parameters and run-time reprogramming, presents challenging issues for integrating the accelerator into these systems. The architecture of the accelerator is based on an application-specific instruction processor, which executes a set of constant-time instructions from an internal register file and memories. The role of the embedded processor is reduced to the initial writing of the instruction memory of the accelerator, the launching of the required set of instructions and configuring the Direct Memory Access controller to retrieve and store data from external memory. The run-time programming of the accelerator provides high flexibility in applications that requires post-quantum cryptography. A set of configurable parameters permits to adapt the security level of the McEliece encryption-decryption and the area-performance tradeoff imposed by the target device. Thus, the accelerator can be implemented from low-cost to high-end FPGAs by configuring the data-width of DMA buses or the parallelism level of the Galois-field adder-multiplier. Experimental results show the accelerator is suited for implementing efficiently the highest security parameters of the Classic McEliece, achieving a McEliece decryption speed-up from x370 to x556 and occupying a small number of resources on a low-cost FPGA. In high-end FPGAs, the accelerator can be configured using higher security parameters not achieved in previous related cryptoprocessors, providing even higher accelerations.

关键词： field programmable gate arrays Cryptography Clocks Codes Microprocessors Table lookup Encryption Public key cryptosystem real-time and embedded systems reconfigurable hardware

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PEPPR-DWS on FPGA: Elevating Universal Parallelism and Precision Through Pulse-Enhanced Push-Relabel and Diffusion Wave Search

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2025年第1期44卷 157-171页

作者： Dong, Zehua Zhang, Boyu Jiang, Yucheng Yu, Yu Li, Han Mai, Songping Tsinghua Univ Shenzhen Int Grad Sch Shenzhen 518055 Peoples R China Peng Cheng Lab Dept Circuit & Syst Shenzhen 518066 Peoples R China

The push-relabel algorithm is recognized as one of the efficient algorithms in the field of graph cut, finding widespread applications in computer vision. While its pixel-level parallel implementations are prevalent, existing methods predominantly rely on checkerboard scheduling, imposing inherent constraints on neighborhood size, limited to four. This limitation compromises both algorithm precision and efficiency, hindering real-time and high-precision applications. To address these issues, this article introduces a novel approach to accelerate push-relabel algorithm implementation on FPGA in a more universal and efficient manner, supporting variable-sized image block operations. First, by introducing the deferred update strategy, we realize the pulse-enhanced parallel push-relabel (PEPPR) algorithm to address data contention and conflict in parallel processing. Second, the simultaneous weighted push method is proposed, further enhancing parallel operations. Lastly, we introduce the efficient diffusion wave search (DWS) algorithm to expedite algorithm convergence and reduce redundancy. While achieving a modest $1.7\times $ acceleration compared to state-of-the-art implementations, the proposed algorithm (PEPPR-DWS) successfully overcomes the inherent limitations of checkerboard scheduling in full pixel-level parallelism. In the test based on Middlebury benchmark V3, the proposed 8-neighborhood implementation exhibits a reduction of error rate by over 1% compared to the typical 4-neighborhood implementation. It provides a versatile and efficient solution for high-precision and real-time applications, holding substantial potential for practical applications.

关键词： Parallel processing field programmable gate arrays Convergence Graphics processing units Scheduling Optimization Design automation Diffusion wave search (DWS) field programmable gate array (FPGA) acceleration hardware-friendly pixel-level parallelism push-relabel simultaneous weighted push (SWP)

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Efficient Integer-Only-Inference of Gradient Boosting Decision Trees on Low-Power Devices

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第1期72卷 241-253页

作者： Alsharari, Majed Mai, Son T. Woods, Roger Reano, Carlos Queens Univ Belfast Sch Elect Elect Engn & Comp Sci Belfast BT7 1NN North Ireland Univ Valencia Dept Comp Sci Valencia 46010 Spain

There is increasingly interest in developing embedded machine learning hardware as it can offer better performance in terms of privacy, bandwidth efficiency, and scalability. Gradient-boosted decision trees (GBDT) represent a strong candidate as they employ less complex logic, but their efficient implementation in field programmable gate array (FPGA) needs to be explored in detail. In this paper, we propose sophisticated quantisation approaches to balance the dual goals of efficiency and performance. In particular, we introduce quantisation-aware training of GBDT for integer-only and binary arithmetic. Results are presented for implementations on a Zynq UltraScale + MPSoC FPGA with the best design using only 170 Look-up Tables and 233 flip-flops at a clock speed of 724 MHz. Implementations focused on network intrusion detection and jet substructure classification for large-scale physics experiments are explored. An order of magnitude less FPGA resources are used whilst offering extremely high throughput rate and maintaining accuracy. Code is available at https://***/malsharari/QATGBDT.

关键词： field programmable gate arrays Quantization (signal) Computational modeling Decision trees Accuracy Training Hardware Gradient-boosted decision trees embedded AI field programmable gate array quantization-aware training design framework

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FPGA-Based Design of Multipoint Parallel EMD for Anomaly Detection in Acquisition System

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2025年

作者： Li, Chengyang Tian, Shulin Yang, Kuojun Ye, Peng Huang, Wuhuang Ye, Ziyang Univ Elect Sci & Technol China Sch Automat Engn Chengdu 611731 Peoples R China Southwest Jiaotong Univ Sch Elect Engn Chengdu 611756 Peoples R China

Empirical mode decomposition (EMD) is effective in anomaly detection applications based on nonsmooth signal decomposition in the electronics industry. With the increasing bandwidth of electrical signals, the transient characteristics of signals are becoming increasingly significant. To detect anomalies in repetitive and periodic signals that can be decomposed by EMD, real-time EMD with high throughput is urgently required. The existing FPGA-based EMD design cannot meet the requirements for real-time processing of several Gbps data. Moreover, the EMD design of FPGA in the existing literature ignores the influence of different intrinsic mode functions (IMFs) caused by different decomposition starting points of EMD. Consequently, a multipoint parallel pipeline architecture for EMD based on characteristic points is proposed. First, the characteristic point of the signal serves as the decomposition start point for real-time EMD, which avoids the problem of different IMFs caused by different decomposition start points in EMD. Second, a multipoint parallel pipeline architecture is employed to facilitate the extrema extraction and the envelope calculation, markedly enhancing the speed of EMD decomposition. Finally, the proposed multipoint parallel EMD design is implemented on the KU115 series FPGA in the 20 GSPS data acquisition system and the performance of the proposed architecture is verified by EMD decomposition in anomaly detection testing. Compared to all current FPGA-based EMD designs, the EMD design proposed in this article achieves a 4.25-fold increased throughput of 2640 Mbps. This demonstrates the efficacy of the proposed multipoint parallel architecture in enhancing the EMD decomposition speed. The proposed architecture can be widely used for the real-time decomposition of high-speed signals in electronics measurement.

关键词： field programmable gate arrays Real-time systems Pipelines Anomaly detection Throughput Hardware Service-oriented architecture Interpolation Data preprocessing Clocks Empirical mode decomposition (EMD) field programmable gate array (FPGA) high-speed data acquisition multipoint parallel pipeline

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