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On-line fault detection for bus-based field programmable gate arrays

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1998年第4期6卷 656-666页

作者： Shnidman, NR Mangione-Smith, WH Potkonjak, M MIT Dept Elect Engn & Comp Sci Cambridge MA 02139 USA Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90095 USA MIT Dept Comp Sci Cambridge MA 02139 USA

We introduce a technique for on-line built-in self-testing (BIST) of bus-based held programmable gate arrays (FPGA's), This system detects deviations from the intended functionality of an FPGA without using special-purpose hardware, hardware external to the device, and without interrupting system operation. Such a system would be useful for mission-critical applications with resource constraints. The system solves these problems through an on-line fault scanning methodology. A device's internal resources are configured to test for faults. Testing scans across an FPGA, checking a section at a time. Simulation on a model FPGA supports the viability and effectiveness of such a system.

关键词： digital system fault tolerance field programmable gate arrays self-testing

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SYNTHESIS METHODS FOR field-programmable gate arrays

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PROCEEDINGS OF THE IEEE 1993年第7期81卷 1057-1083页

作者： SANGIOVANNIVINCENTELLI, A ELGAMAL, A ROSE, J STANFORD UNIV DEPT ELECT ENGNSTANFORDCA 94305 UNIV TORONTO DEPT ELECT ENGNTORONTO M5S 1A4ONTARIOCANADA

field programmable gate arrays (FPGA's) reduce the turn-around time of application-specific integrated circuits from weeks to minutes. However, the high complexity of their architectures makes manual mapping of designs time consuming and error prone thereby offsetting any turnaround advantage. Consequently, effective design autontation tools are needed to reduce design time. Among the most important is logic synthesis. While standard synthesis techniques could be used for FPGA's, the quality of the synthesized designs is often unacceptable. As a result, much recent work has been devoted to developing logic synthesis tools targeted to different FPGA architectures. The paper surveys this work- The three most popular types of FPGA architectures are considered, namely those using logic blocks based on lookup-tables, multiplexers and wide AND/OR arrays. The emphasis is on tools which attempt to minimize the area of the combinational logic part of a design since little work has been done on optimizing performance or routability, or on synthesis of the sequential part of a design. The different tools surveyed are compared using a suite of benchmark designs.

关键词： FPGA architectures application specific integrated circuits circuit CAD combinational logic part field programmable gate arrays logic CAD logic arrays logic synthesis algorithms lookup-tables multiplexers sequential part wide AND/OR arrays

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Reconfiguration time overhead on field programmable gate arrays: reduction and cost model

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IET COMPUTERS AND DIGITAL TECHNIQUES 2012年第2期6卷 105-113页

作者： Duhem, F. Muller, F. Lorenzini, P. Univ Nice Sophia Antipolis LEAT CNRS F-06560 Valbonne France

Partial reconfiguration suffers from low performance and thus its use is limited when the reconfiguration overhead is too high compared to the task execution time. To overcome this issue, the authors present a fast internal configuration access port (ICAP) controller, FaRM, providing high-speed configuration and easy-to-use readback capabilities, reducing configuration overhead as much as possible. In order to enhance performance, FaRM uses techniques such as master accesses, ICAP overclocking, bitstream pre-load into a controller and bitstream compression technique, Offset-run length encoding (RLE), which is an improvement of the RLE algorithm. Combining these approaches allows us to achieve an ICAP theoretical throughput of 800 MB/S at 200 MHz. In order to complete our approach, we provide a cost model for the reconfiguration overhead for the system level that can be used during the early stages of development. The authors tested their approach on an Advanced Encryption Standard (AES) encryption/decryption architecture.

关键词： Logic circuits advanced encryption standard high speed configuration AES bitstream compression technique easy-to-use readback capabilities field programmable gate arrays RLE partial reconfiguration run length encoding internal configuration access port cost model ICAP reduction model Logic and switching circuits

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Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks

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IET INFORMATION SECURITY 2011年第4期5卷 181-190页

作者： Selmane, N. Bhasin, S. Guilley, S. Danger, J. -L. TELECOM ParisTech Inst TELECOM CNRS LTCI UMR 5141 Paris France Dept COMELEC F-75634 Paris 13 France

Fault attacks are real threats against hardware implementations of robust cryptographic algorithms such as advanced encryption standard (AES). The authors present an active non-invasive attack to inject faults during the execution of the algorithm and describe setup time violation attacks by under-powering and overclocking an application-specific integrated circuit. Then a security evaluation is presented against setup time violation attacks of several AES architectures on two field programmable gate arrays (FPGA) brands, namely Altera Stratix and Xilinx Virtex5. The authors notice that the architecture of the substitution box greatly impacts the faults statistics. These statistics are furthermore different depending on the FPGA vendor, and also notice that it is more difficult to inject single fault in the most recent technology. Also, the use-cases show how difficult it is to predict the most vulnerable resource in an FPGA. Finally, a low-cost countermeasure against this kind of attack is presented.

关键词： AES architectures Altera Stratix FPGA brands FPGA vendor Xilinx Virtex5 active noninvasive attack advanced encryption standard application specific integrated circuits application-specific integrated circuits cryptography fault attacks fault diagnosis faults statistics field programmable gate arrays field programmable gate arrays hardware implementations inject faults low-cost countermeasure robust cryptographic algorithms security evaluation setup time violation attacks substitution box vulnerable resource

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Extendable multirate real-time simulation of active distribution networks based on field programmable gate arrays

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APPLIED ENERGY 2018年 228卷 2422-2436页

作者： Wang, Zhiying Wang, Chengshan Li, Peng Fu, Xiaopeng Wu, Jianzhong Tianjin Univ Key Lab Smart Grid Minist Educ Tianjin 300072 Peoples R China Cardiff Univ Inst Energy Sch Engn Cardiff CF24 3AA S Glam Wales

Real-time simulation of large-scale active distribution networks exhibiting a wide range of time-scales puts forward higher requirements for simulation accuracy and efficiency. This paper presents an extendable method and design for the real-time simulation of active distribution networks utilising high-performance hardware field programmable gate arrays. In the aspect of numerical algorithm, a high-accuracy and stable multirate simulation algorithm is proposed. The entire active distribution network is decoupled into different subsystems by their inherent time-scales and distinct time steps are used to solve the subsystems. Then root-matching method is adopted to form the exponential difference equations that represent the behaviours of the electric distribution network being modelled, which eliminates the truncation errors and thus provides a highly accurate time-domain solution. To handle the interface between the subsystems, a multirate interfacing method is proposed. The hardware design of the multirate interfaces is presented as well. With the multirate algorithm, a fully functional extendable real-time simulator based on field programmable gate arrays is designed and implemented. Two modified IEEE 33-node systems with photovoltaics and energy storage are simulated on the 4-field-programmable-gate-arrays-based real-time simulator. Simulation results are compared with the commercial simulation tool PSCAD/EMTDC to validate the correctness and effectiveness of the proposed method and design.

关键词： Real-time simulation field programmable gate arrays Multirate simulation Root-matching method Active distribution network

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Multiplicative finite impulse response filters: implementations and applications using field programmable gate arrays

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IET SIGNAL PROCESSING 2015年第5期9卷 449-456页

作者： Vandenbussche, Jean-Jacques Lee, Peter Peuteman, Joan Katholieke Univ Leuven KU Leuven Kulab Dept ESAT Fac Engn Technol Louvain Belgium Univ Kent Sch Engn & Digital Arts Canterbury CT2 7NT Kent England

This paper describes how modern field programmable gate array (FPGA) technology can be used to build practical and efficient multiplicative finite impulse response (MFIR) filters with low-pass, high-pass, band-pass and band-stop characteristics. This paper explains how MFIR structures can be built with or without linear phase characteristics and implemented efficiently on modern FPGA architectures using fixed-point arithmetic without incurring stability problems or limit cycles which commonly occur when using equivalent infinite impulse response structures. These properties have a particular importance for applications such as tunable resonators, narrow band rejectors and linear phase filters which have demanding, narrow transition band requirements. The results presented in this paper indicate that MFIR filters are, for some applications, a viable alternative to existing filter structures when implemented on an FPGA.

关键词： field programmable gate arrays FIR filters low-pass filters high-pass filters band-pass filters band-stop filters linear phase filters IIR filters multiplicative finite impulse response filter MFIR filter field programmable gate array low-pass characteristics band-stop characteristics high-pass characteristics band-pass characteristics linear phase characteristics modern FPGA architecture fixed-point arithmetic equivalent infinite impulse response structures

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Technology mapping algorithm for heterogeneous field programmable gate arrays

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 2002年第6期149卷 249-255页

作者： Lai, YT Kao, CC Natl Cheng Kung Univ Dept Elect Engn Tainan 701 Taiwan

To maximise device utilisation, a heterogeneous field programmable gate array (FPGA) provides either an array of homogeneous lookup tables (LUTs) of different sizes or an array of physically heterogeneous LUTs. It is shown that heterogeneous FPGAs have a significant number of desirable attributes. A technology mapping algorithm is proposed for heterogeneous FPGAs. The technology mapping problem is first formulated as a flow network problem. Then, an algorithm based on the min-cost max-flow algorithm is presented to select a proper set of feasible LUTs for various objectives. Two objectives: (i) the minimum number of LUTs;and (ii) the total area composed of LUTs and routing area are discussed. The algorithm is tested on the MCNC benchmark circuits and produces better characteristics than existing LUT-based FPGA mapping algorithms.

关键词： Computer-aided circuit analysis and design field programmable gate arrays device utilisation benchmark circuits logic CAD heterogeneous field programmable gate array table lookup FPGA mapping Digital circuit design, modelling and testing Computer-aided logic design technology mapping homogeneous lookup tables Logic and switching circuits Logic circuits LUTs lookup tables

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Step forward to map fully parallel energy efficient cortical columns on field programmable gate arrays

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IET SCIENCE MEASUREMENT & TECHNOLOGY 2014年第6期8卷 432-440页

作者： Ghani, Arfan See, Chan H. Ali, Syed M. Usman Univ Bolton Dept Elect & Elect Engn Bolton BL3 5AB England Newcastle Univ Dept Elect & Elect Engn Newcastle Upon Tyne NE1 7RU Tyne & Wear England NED Univ Engn & Technol Dept Elect Engn Karachi 75270 Pakistan

This study presents energy and area-efficient hardware architectures to map fully parallel cortical columns on reconfigurable platform - field programmable gate arrays (FPGAs). An area-efficient architecture is proposed at the system level and benchmarked with a speech recognition application. Owing to the spatio-temporal nature of spiking neurons it is more suitable to map such architectures on FPGAs where signals can be represented in binary form and communication can be performed through the use of spikes. The viability of implementing multiple recurrent neural reservoirs is demonstrated with a novel multiplier-less reconfigurable architectures and a design strategy is devised for its implementation.

关键词： field programmable gate arrays reconfigurable architectures speech recognition neurophysiology recurrent neural nets fully parallel energy efficient cortical columns field programmable gate arrays area-efficient hardware architectures reconfigurable platform FPGAs speech recognition application spiking neurons multiple recurrent neural reservoirs multiplier-less reconfigurable architectures

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A Hardware-Friendly Hyperspectral Lossy Compressor for Next-Generation Space-Grade field programmable gate arrays

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IEEE JOURNAL OF SELECTED TOPICS IN APPLIED EARTH OBSERVATIONS AND REMOTE SENSING 2019年第12期12卷 4813-4828页

作者： Guerra, Raul Barrios, Yubal Diaz, Maria Baez, Abelardo Lopez, Sebastian Sarmiento, Roberto Univ Las Palmas Gran Canaria Inst Appl Microelect Las Palmas Gran Canaria 35017 Spain

The increment in the data rate of the new-generation hyperspectral sensors is making more critical the necessity of lossy compression solutions able to achieve higher compression ratios (CRs). In this paper, a transform-based lossy compressor, namely lossy compression algorithm for hyperspectral image systems (HW-HyperLCA), is proposed as a modification of the original HyperLCA, specifically designed for being executed into space-grade field programmable gate array (FPGA) devices. The HW-HyperLCA compressor can be totally executed using integer arithmetic, using different levels of precision that can be adapted for achieving the best relation between compression performance and computational burden. The experiments carried out in this paper demonstrate that the HW-HyperLCA compressor is able to compress the hyperspectral images to less than 1 bit per pixel per band with low distortions (more than 40 dB of signal-to-noise ratio) while the performed complexity analysis demonstrates that it can be efficiently executed into space-grade FPGAs using very few computational resources and good results in terms of maximum clock frequency can be obtained.

关键词： Image coding Transforms field programmable gate arrays Hyperspectral imaging HyperLCA compressor hyperspectral compression lossy compression on-board compression

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HARDWARE IMPLEMENTATION OF AN ARTIFICIAL NEURAL-NETWORK USING field-programmable gate arrays (FPGAS)

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 1994年第6期41卷 665-667页

作者： BOTROS, NM ABDULAZIZ, M Department of Electrical Engineering Southem Illinois University Carbondale IL USA

In this paper we present a hardware implementation of a fully digital multi-layer perceptron artificial neural network using Xilinx field programmable gate arrays (FPGAs). Each node is implemented with two XC3042 FPGAs and a 1K x 8 EPROM. Training is done off-line on a PC. We have tested successfully the performance of the network.

关键词： field programmable gate arrays Neural network hardware Artificial neural networks Very large scale integration programmable logic arrays Computational modeling Medical simulation Software packages Multilayer perceptrons EPROM

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