field-programmablegatearrays (FPGAs) have recently garnered significant interest for certain applications within the nuclear field including instrumentation and control (I&C) systems, pulse measurement systems, ...
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field-programmablegatearrays (FPGAs) have recently garnered significant interest for certain applications within the nuclear field including instrumentation and control (I&C) systems, pulse measurement systems, particle detectors, and health physics. In CANada Deuterium Uranium (CANDU) nuclear power plants, the use of heavy water (D2O) as the moderator leads to increased production of tritium, which poses a health risk and must be monitored by tritium-in-air monitors (TAMs). Traditional TAMs are mostly designed using microprocessors. More recent studies show that FPGAs could be a potential alternative to implement the electronic logic used in radiation detectors, such as the TAM, more effectively. In this paper, an FPGA-based TAM is designed and constructed in a laboratory setting using an FPGA-based cRIO system. New functionalities, such as the detection of carbon-14 and the addition of noble-gas compensation, are incorporated into a new FPGA-based TAM along with the standard functions included in the original microprocessor-based TAM. The effectiveness of the new design is demonstrated through simulations as well as laboratory testing on the prototype system. Potential issues caused by radiation interactions with the FPGA are beyond the scope of this work.
This study examined high-current events observed in Xilinx field-programmablegatearrays irradiated with heavy ions. A probable cause and proposed changes to the test methodology to prevent these high-current events ...
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ISBN:
(纸本)9781509060818
This study examined high-current events observed in Xilinx field-programmablegatearrays irradiated with heavy ions. A probable cause and proposed changes to the test methodology to prevent these high-current events is described.
In this paper, a FPGA remote laboratory for students in digital electronics circuits is presented. The proposed system provides low-cost experiments by means of low network bandwidth consumption, effective user manage...
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In this paper, a FPGA remote laboratory for students in digital electronics circuits is presented. The proposed system provides low-cost experiments by means of low network bandwidth consumption, effective user management and low setup cost. The experiments on the remote laboratory are also carried out to demonstrate and evaluate the performance of the proposed system.
At present, the relevancy to image processing is increasing and applications of image processing are developing. Also “field programmable gate arrays (FPGA)” is gaining in popularity nowadays. FPGAs are strong in pa...
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At present, the relevancy to image processing is increasing and applications of image processing are developing. Also “field programmable gate arrays (FPGA)” is gaining in popularity nowadays. FPGAs are strong in parallel computation and then can work too fast. Because of these advantages, they are preferred in applications which has complex calculation and needs high speed. In this work, basic image processing applications were implemented on FPGA hardware. Real-time motion video was used for these applications and results of applications were given at the result part of work. Also, the performance of hardware for advanced level of image processing applications was explained.
Floating-point (FP) multiply-add fused (F-1*F-2 +/- F-3) and multiply-accumulate represent the most common arithmetic operation in a wide range of applications, such as graphic processing, multimedia or FP digital sig...
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Floating-point (FP) multiply-add fused (F-1*F-2 +/- F-3) and multiply-accumulate represent the most common arithmetic operation in a wide range of applications, such as graphic processing, multimedia or FP digital signal processing (DSP). This study proposes FP multiply-add fused units for low-precision formats (IEEE 16-bit half precision or the 32-bit single precision) which rely on modern fieldprogrammablegate Array (FPGA) features such as the available integer multiply-accumulate-based support built-in the FPGA DSP blocks. These are employed as building-blocks within the mantissa data-path processing for the multiplication and the add/subtract operations. In order to use the DSP block for these operations, the alignment right shifts are performed before the multiply-add stage: a right shift on the addend, and, a right shift for one of the multiplicands. This results in efficient DSP usage;thus both cost savings and higher performance (high working frequencies and low latencies) are obtained for the multiply-add fused operation.
Hardware Trojans (HTs) are an emerging threat for integrated circuits integrity and their applications. Trying to find efficient HT detection methods is necessary. However, before detecting them, HTs need to be create...
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Hardware Trojans (HTs) are an emerging threat for integrated circuits integrity and their applications. Trying to find efficient HT detection methods is necessary. However, before detecting them, HTs need to be created with an efficient method and their effects need to be understood. There are very few studies which describe HTs implementation methods and the methods used are not convenient for systematic study of HTs effects. The Trust-Hub website, known for hardware security in general, had published a full HT implementation tutorial, which is not completely satisfying. This study proposes a stealthy and reusable HT implementation method on field programmable gate arrays at the layout level adapted for the study of different HTs with the same non-infected circuit. Created for a systematic study of the effects brought by different HTs, the proposed approach allows designers to insert stealthy HTs inside the same circuit in order to create different realistic infected circuits. HTs implementation results on an advance encryption standard system and detection experiments based on side-channel are also presented in this study. The implementation method the authors propose can be used with scripts in order to accelerate the insertions of HTs variants.
This study presents energy and area-efficient hardware architectures to map fully parallel cortical columns on reconfigurable platform - field programmable gate arrays (FPGAs). An area-efficient architecture is propos...
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This study presents energy and area-efficient hardware architectures to map fully parallel cortical columns on reconfigurable platform - field programmable gate arrays (FPGAs). An area-efficient architecture is proposed at the system level and benchmarked with a speech recognition application. Owing to the spatio-temporal nature of spiking neurons it is more suitable to map such architectures on FPGAs where signals can be represented in binary form and communication can be performed through the use of spikes. The viability of implementing multiple recurrent neural reservoirs is demonstrated with a novel multiplier-less reconfigurable architectures and a design strategy is devised for its implementation.
In this work, we demonstrate the use of a fieldprogrammablegate Array (FPGA) as a physical platform for realizing chaotic delay differential equations (DDE). Moreover, using our platform, we also experimentally stud...
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In this work, we demonstrate the use of a fieldprogrammablegate Array (FPGA) as a physical platform for realizing chaotic delay differential equations (DDE). Moreover, using our platform, we also experimentally study the synchronization between two time delayed systems. We illustrate two different experimental approaches - one is hardware co-simulation (using a Digilent Atlys with a Xilinx Spartan-6 FPGA) and the other is analog output (using a Terasic DE-2115 with an Altera Cyclone IV E FPGA).
Billions of internet end-users and device to device connections contribute to the significant data growth in recent years, large scale, unstructured, heterogeneous data and the corresponding complexity present challen...
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ISBN:
(纸本)9781479942749
Billions of internet end-users and device to device connections contribute to the significant data growth in recent years, large scale, unstructured, heterogeneous data and the corresponding complexity present challenges to the conventional real-time online fraud detection system security. With the advent of big data era, it is expected the data analytic techniques to be much faster and more efficient than ever before. Moreover, one of the challenges with many modern algorithms is that they run too slowly in software to have any practical value. This paper proposes a fieldprogrammablegate Array (FPGA) -based intrusion detection system (IDS), driven by a new coupled metric learning to discover the inter-and intra-coupling relationships against the growth of data volumes and item relationship to provide a new approach for efficient anomaly detections. This work is experimented on our previously published NetFlow-based IDS dataset, which is further processed into the categorical data for coupled metric learning purpose. The overall performance of the new hardware system has been further compared with the presence of conventional Bayesian classifier and Support Vector Machines classifier. The experimental results show the very promising performance by considering the coupled metric learning scheme in the FPGA implementation. The false alarm rate is successfully reduced down to 5% while the high detection rate (= 99.9%) is maintained.
field programmable gate arrays (FPGAs) are a popular platform for evolving digital circuits. FPGAs allow to be reconfigured partially which provides a natural way of establishing candidate solutions. Recent research f...
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ISBN:
(纸本)9781479944798
field programmable gate arrays (FPGAs) are a popular platform for evolving digital circuits. FPGAs allow to be reconfigured partially which provides a natural way of establishing candidate solutions. Recent research focuses on the hardware implementation of evolutionary design platforms. Several approaches have been developed for effective establishment and evaluation of candidate solutions in FPGAs. In this paper a new mutation operator is proposed for evolutionary algorithms. The chromosome representing the candidate solution is mutated in such a way that only one configuration frame is required for establishing the mutated candidate solution in hardware. The experimental results confirm that the reduced number of configuration frames and mutations at lower level of granularity ensure faster evolution, generation of more candidate solutions in a given time as well as solutions with better quality.
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