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TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第5期72卷 2263-2273页

作者： Sestito, Cristian Agwa, Shady Prodromakis, Themis Univ Edinburgh Inst Integrated Micro & Nano Syst Ctr Elect Frontiers Sch Engn Edinburgh EH9 3BF Scotland

Modern hardware architectures for Convolutional Neural Networks (CNNs), other than targeting high performance, aim at dissipating limited energy. Reducing the data movement cost between the computing cores and the memory is a way to mitigate the energy consumption. Systolic arrays are suitable architectures to achieve this objective: they use multiple processing elements that communicate each other to maximize data utilization, based on proper dataflows like the weight stationary and row stationary. Motivated by this, we have proposed TrIM, an innovative dataflow based on a triangular movement of inputs, and capable to reduce the number of memory accesses by one order of magnitude when compared to state-of-the-art systolic arrays. In this paper, we present a TrIM-based hardware architecture for CNNs. As a showcase, the accelerator is implemented onto a field programmable gate Array (FPGA) to execute the VGG-16 and AlexNet CNNs. The architecture achieves a peak throughput of 453.6 Giga Operations per Second, outperforming a state-of-the-art row stationary systolic array up to similar to 3x in terms of memory accesses, and being up to similar to 11.9 x more energy-efficient than other FPGA accelerators.

关键词： Artificial intelligence convolutional neural networks systolic arrays field programmable gate arrays memory accesses energy efficiency

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CapsBeam: Accelerating Capsule Network-Based Beamformer for Ultrasound Nonsteered Plane-Wave Imaging on field-programmable gate Array

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年

作者： Rahoof, Abdul Chaturvedi, Vivek Raveendranatha Panicker, Mahesh Shafique, Muhammad Indian Inst Technol Palakkad IITPKD Kanjikode 678623 India Singapore Inst Technol SIT Singapore 138683 Singapore New York Univ Abu Dhabi Div Engn Abu Dhabi U Arab Emirates

In recent years, there has been a growing trend in accelerating computationally complex nonreal-time beamforming algorithms in ultrasound imaging using deep learning models. However, due to the large size and complexity, these state-of-the-art deep learning techniques pose significant challenges when deploying on resource-constrained edge devices. In this work, we propose a novel capsule network-based beamformer called CapsBeam, designed to operate on raw radio frequency data and provide an envelope of beamformed data through nonsteered plane-wave insonification. In experiments on in vivo data, CapsBeam reduced artifacts compared to the standard Delay-and-Sum (DAS) beamforming. For in vitro data, CapsBeam demonstrated a 32.31% increase in contrast, along with gains of 16.54% and 6.7% in axial and lateral resolution compared to the DAS. Similarly, in silico data showed a 26% enhancement in contrast, along with improvements of 13.6% and 21.5% in axial and lateral resolution, respectively, compared to the DAS. To reduce the parameter redundancy and enhance the computational efficiency, we pruned the model using our multilayer look-ahead kernel pruning (LAKP-ML) methodology, achieving a compression ratio of 85% without affecting the image quality. Additionally, the hardware complexity of the proposed model is reduced by applying quantization, simplification of nonlinear operations, and parallelizing operations. Finally, we proposed a specialized accelerator architecture for the pruned and optimized CapsBeam model, implemented on a Xilinx ZU7EV FPGA. The proposed accelerator achieved a throughput of 30 GOPS for the convolution operation and 17.4 GOPS for the dynamic routing operation.

关键词： Imaging Array signal processing Heuristic algorithms Ultrasonic imaging Routing field programmable gate arrays Deep learning Image quality Image resolution Image reconstruction Beamforming capsule network field-programmable gate array (FPGA) hardware accelerator reconstruction ultrasound imaging

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Method for the Real-Time Simulation of High Switching Frequency Power Electronic Converter Considering Switch Junction Capacitance

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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 2025年第1期13卷 1256-1268页

作者： Sun, Zonghui Guo, Xizheng Wang, Shinan Li, Yue Wang, Yule Yin, Yongjie You, Xiaojie Beijing Jiaotong Univ Sch Elect Engn Beijing 100044 Peoples R China

The high precision of the R-on / R-off model makes it suitable for the real-time simulation of high switching frequency power electronic converters (HSFPECs). However, the R-on / R-off model encounters two significant challenges: 1) Neglecting the switching transient process introduces inaccuracies in simulations. 2) Iterative operations when judging the switch status limit the switching frequency range. To address these issues, this paper proposes an improved method that incorporates the effects of switch junction capacitance. The calculated amount is significantly reduced by constructing an equivalent state equation without regarding junction capacitances as state variables and the switch status can be obtained by non-iterative operations. Moreover, this method can ensure the system stability by using backward Euler method and realizes the decoupling between the half-bridge arms, which greatly reduces the workload of judging the switch status for the R-on / R-off model. Finally, the field programmable gate array (FPGA) implementation scheme is presented, and an LLC resonant converter with 30 ns simulation time step and 250 kHz switching frequency is simulated on FPGA. The results derived from the real-time simulation and hardware experiment corroborate the effectiveness and accuracy of the proposed method.

关键词： Switches Capacitance Mathematical models Junctions Transient analysis field programmable gate arrays Switching frequency Switching circuits Power electronics Integrated circuit modeling field-programmable gate array (FPGA) high switching frequency power electronic converters (HSFPECs) noniterative operations real-time simulation RON/ROFF model switch junction capacitance

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MR-Transformer: FPGA Accelerated Deep Learning Attention Model for Modulation Recognition

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IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS 2025年第2期24卷 1221-1233页

作者： Wang, Haiyan Qi, Zhongzheng Li, Zan Zhao, Xiaohui Jilin Univ Coll Commun Engn Changchun 130012 Peoples R China

Modulation recognition has emerged as an intensive research topic to improve the communication efficiency in the future 6G network and plays an important role in the security of electromagnetic spectrum. Various pattern recognition methods have been proposed to enhance the performance of modulation recognition, especially deep learning models showing their emerging performance. In this work, we design a modulation recognition model based on an enhanced Transformer, namely MR-Transformer, which is accelerated on a field programmable gate Array (FPGA). The design of MR-Transformer targets on high recognition accuracy, low power consumption, and high computation efficiency, which is suitable for modulation recognition at edge devices. MR-Transformer leverages attention mechanism to extract global features and correspondingly enhance the recognition accuracy. An improved matrix multiplication operation and enhanced Design Space Exploration (DSE) method are proposed in MR-Transformer to improve the computation efficiency and reduce resource consumption. We conduct comprehensive experiments to evaluate the performance of MR-Transformer on three platforms, i.e. Central Processing Unit (CPU), Graphics Processing Unit (GPU), and FPGA, based on two open-source datasets. According to the evaluation results, the MR-Transformer based on FPGA shows the best performance compared with the baseline models considering accuracy, power consumption, and computation efficiency.

关键词： field programmable gate arrays Feature extraction Modulation Transformers Accuracy Computational modeling Computational efficiency Parallel processing Deep learning Power demand modulation recognition FPGA transformer

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High-efficiency multilevel inverter topology with minimal switching devices for enhanced power quality and reduced losses

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IET POWER ELECTRONICS 2025年第1期18卷

作者： Jayaraman, Ramesh Thamizharasan, Sandirasegarane Baskaran, Jeevarathinam Meena, Veerpratap Bahadur, Jitendra Jadoun, Vinay Kumar Siddhartha Acad Higher Educ Dept Elect & Elect Engn Vijayawada Andra Pradesh India CK Coll Engn & Technol Dept Elect & Elect Engn Cuddalore Tamil Nadu India PSG Inst Technol & Appl Res Dept Elect & Elect Engn Coimbatore Tamilnadu India Natl Inst Technol Jamshedpur Dept Elect Engn Jamshedpur 831014 Jharkhand India Amrita Vishwa Vidyapeetham Dept Elect & Commun Engn Amrita Sch Engn Bengaluru India Manipal Acad Higher Educ Manipal Inst Technol Dept Elect & Elect Engn Manipal 576104 India

The advent of multilevel inverters (MLIs) has brought significant advancements in their applications across industrial, residential, and renewable energy sectors, as they produce high-quality output voltage that closely approximates a sinusoid in small voltage steps or levels, resulting in lower total harmonic distortion (THD) and reduced electromagnetic interference (EMI). However, the MLI topologies require more switching unidirectional/bidirectional semiconductor devices with high standing voltage, gate drivers, and complex control strategies while attaining higher voltage levels. From this perspective of reducing component count and gate drivers, the objective is to develop a new MLI topology that overcomes the drawbacks above. In this article, a novel MLI topology is introduced in symmetric and asymmetric configurations aiming to attain fewer power electronic devices for synthesizing more steps in the load voltage in contrast with conventional topologies. The idea behind the approach is coining the series connected voltage source, which imbibes bidirectional current flow with an additional voltage source for performing algebraic operation under asymmetrical modes of operation. The proposed topology uses minimal on-state switching devices leading to a diminution of power loss and voltage drop. The suggested topology is optimized for a fewer number of power devices, an input DC supply, and auxiliary gate drivers to achieve a maximum voltage level in the load terminals. The suggested topology has been verified in SIMULINK and the laboratory prototype is constructed in line with the simulated response to demonstrate its performance suitable for real-time applications.

关键词： field programmable gate arrays harmonic distortion invertors real-time systems

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A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2025年第3期44卷 1003-1016页

作者： Jiang, Xun Wang, Jiarui Mai, Jing Di, Zhixiong Lin, Yibo Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China Peking Univ Sch Comp Sci Beijing 100871 Peoples R China Univ Elect Sci & Technol China Sch Integrated Circuits Sci & Engn Chengdu 610031 Peoples R China Peking Univ Beijing Adv Innovat Ctr Integrated Circuits Beijing 100871 Peoples R China Peking Univ Inst Elect Design Automat Wuxi 214000 Peoples R China

Routing is the most time-consuming step in the implementation flow of field programmable gate array (FPGA) designs. With the advance in transistor scaling and system integration, hardware resources in FPGA devices are growing in a larger quantity and diversity. The routing architecture is designed to be more complicated for mapping RTL designs to FPGA devices correctly, which brings significant challenges for current FPGA routing algorithms. The key challenges for routing algorithms lie in large solution space and heavy congestion, especially for high-fanout nets (HFNets). We propose a partition-based algorithm to accelerate the routing of HFNets, which decomposes the global routing guide to shrink the search space for connecting each sink. Meanwhile, the congestions existing inside configurable logic block (CLB) are hard to handle by traditional sequential negotiation-based algorithms, because the industrial routing architecture is quite complex. We propose a concurrent intra-CLB rerouting algorithm to effectively resolve routing congestion inside a CLB tile induced by connections between intra-CLB logic pins, e.g., logic elements and switch boxes. Experimental results on modified ISPD2016 benchmarks demonstrate that our framework can achieve 100% routability in 9.8% less wirelength and $11\times $ less runtime, while the state-of-the-art VTR 8.0 routing algorithm fails at 7 of 12 benchmarks.

关键词： Routing field programmable gate arrays Computer architecture Pins Logic Video recording Partitioning algorithms integer linear programming routing Steiner trees partitioning algorithms

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Fail-Safe Logic Design Strategies Within Modern FPGA Architectures

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IEEE ACCESS 2025年 13卷 3434-3452页

作者： Bhakta, Priya A. Plusquellic, Jim Suchanek, Andrew Mannos, Tom J. Univ New Mexico Dept Elect & Comp Engn Albuquerque NM 87131 USA Sandia Natl Labs Albuquerque NM 87123 USA

Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. In this paper, we investigate a circuit level technique as mitigation for single event upsets (SEUs) and fault injection attacks on field programmable gate arrays (FPGAs), and analyze the effectiveness of the technique as a fail-safe monitor for an encryption algorithm. The propagation of fault effects through FPGA primitives including lookup tables (LUTs) and programmable interconnect points (PIPs) is assessed within an FPGA architecture created using an open source tool, and validated using fault injection experiments on an FPGA. The analysis reveals additional vulnerabilities exist within reconfigurable architectures over those in equivalent fail-safe application specific integrated circuit (ASIC), thus requiring a more elaborate network of redundant circuits and checking logic. The configuration memory bits (CMBs), which configure routing and designate logic functions within the LUTs of the FPGA, add complexity to fail-safe design strategies by introducing additional fault conditions and fault propagation paths. A resource-efficient fail-safe circuit design technique called DEsign for Fail-safe in reCONfigurable systems (DEFCON) is proposed. The benefits and limitations associated with DEFCON are described in the context of fault injection experiments carried out as simulations and in FPGA hardware.

关键词： Circuit faults field programmable gate arrays Table lookup Logic gates Routing Monitoring Redundancy Prevention and mitigation Hardware Fault tolerant systems DEFCON duplication-with-comparison fail-safe fault injection attacks single-event-upsets fault tolerance dynamic partial reconfiguration

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A Low-Latency and High-Performance Microwave Photonic AOA and IFM System Based on Deep Learning and FPGA

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IEEE SENSORS JOURNAL 2025年第6期25卷 9934-9945页

作者： Zhang, Longlong Li, Yin Liao, Xuan Hu, Xiang Peng, Yuanxi Zhou, Tong Natl Univ Def Technol Coll Comp Sci & Technol Changsha 410073 Peoples R China Acad Mil Sci PLA China Natl Innovat Inst Def Technol Beijing 100071 Peoples R China Natl Univ Def Technol Beijing Inst Adv Study Changsha 410073 Peoples R China

The angle of arrival (AOA) estimation and instantaneous frequency measurement (IFM) are the important aspects of radar, communication, and electronic warfare, and there is an urgent need to find intelligent solutions that are faster and more accurate than the traditional methods. Currently, deep learning (DL) has increasingly strong learning and feature extraction capabilities, which brings new opportunities to the field of electromagnetic signal processing. However, the models in DL have a large number of parameters, high storage requirements, and long computational latency and not practical for deploying applications on resource-limited devices. In this article, we build a complete AOA and IFM system for the first time, taking advantage of microwave photonics (MWPs) technology, DL, and features of field-programmable gate array (FPGA). Then, a novel hardware-friendly pruning-quantization-iteration compression (PQIC) algorithm is proposed for the post-processing of MWP signal measurement applications. By reducing the data width from 32 bits to four bits, the compressed algorithm reduces parameter storage requirements and hardware implementation complexity with negligible performance loss. Finally, we deploy the acceleration system and test the actual collected signal data on FPGA while running 200 MHz. The results show that with a 14x model compression and a 3.99x reduction in operations, the accuracy of AOA reaches 98.82%, with the mean absolute error (MAE) of 0.27 degrees. More importantly, the running latency is only 20.78 mu s, meeting the real-time processing requirements of MWP signal processing. It is also applicable to real-world signal intelligence processing and demonstrates superior performance compared to other existing algorithms in this field.

关键词： Microwave measurement Microwave theory and techniques field programmable gate arrays Phase measurement Signal processing algorithms Frequency measurement Accuracy Signal processing Optical sensors Acceleration system angle of arrival (AOA) estimation deep learning (DL) field-programmable gate arrays (FPGAs) instantaneous frequency measurement (IFM) microwave photonic (MWP) microwave photonic (MWP)

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Evaluating the Influence of Execution Speed on Real-Time Simulation Accuracy: A Buck Converter Case Study

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IEEE ACCESS 2025年 13卷 15168-15177页

作者： Camacho, Jesus Ibarra, Luis Ponce, Pedro Tecnol Monterrey Sch Engn & Sci Mexico City 14380 Mexico Tecnol Monterrey Inst Adv Mat Sustainable Mfg Monterrey 64849 Mexico

The relevance of power electronics converters is undoubted and is growing in many modern applications. Real-Time Simulation (RTS) is commonly used to test converters before deployment, assessing what-if scenarios that may pose risks or add costs. RTS can also run alongside the real system for online assessment through direct comparison. Most of the research in this area focuses on accelerating the execution of RTS to comply with shorter sampling times. As a result, field-programmable gate arrays (FPGAs) are typically preferred, while microcontrollers have been mostly overlooked under the premise of their inferior throughput. However, it has not been assessed how fast a RTS must actually be, beyond the usual suggestion of always accelerating its execution. Therefore, this study was intended to find a fair balance between computational requirements and RTS error, aiming to identify operating conditions applicable to digital systems. A case study on a commercial buck converter with a RTS in a microcontroller tested the modeling Integral Squared Error (ISE). The RTS was run at various execution frequencies while the input PWM frequency varied between 2 and 100 times faster;6,000 randomized duty cycles (0.2 to 0.8) were tested and their ISEs were statistically analyzed. The results show that smaller RTS time steps do not necessarily reduce the error. The minimum ISE occurred when the RTS execution frequency was about 35 to 45 times higher than the PWM frequency, regardless of the RTS frequency. This study challenges the idea that faster RTS always means lower error and demonstrates the potential of low-end digital devices for RTS.

关键词： Microcontrollers Mathematical models Buck converters Pulse width modulation Real-time systems field programmable gate arrays Software packages Hardware-in-the-loop simulation Power electronics Buck converter execution speed hardware in the loop microcontroller power electronics real-time simulation

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Pulsewidth-Modulated Timed Array for Independently Controllable Harmonic Beams in Multiuser Wireless Scenario

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IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION 2025年第1期73卷 279-292页

作者： Arjun, K. S. Prahannathan, V. Gopika, R. Saha, Chinmoy Indian Inst Space Sci & Technol Dept Avionics Thiruvananthapuram 695547 India

This article presents a novel time modulated array (TMA) or timed array, which can be a potential candidate for enabling versatile, multiuser heterogeneous wireless systems, with each user uniquely powered by a switching harmonic frequency. In the proposed timed array, each switch at the antenna element feed is controlled with a pulsewidth-modulated (PWM) signal, carrying the phase information of a triangular wave and a reference signal. This PWM timed array architecture offers precise control of the number of radiated harmonics, independent steering of individual beams, and radiated beam power levels. The user-definable beam steering makes the system an efficient candidate for dynamic multiuser applications demanding stringent scanning capabilities. The proposed timed array is experimentally validated using a 1x4 microstrip antenna array at 2.4 GHz with a PWM control signal generated by a PYNQ-Z2 field-programmable gate array (FPGA). The effect of PWM signal waveform and a systematic design methodology to achieve desired harmonics, beam direction, and power level are systematically presented in this article. Furthermore, the RF switching speed constraints and effects on PWM timed array architecture are discussed in detail.

关键词： Harmonic analysis Pulse width modulation Switches Power system harmonics Control systems Antenna arrays Wireless communication Radio frequency field programmable gate arrays Antennas Beam steering multiharmonic pulsewidth modulated (PWM) time-modulated array (TMA)

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