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A Parallel Computing Scheme Utilizing Memristor Crossbars for Fast Corner Detection and Rotation Invariance in the ORB Algorithm

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IEEE TRANSACTIONS ON COMPUTERS 2025年第3期74卷 996-1010页

作者： Hong, Qinghui Jiang, Haoyou Xiao, Pingdan Du, Sichun Li, Tao Hunan Univ Coll Comp Sci & Elect Engn Changsha 410082 Peoples R China

The Oriented FAST and Rotated BRIEF (ORB) algorithm plays a crucial role in rapidly extracting image keypoints. However, in the domain of high-frame-rate real-time applications, the algorithm faces challenges of the speed and computational efficiency with the increase in both the size and quantity of images. To address this issue, an ORB algorithm accelerator based on a computing-in-memory (CIM) circuit is firstly proposed in this paper, which replaces the iterative calculations in traditional methods with one-step parallel analog computation. The proposed accelerator improves algorithm computational efficiency through CIM technology and enhances algorithm speed through parallel computation. Simulation demonstrate that the proposed method exhibits an average processing speed 22 x faster than traditional methods and obtains more uniform corners distribution in large-scale images.

关键词： Gray-scale Feature extraction Computer architecture Memristors Hardware field programmable gate arrays Common Information Model (computing) In-memory computing Corner detection Computers Computing in memory (CIM) hardware accelerator feature extraction ORB algorithm memristor

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Evaluation of Timing and Pulse Shape Analysis Method for the Measurement of Photoneutron Energy Distribution Using Commercially Available Digitizer

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 538-544页

作者： Tran, Kim-Tuyet Sanami, Toshiya Bui, Tuan-Khai High Energy Accelerator Res Org KEK Radiat Sci Ctr Tsukuba 3050801 Japan Grad Univ Adv Studies SOKENDAI Sch High Energy Accelerator Sci Dept Accelerator Sci Hayama 2400115 Japan High Energy Accelerator Res Org KEK Int Ctr Quantum Field Measurement Syst Studies Uni Tsukuba 3050801 Japan

Photonuclear reactions triggered by high-energy photons are crucial in simulations for both nuclear physics and radiation transport. In such simulations, understanding the photonuclear reaction cross section and the energy distribution of secondary particles, particularly neutrons, is vital owing to the energy-dependent nature of neutrons. Experimental investigations have used monoenergetic, linearly polarized photons in the range of tens of MeV to measure neutron energy distributions resulting from photonuclear reactions. In an experiment, we adopted an electronic circuit and detector system based on the time-of-flight (ToF) method and particle identification to determine the energy distribution of emitted neutrons. This system required precise nanosecond-level timing and the ability to distinguish signals with millivolt-level differences. The advent of GHz sampling digitizers, field-programmable gate arrays (FPGAs), and high-speed interfaces allows these measurements to be conducted using commercially available single-board electronics. This study highlights the data acquisition (DAQ) process using a 1-GHz sampling rate, 14-bit resolution, FPGA-based real-time signal processing, and 1-MHz throughput digitizer (APV8104 by TechnoAP Company). Moreover, it provides a detailed description of the motivation behind the study, underscoring the importance of the energy spectrum. We evaluated the digitized data for their applicability and analyzed the raw data for potential improvements in timing and signal differentiation compared to those of traditional FPGA-based schemes.

关键词： Photonics Neutrons Detectors Data acquisition Measurement by laser beam Laser beams Ethernet Energy measurement field programmable gate arrays Storage rings Digitizer laser Compton scattering (LCS) photons photoneutron photonuclear

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Integration of DPDK for Real-Time Communication in the Elettra Synchrotron Orbit Feedback Control System: Jitter and Latency Optimization

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IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS 2025年

作者： Anastasio, Luca Bogani, Alessio Cappelli, Mauro Di Gennaro, Stefano Gaio, Giulio Lonza, Marco Univ Aquila Dept Informat Engn Comp Sci & Math I-67100 Laquila Italy Elettra Sincrotrone Trieste SCpA I-34149 Basovizza Italy Univ Aquila Ctr Excellence DEWS I-67100 Laquila Italy

The scope of this work is the evaluation of the software-driven platform for the upcoming global orbit correction feedback system for the Elettra 2.0 synchrotron to be deployed in 2026. Here, a detailed analysis including latency and jitter of a full acquisition system based on Ethernet and an Intel server running Linux and DPDK is presented for the first time in the literature of particle accelerators. This assessment has primarily focused on measuring the receiving time of hundreds of remote devices based on FPGAs and their data processing. Unlike the current orbit correction system, which is distributed across multiple CPUs and involves heterogeneous hardware, the approach presented here is based on the centralization of the data acquisition and processing within a single server. The latter is to be connected to a maximum of a hundred of sensors via Ethernet ensuring, under heavy CPU and memory load, real-time communication with these peripherals through the utilization of the DPDK framework in conjunction with core isolation capabilities of multicore CPUs. The expected performance in terms of feedback repetition rate is between 40 and 100 kHz. The results show that the global orbit feedback for the Elettra 2.0 synchrotron can be definitely realized on the proposed hardware, which has many advantages over the current global orbit feedback system. This work demonstrates the viability of a software-based solution for high-frequency feedback, matching the latency and determinism of specialized FPGA systems. It introduces a scalable model for high-speed feedback applications, such as nuclear fusion and advanced manufacturing, validating DPDK as an alternative for these fields. This foundation supports future exploration of HPC-based centralized control systems in scientific infrastructures.

关键词： Orbits Synchrotrons Sensors Actuators field programmable gate arrays Ethernet Real-time systems Jitter Servers Sensor systems DPDK feedback systems network performance particle accelerators real-time systems

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100-Gbit/s UDP Data Acquisition on Linux Using AF_XDP: The TRISTAN Detector

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 295-300页

作者： Mostafa, Jalal Tcherniakhovski, Denis Chilingaryan, Suren Balzer, Matthias Kopmann, Andreas Becker, Jurgen Karlsruhe Inst Technol Inst Data Proc & Elect D-76344 Eggenstein Leopoldshafen Germany Karlsruhe Inst Technol Inst Tech Informat Verarbeitung D-76131 Karlsruhe Germany

A growing number of detectors produce data rates of more than 100 Gb/s, which often necessitate software-defined data processing to operate. Because of its simplicity, the user datagram protocol (UDP) offers a straightforward method for integrating such detectors with online computing resources that host the data processing software. Nevertheless, conventional technologies-such as POSIX sockets-are either ineffective or difficult to apply on detector boards based on field-programmable gateway arrays (FPGAs). The new Linux AF_XDP sockets (XSK) are a novel method that uses zero-copy methods to target high data speeds. In this article, we present "DQDK," a novel data acquisition (DAQ) framework based on AF_XDP and UDP for readout systems with more than 100 Gb/s. We evaluate our framework for the TRItium sterile antineutrino (TRISTAN) detector whose rates are expected to reach 200 Gb/s. We describe our experience developing a TRISTAN detector readout system using AF_XDP.

关键词： Data acquisition Detectors Software Protocols Linux Sockets field programmable gate arrays AF_XDP data acquisition (DAQ) high-throughput detectors remote direct memory access (RDMA) user datagram protocol (UDP) zero-copy networking

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Network-Distributed Data-Acquisition System for Photoproduction Experiments With LEPS2

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 348-354页

作者： Ryu, Sun Young Ajimura, Shuhei Kobayakawa, Ryo Mizutani, Keigo Yosoi, Masaru Watanabe, Ken Sada, Yuta Hotta, Tomoaki Ishikawa, Takatsugu Niiyama, Masayuki Ahn, Jung Keun Osaka Univ Res Ctr Nucl Phys Osaka 6870041 Japan Tohoku Univ Res Ctr Accelerator & Radioisotope Sci Sendai 9820826 Japan Mitutoyo Corp Kawasaki Kanagawa 2138533 Japan Kyoto Sangyo Univ Dept Phys Kyoto 6038555 Japan Korea Univ Dept Phys Seoul 02841 South Korea

The LEPS2 data-acquisition (DAQ) system is built on the network-distributed DAQ-middleware framework. It consists of gatherers that collect data from detector subsystems, mergers that integrate data from gatherers, an event builder and a logger that writes data to files in the DAQ software. The 10K time projection chamber (TPC) pad signals are transmitted to 16-channel flash analog-to-digital converter (FADC) boards and transferred through the SpaceWire protocol to DAQ software components. We need to handle different subsystems with extensive variation in the number of channels. We have successfully commissioned the DAQ system of the LEPS2 detector, which includes a TPC, drift chambers (DCs), resistive plate chambers, Pb/scintillator sampling calorimeters, and neutron counters (NCs). The LEPS2 DAQ system reads approximately 10K channels from TPC and 5K channels from other detector components at a trigger rate of 100-200 Hz and an event size of 40 MB/s.

关键词： Data acquisition field programmable gate arrays Protocols Nuclear physics Detectors Wires Photonics Data-acquisition (DAQ) middleware LEPS2 photoproduction space-wire time projection chamber (TPC)

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The Front-End Electronics for the Hyper-Kamiokande Far Detector

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 631-638页

作者： Di Nola, A. Hyper Kamiokande Collaboration Univ Napoli Federico II Dept Phys Ettore Pancini I-80138 Naples Italy INFN Naples I-80126 Naples Italy

A new front-end (FE) board has been designed and developed for the photomultipliers used in the Hyper-Kamiokande (HK) experiment, the new-generation water Cherenkov detector in Japan. The HK far detector will be instrumented by 20000 Hamamatsu R12860 photomultiplier tubes (PMTs), a new and improved version of the photosensors used in the previous experiment Super-Kamiokande (SK). These PMTs have been specially developed by Hamamatsu to create a sensor that improves the quantum efficiency and the ability to withstand higher pressures that will be present in HK. The new PMT electronics will be placed in a pressure vessel alongside the PMTs underwater. The use of new photosensors and the use of underwater vessels require the development of a new board with improved digitizing capabilities and a long life expectancy. This work describes the design and features of the new digitizer FE board designed for HK: the stringent requirements imposed by the collaboration, to how the board was designed, and concluding with the tests performed on the last proven prototypes before mass production.

关键词： Neutrino sources Detectors Circuits Impedance Receivers Protection Photomultipliers Operational amplifiers Iron field programmable gate arrays Analog circuits neutrinos photomultipliers readout electronics

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Design and Validation of a Very Low-Power Phasor Measurement Unit for the Distribution System

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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS 2025年第2期61卷 3553-3562页

作者： Lythgoe, Zachary J. Long, Thomas F. Buchholz, Michael J. Livernois, Anthony R. Kanuteh, Kebba Allee, David R. Pal, Anamitra Graham, Ian R. Drummond, Zachary D. Arizona State Univ Dept Elect Comp & Energy Engn Tempe AZ 85287 USA BG Prod Inc Wichita KS 67213 USA Naval Surface Warfare Ctr Philadelphia PA 19112 USA Univ Penn Dept Phys & Astron Philadelphia PA 19104 USA DEVCOM Army Res Lab Adelphi MD 20783 USA

Phasor measurement units (PMUs) provide a high-resolution view of the power system at the locations where they are placed. As such, it is desirable to place them in bulk in low-voltage distribution circuits. However, the power consumption of a PMU/micro-PMU is on the order of Watts (W), requiring an external power supply, which both increases the overall cost as well as limits the locations where they can be placed. This work details the hardware design of a PMU capable of measuring and reporting voltage and current phasors for a single-phase system at an average power consumption of only 30.8 mW-one to two orders of magnitude lower than existing academic and commercial PMUs. This enables the proposed PMU to run for two weeks using an 11-Wh battery or indefinitely if paired with an inexpensive solar panel. A test bench developed in accordance with the 2018 IEC/IEEE 60255-118-1 PMU Standard confirms the accuracy of this PMU, and a Fluke 6135A PMU calibration system evaluates its performance under realistic conditions. Given its low power consumption, the proposed design is expected to accelerate adoption of PMUs in modern distribution grids.

关键词： Phasor measurement units Sensors Voltage measurement Low-pass filters Conductors Power demand field programmable gate arrays Batteries Signal processing algorithms Sensor arrays Digital signal processing distribution system field-programmable gate array (FPGA) phasor measurement unit (PMU) smart grid

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FPGA Implementation of Digital Filters for China Dark Matter Experiment

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第2期72卷 189-196页

作者： Yang, Haoyan Xue, Tao Pan, Qiutong Liang, Bo Liu, Yinong Li, Jianmin Tsinghua Univ DEP Beijing 100086 Peoples R China

The direct detection of light dark matter is a prominent topic in international physics research. Weakly interacting massive particles (WIMPs) are the leading dark matter candidates. The scientific goal of the China Dark matter EXperiment (CDEX), located in the China Jinping Underground Laboratory (CJPL), is to detect light dark matter candidates using a high-purity germanium (HPGe) detector array. In 2013, CDEX-1B achieved the most sensitive experimental results for spin-independent WIMPs below 4 GeV/c(2 ), with a data collection of 783 kg & sdot;day . In 2018, CDEX-10 obtained the most sensitive experimental results for spin-independent WIMPs in the 4-5- GeV/c(2) range, using 102.8 kg & sdot;day of data. The CDEX-50, which is currently under construction, is expected to achieve an energy threshold of 100 eV, which poses a huge challenge to the waveform digitization system. However, the reduction of the threshold is constrained by the analog shaping system's ability to suppress preamplifier noise. Therefore, this article studies the implementation of a CR-(RC)4 filter, a trapezoidal shaping filter, and a digital penalized least mean square (DPLMS) filter on a field programmable gate array (FPGA). The DPLMS filter consumes the most resources, followed by the CR-(RC)(4), while the trapezoidal filter consumes the least amount of resources. An experimental platform based on a Broad Energy Germanium (BEGe) detector was built to compare different digital filters and analog shaping systems. The results show that the DPLMS filter is the most effective at improving the signal-to-noise ratio of the preamplifier output. Compared to the analog shaping systems used in CDEX-1B and CDEX-10, the standard deviation of the baseline noise was reduced from 216.3 to 170.0 eV. The energy corresponding to a 99% trigger efficiency was reduced from 862 to 712 eV, a decrease of about 17.4%. These results can provide a reference for upgrading...

关键词： Noise Digital filters Detectors Dark matter field programmable gate arrays Optical filters Germanium Filtering theory Preamplifiers JFETs Dark matter experiment digital filter field programmable gate array (FPGA) high-purity germanium (HPGe) detector Jinping Underground Laboratory

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An analytical timing-driven placer for modern heterogeneous FPGAs

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JOURNAL OF SUPERCOMPUTING 2025年第1期81卷 1-18页

作者： Lin, Zhifeng Chen, Yilu Xie, Yanyue Chen, Chuandong Yu, Jun Chen, Jianli Fuzhou Univ Ctr Discrete Math & Theoret Comp Sci Fuzhou 350108 Peoples R China Xiamen Univ Technol Sch Comp & Informat Engn Xiamen Peoples R China Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA Fuzhou Univ Sch Microelect Fuzhou 350108 Peoples R China Shanghai Fudan Microelect Grp Co Ltd Shanghai 200433 Peoples R China Fudan Univ Sch Microelect Shanghai 200433 Peoples R China

As the feature sizes keep shrinking, interconnect delays have become a major limiting factor for FPGA timing closure. Traditional placement algorithms that address wirelength alone are no longer sufficient to close timing, especially for the large-scale heterogeneous FPGAs. In this paper, we propose an analytical placement algorithm for FPGA timing optimization. By leveraging the look-up table technique, we first present a smoothed routing-architecture-aware timing model to calculate each connection delay rapidly. Then, an effective wirelength and timing co-optimization strategy is developed to produce high-quality placements without timing violations. Finally, a delay optimal region-based detail placement strategy is designed to further improve the timing performance. Compared with Vivado 2023.1 on AMD benchmark suites for xc7k325t device, experimental results show that our algorithm achieves not only a 3.2% improvement in worst slack, but also a 2.5% reduction for routed wirelength.

关键词： field programmable gate arrays Physical design Placement Timing optimization

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Ultrafast Ultrasound Imaging System With Beamforming on Single FPGA

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷

作者： Zhang, Xi Qi, Sheng Li, Yifan Xu, Lijun Ma, Jianguo Beihang Univ Sch Instrumentat & Optoelect Engn Beijing 100191 Peoples R China Shandong Jianzhu Univ Sch Sci Jinan 250100 Peoples R China

Ultrafast ultrasound imaging technologies, such as ultrasound localization microscopy (ULM) and functional ultrasound (FUS), are gaining significant attention in the ultrasound field, driving the demand for higher frame rates in open ultrasound systems. However, current open ultrasound systems face the challenge of balancing high imaging frame rates with the complexity of hardware architecture. This work reports the detailed implementation and hardware architecture of a 128-channel ultrafast ultrasound platform based on a single field-programmable gate array (FPGA). This platform connects the ultrasound card to a personal computer (PC) via peripheral component interconnect express (PCIe) 3.0, providing excellent compatibility. The platform uses custom instructions to implement flexible parameter configuration in the FPGA. It can control the transmission and reception of signals, the output of raw or beamformed RF data, and the sampling depth. Additionally, a 64 sub-aperture delay-and-sum (DAS) beamformer within the FPGA is implemented in the platform. This beamformer gives output as a 128x2048 image at 10000 frames/s (fps) using plane wave. The core components of the platform measure only 12x21 cm, achieving a compact design while delivering high-frame-rate (HFR) imaging.

关键词： Ultrasonic imaging field programmable gate arrays Delays Array signal processing Imaging Hardware Computer architecture Software Radio frequency Software algorithms Beamforming field-programmable gate array (FPGA) ultrasound system ultrafast ultrasound

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