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Efficient Hierarchical Hash-Based Multi-field Packet Classification With Fast Update for Software Switches

IEEE ACCESS 2025年 13卷 28962-28978页

作者： Chang, Yeim-Kuan Lin, Yu-Hung Chang, Jia-Chang Li, Wenjun Hsieh, Sun-Yuan Natl Cheng Kung Univ Dept Comp Sci & Informat Engn Tainan 70101 Taiwan Peng Cheng Lab Network Commun Res Ctr Shenzhen 518066 Peoples R China Natl Chi Nan Univ Dept Comp Sci & Informat Engn Puli 54561 Taiwan

Packet classification that attracts wide interests in router designs is one of the most important functionalities to provide services such as QoS, packet forwarding, firewall, and VPN. With the expanding network and the rise of software-defined networks, software routers/switches are needed to enable a wide variety of network applications in physical or virtual networks. Existing packet classification schemes used in software switches had become difficult to support a fast classification process for large multi-field rulesets. In addition, it is necessary to have fast updates that are frequently performed. In this paper, we propose a hash-based partitioning scheme for a multi-field packet classification problem. The proposed design is a 4-level data structure based on hashing. It selects the suitable fields to construct the data structures so that we can quickly narrow down the search space to find matched rules. The hash table used in the proposed design is more effective than the existing search data structures. Our experimental results show that the proposed scheme performs best in all four-performance metrics of memory consumption, construction time, classification time, and update time compared with the six most recently proposed schemes, CutTSS, TabTree, TupleMerge, CutSplit, PartitionSort, and PSTSS. The average number of bytes required per rule is only 27-99% of that needed in these schemes. The construction time of our scheme is 2.06 to 327.82 times faster than these schemes. Most importantly, the proposed scheme is 1.92-16.65 and 2.22-4.54 times faster than these six schemes in throughput and update time, respectively.

关键词： IP networks Control systems Protocols Software Decision trees Classification algorithms Memory management Software defined networking field programmable gate arrays Computer science Packet classification hash table tuple space search linear search OpenFlow

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Protection of systems containing IBR from asymmetrical ground faults using zero sequence current with hardware implementation on FPGA

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IET GENERATION TRANSMISSION & DISTRIBUTION 2025年第1期19卷

作者： Pannell, Jason Gokaraju, Ramakrishna Univ Saskatchewan Elect & Comp Engn Saskatoon SK Canada

The addition of inverter-based generation to the power system complicates protective relaying in several ways: the magnitude of the fault current will be altered based upon the location of the fault relative to the inverter-based resource, and the response to a fault will be different than traditional generation. The relatively low fault current of inverter-based resources presents difficulties in differentiating faults from increased loads. Additionally negative sequence relays may fail in the presence of IBR's due to the negligible negative sequence current produced by the IBR during a fault. This paper presents a novel method to allow the sensitive sub-cycle detection, and determination of the relative location, of asymmetrical ground in systems containing inverter-based resources through phasor analysis of zero sequence current. Least Error Squares Estimation is applied to the fault currents to improve the detection time of these faults, with low computational overheard for hardware implementation. Hardware implementation of the protection scheme on an Intel Cyclone IV-E FPGA is completed and correct operation of the scheme is verified for the raw samples, as well as five and seven sample LES phasor estimations. Hardware testing is compared to the EMT output to confirm the results.

关键词： field programmable gate arrays power system protection PWM invertors renewable energy sources

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100 Gbps Low-Latency Protocol Processing and FPGA Implementation

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IEEE ACCESS 2025年 13卷 53804-53814页

作者： Lei, Liangwei Zhu, Funan Lu, Shaowen Du, Yaohui Li, Jiawei Hou, Xia Shanghai Univ Sch Microelect Shanghai 200444 Peoples R China Chinese Acad Sci Shanghai Inst Opt & Fine Mech Aerosp Laser Technol & Syst Dept Shanghai 201800 Peoples R China

With the ongoing evolution of integrated space-air-ground networks, space laser communications face increasingly stringent demands for low latency and high throughput in high-speed data transmission. To meet these requirements, this paper presents a low-latency protocol stack processing architecture based on field programmable gate Array (FPGA) and provides an in-depth investigation into its implementation at the hardware level. By employing a nonindependent four-channel data interface, the proposed architecture significantly enhances the alignment efficiency during the data framing and deframing processes, thereby mitigating the overhead associated with large-volume data handling. In addition, an adaptive inter-frame interval control mechanism is introduced to effectively reduce the data processing latency. Experimental validation on a Xilinx Virtex UltraScale VCU108 development board, equipped with a 100G CFP2-DCO optical module, demonstrates that the system achieves a throughput of up to 98.1 Gbps, with an end-to-end latency of approximately 300 ns. Compared to other FPGA-based solutions, which achieve a best-reported protocol processing latency of approximately 1.3 mu s in existing research, our method achieves at least a 4x improvement in overall data processing speed.

关键词： Protocols IP networks Throughput Low latency communication Data processing Data communication Transceivers field programmable gate arrays Satellite broadcasting High-speed optical techniques FPGA low-latency protocol stack data alignment adaptive inter-frame interval control high throughput

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FPGA-Based Hardware Implementation of Blue-Noise Stacked Error Diffusion Multitoning

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Hu, Qishi Lau, Daniel L. Venugopal, Rishvanth Kora Heath, J. Robert Univ Kentucky Dept Elect & Comp Engn Lexington KY 40506 USA Cummins Inc Columbus IN 47201 USA

Blue-noise stacked error diffusion (BSED) is a high-quality multi-level halftoning (multitoning) algorithm based on the blue-noise dithering model. This algorithm transforms a multitoning task into multiple error diffusion halftoning tasks, each producing a sub-halftone with inter-layer dependencies. These sub-halftones are stacked together to form the final visually pleasing multitone with blue-noise characteristics. In this research, the significant potential for parallelizing this multitoning algorithm inspires the design of a novel parallel raster image processor (NPRIP) for highly efficient execution, capable of producing an output pixel every six clock cycles at a clock frequency of 200 MHz. A hardware prototype based on the Xilinx Zynq SoC implements our raster image processor design on the FPGA within the SoC. The prototype is also capable of a conventional software implementation of the BSED algorithm running on the ARM CPU within the SoC. Output images from the prototype are successfully validated in both the spatial and frequency domains. Benchmark results demonstrate a consistent speedup exceeding 30x with FPGA co-processing compared to conventional sequential execution on the ARM CPU, reaching a maximum processing speed of 3.963 megapixels per second.

关键词： Image color analysis field programmable gate arrays Printing Ink Frequency modulation Head Parallel processing Software Prototypes Parallel architectures Digital halftoning multitoning error diffusion FPGA parallel architecture hardware acceleration Zynq SoC

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Study of Dynamic Time Over Threshold (DTOT) Method for Application in Spectroscopy Signal Analysis Toward a Low-Complexity Front-End Electronics With High Spectroscopy Resolution and Wide Energy Range

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 749-756页

作者： Holik, M. Ahmadov, F. Sadigov, A. Pavlas, O. Urban, O. Ahmadov, G. Kucera, P. Mamedov, F. Malich, M. Filgas, R. UWB Pilsen FEE Plzen 30100 Czech Republic Czech Tech Univ IEAP Prague 11000 Czech Republic Minist Sci & Educ Inst Radiat Problems AZ-1143 Baku Azerbaijan IDDA Dept Nucl Res AZ-0100 Baku Azerbaijan Joint Inst Nucl Res Dubna 141980 Russia

The traditional approach of spectroscopy signals acquisition and analysis comprises digitization performed ideally by a high bit resolution and short sampling period flash analog-to-digital converter, followed by subsequent digital processing requiring high-computational performance. However, some particular applications cannot implement that traditional approach while demanding comparable high spectroscopic performance due to hardware limitations mainly given by operational conditions, availability of qualified electronic components, power consumption limit, and so on. The dynamic time over threshold (DTOT) conversion method-based processing of spectroscopy signals represents an undemanding alternative contrary to that traditional approach. The detailed study of DTOT method-based processing was performed with the aim to maximize achievable performance via extension of the dynamic range, allowing to process a wide span of input spectroscopy signals. The contribution also presents practical implementation of front-end electronics integrating an enhanced DTOT converter structure dedicated to a gamma detector (based on SiPM-type sensors), while test measurements with common reference radiation sources were performed to provide comparative results.

关键词： Spectroscopy Signal resolution Dynamic range Time measurement Pulse measurements Detectors field programmable gate arrays Complexity theory Standards Noise Detector front-end electronics methodology signal processing spectroscopy

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An Ultrahigh-Throughput and FPGA-Compatible TRNG Based on Dynamic Hybrid Metastability and Jitter Entropy Cells

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第5期72卷 2202-2215页

作者： Wang, Junjun Huang, Zhao Chen, Yin Liu, Jinhui Zhou, Lirong Jiang, Xiaohong Zhou, Jia Wang, Quan Xidian Univ Sch Comp Sci & Technol Xian 710126 Peoples R China Xidian Univ Guangzhou Inst Technol Guangzhou Peoples R China Reitaku Univ Chiba Japan Future Univ Hakodate Sch Syst Informat Sci Hakodate 0410803 Japan Northwestern Polytech Univ Sch Microelect Xian 710060 Peoples R China

The entropy source is the most critical component of a true random number generator (TRNG), which determines the quality of the random numbers. Current TRNGs mainly utilize a specific source of physical randomness as the entropy source, but it is difficult for this method to achieve a balance between low resource overhead and high throughput. This paper explores the self-feedback multiplexer (SFMUX) structure to obtain a novel dynamic hybrid entropy source for TRNGs. Unlike other MUX-based entropy source circuits, our SFMUX cross-connects the outputs of four independent high-frequency ring oscillators (ROs) as the input signals of four MUXs, and the output of each MUX is self-fed back to serve as a selection signal. Thus, the SFMUX can not only output jitter, but also update the selection signal rapidly and randomly, which increases the probability that the SFMUX outputs unstable signals. When using a D-flip-flop (DFF) to sample this signal, the DFF may become metastable. Modeling the entropy source shows that connecting 1-stage ROs and 2-stage ROs to each SFMUX can achieve higher minimum entropy than using ROs with other numbers of stages. The proposed TRNG design is implemented on Xilinx Virtex-6, Artix-7 and Kintex-7 FPGAs. The experimental results demonstrate that our TRNG achieves a maximum throughput of 550 Mbps while using only 6 slices, and it passes the NIST, AIS-31 and Dieharder tests without postprocessing.

关键词： Entropy Jitter Clocks Circuits field programmable gate arrays Throughput Noise Threshold voltage Computer architecture Stochastic processes TRNG hybird entropy source self-feedback jitter metastability FPGA

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Development of Radiation-Tolerant Slow-Control Board Based on Atom Switch-Based FPGA

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第4期72卷 1525-1530页

作者： Ueno, Kazuki Taniguchi, Nanae Sakamoto, Toshitsugu Miyamura, Makoto Osaka Univ Dept Phys Osaka 5600043 Japan KEK Inst Particle & Nucl Studies Tsukuba 3050801 Japan NanoBridge Semicond Inc Tsukuba 3050047 Japan

The atom switch-based FPGA (AS-FPGA) is a promising candidate for high-radiation environments, such as those encountered in future particle physics experiments using accelerators. To assess its feasibility, we conducted neutron and gamma-ray irradiation tests. No single-event upsets (SEUs) were detected at least up to 1011 and 1012 n/cm(2) with and without applied voltage, respectively. The AS-field-programmable gate array (FPGA) withstood displacement damage dose (DDD) levels at least up to 1014 n/cm2 and exhibited no total ionizing dose (TID) effects at least up to 5 and 10 kGy with and without applied voltage, respectively. These results confirm its suitability for high-radiation environments. To facilitate its practical application, we developed an evaluation board to investigate its functions and performance. A prototype slow-control board incorporating a commercial slow-control sensor was constructed. This prototype was used to implement basic logic for temperature data acquisition and tested under neutron irradiation. The slow-control board operated successfully in a high-radiation environment up to 1011 n/cm2, demonstrating the potential of the AS-FPGA and the slow-control board for future particle physics experiments.

关键词： Radiation effects Neutrons field programmable gate arrays Leakage currents Random access memory Gamma-rays Switches High energy physics Current measurement Particle beams Atom switch (AS) field-programmable gate array (FPGA) radiation tolerance slow control

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Long-Horizon FCS-MPC Trained 1-D Convolution Neural Networks for FPGA-Based Power-Electronic Converter Control With a Si/SiC Hybrid Converter Case Study

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2025年

作者： Li, Ning Yu, Hao Finney, Stephen Judge, Paul D. Univ Edinburgh Sch Engn Edinburgh EH8 9YL Scotland

Conventional long-horizon finite-control-set model predictive control (FCS-MPC) for power electronics has two main real-time implementation problems: 1) calculation burden and latency;and 2) high hardware resource requirements on real-time platforms such as FPGA. To solve these problems, machine learning models have been proposed using model predictive control results as offline training data to train an artificial neural network (ANN), which will be implemented in the real-time controller instead of the original model predictive control model. In this way, the ANN reduces the online calculation burden and the hardware resource requirements. In this article, an FPGA-based 1-D convolution neural network (CNN) for long-horizon FCS-MPC is proposed. To simplify the network model and reduce the hardware resources further, model compression techniques of pruning, fine-tuning, and quantization are implemented. The proposed model is verified using a parallel hybrid converter as a case study converter, with performance and hardware resource requirements compared to conventional FCS-MPC and multilayer perceptron (MLP) models. The results show that the proposed compressed CNN model can reduce FPGA DSP resource requirements by 75% compared to a FCS-MPC model and an MLP models, while also achieving comparable or superior performance.

关键词： Hafnium Computational modeling Real-time systems Hardware Convolutional neural networks Bridge circuits Vectors Switches field programmable gate arrays Predictive control Artificial neural network (ANN) convolution neural network (CNN) model predictive control parallel hybrid converter (PHC)

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Real-Time Simulation Method for Power Electronic Converters With Low Resource Consumption

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IEEE TRANSACTIONS ON POWER ELECTRONICS 2025年第4期40卷 4695-4700页

作者： Sun, Zonghui Wang, Guangsen Li, Zhuolan Guo, Xizheng Zhang, Yu Huazhong Univ Sci & Technol Sch Elect & Elect Engn Wuhan 430000 Peoples R China Naval Univ Engn Sch Elect Engn Wuhan 430000 Peoples R China Beijing Jiaotong Univ Sch Elect Engn Beijing 100044 Peoples R China

This letter presents a real-time simulation method for bridge-based power electronic converters based on the R-on/R-off model. By constructing the equivalent system state equation, all multiplications can be performed by shift addition operations in field programmable gate array (FPGA) implementation and avoids using limited multipliers. Then, a 50-kHz dual active bridge converter and a 100-kHz ac-dc-ac converter are simulated on FPGA with 20 ns simulation time step. Accuracy, timing, and resource consumption results verify the effectiveness of this method.

关键词： Switches field programmable gate arrays Mathematical models Vectors Iterative methods Computational modeling Inductors Accuracy Resistors Real-time systems FPGA multipliers power electronic converters real-time simulation r(on)/r(off) model

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Polarization and space multiplexing metasurface for high-efficiency holography

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OPTICS EXPRESS 2025年第4期33卷 8701-8711页

作者： Yang, Silei Zhu, Ziyi Fu, Xiaojian Wang, Peng Liu, Yujie Wu, Junwei Southeast Univ State Key Lab Millimeter Waves Nanjing 210096 Peoples R China Southeast Univ Inst Electromagnet Space Nanjing 210096 Peoples R China

This paper presents a fast and efficient design method for generating multiplanar, dual-linearly polarized holographic patterns in the near-field of a Huygens metasurface when illuminated by incident waves with matching polarizations. The propagation kernel of the traditional Gerchberg-Saxton (GS) algorithm is modified to utilize Green's function (DGF), and a dynamic control factor is introduced to adjust the uniformity of the pattern amplitude. This modification results in an imaging phase distribution, hereby designated as the improved weighted Gerchberg-Saxton algorithm (GS-W). The use of a Huygens metasurface with high transmittance and large phase coverage increases the imaging efficiency of the incident energy, exceeding 32%. As proof of the concept, we fabricate the aforementioned meta-device, which contains 40 x 40 meta-atoms, each with a length and width of 6 mm (0.5 lambda at 25 GHz) and thickness in the longitudinal direction of 1.8 mm. Both the calculation and simulation results show that the quality factors of all reconstructed patterns can exceed more than 42%. (c) 2025 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement

关键词： field programmable gate arrays Imaging techniques Optical data storage Optical properties Phase imaging Real time imaging

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