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IEEE COMPUTER ARCHITECTURE LETTERS 2025年第1期24卷 65-68页

作者： Lin, Yuanmiao Fu, Shansen Li, Xueming Yang, Chaoming Li, Rongfeng Huang, Hongmin Hu, Xianghong Cai, Shuting Xiong, Xiaoming Guangdong Univ Technol Sch Integrated Circuits Guangzhou 510006 Peoples R China Guangdong Univ Technol Sch Automat Guangzhou 510006 Peoples R China Guangdong Polytech Normal Univ Sch Elect & Informat Guangzhou 510665 Peoples R China

Precision-scalable convolutional neural networks (CNNs) offer a promising solution to balance network accuracy and hardware efficiency, facilitating high-performance execution on embedded devices. However, the requirement for small fine-grained multiplication calculations in precision-scalable (PS) networks has resulted in limited exploration on FPGA platforms. It is found that the deployment of PS accelerators encounters the following challenges: LUT-based multiply-accumulates (MACs) fail to make full use of DSP, and DSP-based MACs support limited precision combinations and cannot efficiently utilize DSP. Therefore, this brief proposes a DSP-based precision-scalable MAC with hybrid dataflow that supports most precision combinations and ensures high-efficiency utilization of DSP and LUT resources. Evaluating on mixed 4 b/8b VGG16, compared with 8b baseline, the proposed accelerator achieves 3.97x improvement in performance with only a 0.37% accuracy degradation. Additionally, compared with state-of-the-art accelerators, the proposed accelerator achieves 1.20 x -2.69x improvement in DSP efficiency and 1.63 x -6.34x improvement in LUT efficiency.

关键词： Vectors Quantization (signal) Table lookup field programmable gate arrays Residual neural networks Clocks Accuracy Hardware Convolutional neural networks Training Arbitrary-basis-quantization convolutional neural network DSP hybrid dataflow multiply-accumulate precision-scalable

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A Novel Grating Lobe Suppression Method for Large-Spacing Phased arrays Using Prephased Metalens and Limited Random Phase

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IEEE ANTENNAS AND WIRELESS PROPAGATION LETTERS 2025年第2期24卷 444-448页

作者： Yu, Ze Chen, Chang Chen, Wei-Dong Zhang, Xiang Zhang, Xiao-Lin Univ Sci & Technol China USTC Res Inst 38 China Elect Technol Grp Corp CETC38 Dept Elect Technol & Phased Array Antennas Hefei 230026 Peoples R China Univ Sci & Technol China USTC Dept Elect Sci & Technol Hefei 230026 Peoples R China China Elect Technol Grp Corp Res Inst 38 Dept Electromagnet Theory & Antenna Arrays Hefei 230088 Peoples R China

The electronically steered phased array (ESPA), which is composed of periodic antenna elements, usually uses subarrays with large spacing to lower system complexity and cost. This kind of phased subarray (PSA) has a serious problem with grating lobes while beam scanning. A prephased metalens PSA (PMPSA) that combines prephases and metalens for modifying the transmitting phases is proposed. Further, the limited random phase method (LRPM) for randomizing the feeding phases and cooperating with prephased metalens to suppress the grating lobes is also proposed. In comparison to a PSA with the same parameters, the results demonstrate that the PMPSA can achieve a much better SLL, especially at wide scanning angles. Finally, calculated and simulated results show that a 16 x 16-unit phased array with 2 x 2-unit subarrays can achieve an SLL below -9.9 dB in 2D scanning using the limited random phase method.

关键词： Gratings Antenna arrays Costs field programmable gate arrays Gain Complexity theory Array signal processing Antenna radiation patterns Limited random phase method Three-dimensional displays phased array phased array prephased metalens prephased metalens sidelobe level (SLL) sidelobe level (SLL) subarray subarray subarray Gratings Antenna arrays Costs field programmable gate arrays Gain Complexity theory Array signal processing Antenna radiation patterns Three-dimensional displays

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Real-Time Pulse Processing on the Time-Division Multiplex Readout Electronics of the Transition Edge Sensor for the Line Emission Mapper (LEM)

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IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 2025年第5期35卷

作者： Sakai, K. Adams, J. S. Bandler, S. R. Chervenak, J. A. Cumbee, R. S. Finkbeiner, F. M. Fuhrman, J. D. Hull, S. V. Kelley, R. L. Kilbourne, C. A. Muramatsu, H. Porter, F. S. Smith, S. J. Wakeham, N. A. Wassell, E. J. Univ Maryland Ctr Space Sci & Technol Baltimore MD 21250 USA NASA Goddard Space Flight Ctr GSFC MD Greenbelt MD 20771 USA NASA GSFC Greenbelt MD 20771 USA Sigma Space Corp Hexagon US Fed Lanham MD 20706 USA Univ Maryland College Pk MD 20742 USA Catholic Univ Amer Washington Washington DC USA

We are developing a real-time X-ray pulse processor for the Line Emission Mapper (LEM) mission, a NASA X-ray probe concept for imaging and spectroscopy in the 0.2 to 2 keV range. The main detector is a hybrid Transition Edge Sensor (TES) array with a 33' outer array with "Hydra" multiplexing and a 7' x 7' inner subarray. The similar to 4,000 TES sensors are read out using time-division multiplexing (TDM) technology. We are developing room-temperature digital readout electronics based on laboratory TDM electronics, where all X-ray pulses are processed in real-time to reduce the size of the data transmission. The process includes pulse triggering, grading, extraction, and optimal filtering performed in the FPGA of the TDM column electronics. In this paper we describe the real-time pulse processing firmware for a LEM flight-like prototype electronics and demonstrate count rate capability. We also demonstrate that it provides identical performance compared to conventional offline pulse-processing.

关键词： field programmable gate arrays Real-time systems Filtering NASA Microprogramming Time division multiplexing Sensor arrays X-ray imaging Fabrics Superconducting filters Imaging array line emission mapper space telescope multiplexed readout superconducting device transition-edge sensor X-ray spectroscopy

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Efficient Number Theoretic Transform Architecture for CRYSTALS-Kyber

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2025年第1期72卷 263-267页

作者： Javeed, Khalid Gregg, David Univ Sharjah Dept Comp Engn Sharjah U Arab Emirates Trinity Coll Dublin Lero The Sci Fdn Ireland Res Ctr Software Dublin 2 Ireland

The Number Theoretic Transform (NTT) is a central primitive to compute polynomial multiplication in a finite ring for both post-quantum cryptography (PQC) and fully homomorphic encryption (FHE) schemes. This brief presents a novel, efficient NTT hardware architecture suitable for CRYSTALS-Kyber, one of the NIST PQC standards. It is based on a new novel unified butterfly unit (UBU) developed by combining interleaved multiplication, radix-4, and resource-sharing strategies. This unit computes all butterfly operations for any generic prime modulus value and is re-configurable to any modulus length. In the proposed NTT architecture, multiple UBUs are deployed, demonstrating an area-time tradeoff. UBU and NTT architectures are synthesized and implemented over the Xilinix Artix-7 FPGA platform and results are shown for different performance evaluation metrics. The implementation results show our lightweight and high-speed designs achieve up to 5.6x and 7x improvements in resource consumption and efficiency, respectively. To the authors' knowledge, it is the first generic NTT architecture based on interleaved multiplication approaches.

关键词： Computer architecture Polynomials Cryptography Transforms field programmable gate arrays Standards Fast Fourier transforms Number theoretic transform FPGA interleaved multiplication post-quantum cryptography

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An Area-Energy-Efficient 64-2048 Point FFT With Approximate Plane-Fitting Complex Multipliers

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年

作者： Shi, Weiwei Wu, Jiasheng Yuan, Yida Mo, Zhihong Wu, Chaoyuan He, Jiangwei Shenzhen Univ State Key Lab Radio Frequency Heterogeneous Integr Shenzhen 518060 Peoples R China Shenzhen Univ Dept Microelect CEIE Shenzhen 518060 Peoples R China Shenzhen Univ Dept Microelect CEIE Shenzhen 518060 Peoples R China WingSemi Technol Shanghai Shanghai 201203 Peoples R China

As a key component of fast Fourier transform (FFT), the complex multiplier (CM) includes twiddle factor generation and corresponding multiplication. This brief proposes an tailored approach for approximating CM functionality by employing an adapted piecewise-plane-fitting technique, effectively replacing the conventional look-up-table-based twiddle generation and exact multipliers by shift-and-add calculation. Numerical binary calculation analysis and simulations are conducted to achieve an optimal tradeoff among accuracy, circuit complexity, power, and delay. Based on 45-nm CMOS, logic synthesis results demonstrate significant improvements, with area, power, and delay reductions of 64.18%, 64.98%, and 19.77%, respectively. With optimizations on logic structures, the complete design of the 64-2048 point FFT has efficiently adopted the proposed CM with evident improvement. The proposed FFT outperforms other reconfigurable FFT designs in terms of normalized area reduction over 55.53% and normalized energy improvement over 21.51%. In field-programmable gate array (FPGA) implementation, the proposed FFT has significantly more savings compared with the exact FFT. In practice, the approximate FFT output results' PSNR ranges from 56 to 83 dB with competent accuracy in typical signal processing.

关键词： Fast Fourier transforms Surface fitting Logic Delays Fitting Accuracy Three-dimensional displays Hardware field programmable gate arrays Discrete Fourier transforms Approximate complex multiplier (CM) approximate computing fast Fourier transform (FFT) piecewise-plane-fitting twiddle factor

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Boosting AES Intrinsic Resilience Using Split SubBytes Round Function Against Power Attacks

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IEEE EMBEDDED SYSTEMS LETTERS 2025年第1期17卷 10-13页

作者： Padmakumar, Vishnu Ignatius, Titu Mary Singha, Thockchom Birjit Palathinkal, Roy Paily Ahamed, Shaik Rafi Natl Inst Technol Dept Elect & Commun Engn Silchar 788010 India Indian Inst Technol Guwahati Dept Elect & Elect Engn Gauhati 781039 India

Advanced encryption standard's (AES) vulnerabilities surfaced with power-side channel attacks (PSCAs). Enhancing security by adding extra countermeasure circuitry introduces significant hardware overheads, which are impractical for resource-constrained Internet of Things (IoT) edge devices. This letter proposes an alternative approach, focusing on the AES design itself to enable lightweight countermeasures. Targeting the SubBytes round operation as the vulnerable point, the operation is split across different clock cycles to minimize side-channel information leakage. We investigated 12-clock, 22-clock, 42-clock, 82-clock, and 162-clock AES designs, among which the 82-clock version stands out as the optimal choice, providing efficient hardware resource utilization. Evaluation using hardware security metrics, such as measurements to disclose (MTD) and signal to noise ratio (SNR), confirms its superior security and reduced information leakage compared to other designs. Power traces for attacks are generated on both application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) platforms, maintaining a consistent 16 MHz design frequency with traces sampled at 1 GSa/s.

关键词： Clocks Security Signal to noise ratio field programmable gate arrays Throughput Resilience Information leakage Advanced encryption standard (AES) application specific integrated circuit (ASIC) correlational power analysis (CPA) countermeasure intrinsic resilience field programmable gate array (FPGA) Internet of Things (IoT) measurements to disclose (MTD) power side channel attack (PSCA) signal to noise ratio (SNR) SubBytes

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20 Gbps real-time source-independent quantum random number generator based on a silicon photonic chip

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OPTICS LETTERS 2025年第4期50卷 1216-1219页

作者： Bian, Yiming Yang, Jie Jiang, Haoyuan Huang, Wei Su, Qi Yu, Song Zhang, Lei Zhang, Yichen Xu, Bingjie Beijing Univ Posts & Telecommun State Key Lab Informat Photon & Opt Commun Beijing 100876 Peoples R China Beijing Univ Posts & Telecommun Sch Elect Engn Beijing 100876 Peoples R China Inst Southwestern Commun Natl Key Lab Secur Commun Chengdu 610041 Peoples R China State Key Lab Cryptol Beijing 100878 Peoples R China Beijing Univ Posts & Telecommun Sch Integrated Circuits Beijing 100876 Peoples R China

Quantum random number generator (QRNG) allows for the production of truly unpredictable random numbers, thanks to the inherent randomness available in quantum mechanics. However, its practical implementation is facing several challenges, including the practical security loophole, high-speed real-time randomness extraction, and large-scale production. In this work, we address these challenges with a chip-based, source-independent quantum random number generator achieving 20 Gbps real-time generation rate. It ensures the practical security through a source-independent security framework and the modeling of measurement devices. A bandwidth exceeding 2 GHz and a clearance reaching 10 dB is achieved by a silicon- based homodyne detector. Analog-to-digital conversion and randomness extraction are integrated on a single data collection and processing board, where the optimized parallel randomness extraction algorithm on a field programmable gate array achieves a throughput up to 28 Gbps. The results promise a high-speed and practically secure quantum random number generation on a chip, paving the way for its large-scale deployments and widespread applications. (c) 2025 Optica Publishing Group. All rights, including for text and data mining (TDM), Artificial Intelligence (AI) training, and similar technologies, are reserved.

关键词： field programmable gate arrays Optical circuits Optical components Quantum key distribution Random number generation Variable optical attenuators

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An Optimized Structure for Data Alignment Logic in Parallel CRC Computing Circuits

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IEEE EMBEDDED SYSTEMS LETTERS 2025年第2期17卷 91-94页

作者： Nie, Yuchen Zhong, Sheng Kuang, Nailiang Ji, Yuting Luo, Hangzai Lishan Microelect Co R&D Innovat Ctr Xian 710065 Peoples R China Northwest Univ Sch Informat Sci & Technol Xian 710127 Peoples R China

In bit-level parallel cyclic redundancy check (CRC) computing circuits, it is possible that the input data length may not be evenly divisible by the parallel bit width. Consequently, the incorporation of alignment logic into the circuit is necessary to discard the invalid data. A comprehensive analysis of 256-bits parallel circuits reveals that the data alignment structure introduces an additional delay of 46% to 53.8%. We proposed a prealignment structure as a means of optimizing the data alignment logic. This structure separates the data alignment logic from the loopback structure generated by the parallel computing logic, allowing for pipelining between the data alignment logic and the parallel computing logic. On-board tests on field-programmable gate arrays (FPGAs) show that circuits with a prealignment structure have an increase in maximum clock frequency of about 95% to 175% and a reduction in average energy consumption for computation of about 40.6% to 55% compared to circuits using a shift-alignment structure.

关键词： Circuits Logic Parallel processing field programmable gate arrays Phase change materials Polynomials Registers Delays Pipelines Periodic structures Cyclic redundancy check (CRC) field-programmable gate array (FPGA) hardware acceleration parallel computation

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RosebudVirt: A High-Performance and Partially Reconfigurable FPGA Virtualization Framework for Multitenant Networks

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第1期33卷 298-302页

作者： Chang, Yiwei Guo, Zhichuan Chinese Acad Sci Inst Acoust Natl Network New Media Engn Res Ctr Beijing 100190 Peoples R China Univ Chinese Acad Sci Sch Elect Elect & Commun Engn Beijing 100049 Peoples R China

field-programmable gate arrays (FPGAs) are key accelerators in cloud data centers due to their parallelism and programmability. However, challenges such as low hardware utilization and high virtualization overhead persist. This brief presents RosebudVirt, a high-performance and partially reconfigurable FPGA virtualization framework tailored for multitenant networks. It enhances the original Rosebud by introducing single-root I/O virtualization (SR-IOV) support, partitioning the PCIe-attached FPGA device into multiple physical functions (PFs) and virtual functions (VFs) accessible to the linux kernel via PF and VF drivers. This facilitates direct mapping among tenants, VFs, and reconfigurable packet-processing units (RPUs) within the FPGA. RosebudVirt achieves near-native throughput with < 1% area overhead and increases hardware utilization by up to 7.6 times by additional VF drivers and network interfaces. What is more, RosebudVirt is compatible with Kubernetes and Docker

关键词： field programmable gate arrays Virtualization Hardware Resource management Cloud computing Throughput Software Cloud data centers field-programmable gate array (FPGA) virtualization multitenant networks partial reconfiguration (PR) single-root I/O virtualization (SR-IOV)

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ISQ: Intermediate-Value Slip Quantization for Accumulator-Aware Training

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IEEE SIGNAL PROCESSING LETTERS 2025年 32卷 976-980页

作者： Zhang, Chi Yang, Xu Yu, Shuangming Dou, Runjiang Liu, Liyuan Chinese Acad Sci Inst Semicond State Key Lab Superlatt & Microstruct Beijing 100083 Peoples R China Univ Chinese Acad Sci Ctr Mat Sci & Optoelect Engn Beijing 100049 Peoples R China

The development of lightweight technologies has made deploying convolutional neural networks on edge devices popular. However, the overflow caused by low-bit accumulators significantly degrades the accuracy of the model. Therefore, there is a challenge in balancing accuracy and low-bit accumulators. In this letter, we propose a novel method applying for training low-bit quantized neural network named Intermediate-Value Slip Quantization (ISQ). ISQ is used to constrain weights to decrease the risk of accumulator's overflow. Besides, we also set a criterion for ISQ to be aware of the bit width of the accumulator. In addition, we propose a method to integrate bias and Batch Normalization (BN) into the ISQ. This allows the computations to be shifted from the floating-point domain to the fixed-point. The experiment results demonstrate that ISQ effectively suppresses the overflow. The model accuracy under the 16-bit accumulator can be restored to 73.16% from 13.7% on CIFAR-100 with the same quantization configuration. Through our method, the design space of the hardware can be explored and the target accuracy can be achieved with the lowest hardware resources.

关键词： Quantization (signal) Training Accuracy Hardware Neural networks Optimization Backpropagation field programmable gate arrays Data mining Convolution Convolutional neural network quantization quantization-aware training overflow accumulator

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