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MorphBungee-Lite: An Edge Neuromorphic Architecture With Balanced Cross-Core Workloads Based on Layer-Wise Event-Batch Learning/Inference

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2025年第1期72卷 293-297页

作者： Zhong, Zhengqing Wang, Haibing Chen, Mingju Lin, Yingcheng Tian, Min Wang, Tengxiao Liu, Liyuan Shi, Cong Chongqing Univ Sch Microelect & Commun Engn Chongqing 400044 Peoples R China Sichuan Univ Sci & Engn Artificial Intelligence Key Lab Sichuan Prov Yibin 643000 Sichuan Peoples R China Chinese Acad Sci Inst Semicond State Key Lab Superlatt & Microstruct Beijing 100083 Peoples R China

Neuromorphic processors are promising candidates for energy-constrained intelligent systems, as they emulate cortical computations via spatiotemporally sparse binary spikes. However, achieving high-accuracy, high-throughput and cost-efficient neuromorphic processing remains challenging. To fully utilize hardware resources for performance improvement, we propose a multi-core neuromorphic architecture characteristic of a uniform neuron-core mapping scheme and a layer-wise event-batch-based parallel processing paradigm. These techniques ensure highly balanced cross-core workloads regardless of actual mapped neural network topologies as well as unpredictable input and internally generated spike counts varying from sample to sample. An FPGA prototype of our neuromorphic processor was implemented. It exhibited comparably high on-chip learning accuracies on various visual and non-visual benchmarks, high learning/inference frame rates (low processing latencies), with a moderate amount of logic and memory resource consumptions.

关键词： Neurons Computer architecture Timing Neuromorphics Program processors System-on-chip Hardware field programmable gate arrays Multicore processing Synapses Neuromorphic processor spiking neural network workload balance event-driven on-chip learning

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A High-Speed, High-Resolution Transition Edge Sensor Spectrometer for Soft X-Rays at the Advanced Photon Source

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IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 2025年第5期35卷

作者： Quaranta, Orlando Jensen, Don Morgan, Kelsey Weber, Joel C. Mcchesney, Jessica L. Zheng, Hao Guruswamy, Tejas Baldwin, Jonathan Mates, Ben Ortiz, Nathan Gard, Johnathon Bennet, Doug Schmidt, Dan Gades, Lisa Miceli, Antonino Argonne Natl Lab Lemont IL 60439 USA NIST Boulder CO 80305 USA

This project explores the design and development of a transition edge sensor (TES) spectrometer for resonant soft X-ray scattering (RSXS) measurements developed in collaboration between Argonne National Laboratory (ANL) and the National Institute of Standards and Technology (NIST). Soft X-ray scattering is a powerful technique for studying the electronic and magnetic properties of materials on a microscopic level. However, the lack of high-performance soft X-ray spectrometers has limited the potential of this technique. TES spectrometers have the potential to overcome these limitations due to their high energy resolution, high efficiency, and broad energy range. This project aims to optimize the design of a TES spectrometer for RSXS measurements and more generally soft X-ray spectroscopy at the Advanced Photon Source (APS) 29-ID, leading to improved understanding of advanced materials. We will present a detailed description of the instrument design and implementation. The spectrometer consists of a large array of approximately 250 high-speed and high-resolution pixels. The pixels have saturation energies of approximately 1 keV, sub-ms pulse duration and energy resolution of approximately 1 eV. The array is read out using microwave multiplexing chips with MHz bandwidth per channel, enabling efficient data throughput. To facilitate measurement of samples in situ under ultra-high vacuum conditions at the beamline, the spectrometer is integrated with an approximately 1 m long snout.

关键词： Energy resolution Photonics Scattering Detectors Iron field programmable gate arrays Cryogenics Thermometers Spectroscopy Multiplexing Beamline cryogenic detector resonant soft X-ray scattering spectroscopy superconductivity transition edge sensor

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Optimized Quantum Random Number Generator for Single Photon LiDAR Interference Suppression

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IEEE PHOTONICS TECHNOLOGY LETTERS 2025年第9期37卷 512-515页

作者： Wang, Yicheng Yang, Xing Pan, Hao Guo, Yunhui Zuo, Lei Chen, Yuwei Natl Univ Def Technol State Key Lab Pulsed Power Laser Technol Hefei 230037 Peoples R China Adv Laser Technol Lab Anhui Prov Hefei 230037 Anhui Peoples R China

Single photon light detection and ranging (LiDAR) sensors have been facing serious issues of light interference and optical attacks. Random modulation of transmitted laser can effectively suppress interference and counter attacks. Quantum Random Number Generator (QRNG) based on single photon detection of LiDAR has become an important solution for generating true random numbers. The performance of traditional QRNG based on the parity of counting values of photon events (CntOE-QRNG) is poor under low photon event rate. This letter proposes a novel QRNG method based on parity discrimination of photon event interval (IntOE-QRNG). It is proved that the IntOE-QRNG has more advantages under the condition of low photon event rate. Based on the analysis of the advantages and disadvantages of these two methods, this letter finally proposes an optimized QRNG that combines these two methods to adapt to different photon event rate conditions.

关键词： Photonics Laser radar Single-photon avalanche diodes Detectors Binary sequences Histograms Generators field programmable gate arrays Entropy Training Quantum random number generator LiDAR SPAD anti-interference

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A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第2期33卷 588-592页

作者： Wang, Zihang Yang, Yushu Wang, Jianfei Hou, Jia Su, Yang Yang, Chen Xi An Jiao Tong Univ Sch Microelect Xian 710049 Shaanxi Peoples R China Engn Univ Peoples Armed Police Sch Cryptog Engn Xian 710086 Peoples R China

Polynomial multiplication is a significant bottleneck in mainstream postquantum cryptography (PQC) schemes. To speed it up, number theoretic transform (NTT) is widely used, which decreases the time complexity from O(n(2)) to O[nlog(2)(n)]. However, it is challenging to ensure optimal hardware efficiency in conjunction with scalability. This brief proposes a novel pipelined NTT/inverse-NTT (INTT) architecture on field-programmable gate array (FPGA). A group-based pairwise memory access (GPMA) scheme is proposed, and a scratchpad and reordering unit (SRU) is designed to form an efficient dataflow that simplifies control units and achieves almost n/2 processing cycles on average for n -point NTT. Moreover, our architecture can support varying parameters. Compared to the state-of-the-art works, our architecture achieves up to 4.8 x latency improvements and up to 4.3 x improvements on area time product (ATP).

关键词： Random access memory Computer architecture Hardware field programmable gate arrays Memory management Delays Scalability Registers Polynomials Pipelines field-programmable gate array (FPGA) number theoretic transform (NTT) pipeline postquantum cryptography (PQC) reordering

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A Co-Optimization of Software and Hardware for PCIe-Based Small Packet DMA Transfer

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IEEE EMBEDDED SYSTEMS LETTERS 2025年第1期17卷 6-9页

作者： Gu, Xiaotian Shao, Lisong Bai, Ningfeng Zhang, Guosheng Zhang, Xinyi Southeast Univ Sch Elect Sci & Engn Nanjing 210096 Peoples R China Phytium Technol Co Ltd Tianjin Peoples R China Southeast Univ Sch Software Nanjing 215000 Peoples R China Southeast Univ Sch Integrated Circuit Nanjing 215000 Peoples R China

To meet the development needs of high-performance networks, the efficiency of PCIe DMA with small packet transmissions emerges as a critical performance bottleneck. For the purpose improving DMA transfer for small packets over PCIe, we focus on the symbiotic co-optimization of software and hardware. By enhancing the software driver with descriptor prefetching, harnessing the outstanding capability at the hardware level, and using multicore for parallel processing, the system's bandwidth has been significantly improved, particularly for the small packets transfers. Postoptimization, we test the DMA read and write bandwidth and utilization rate performance on VC709 FPGA. In a randomized test scenario, the average DMA read bandwidth is approximately 5.3 GB/s, representing a 123% improvement compared to the unoptimized system bandwidth. The average DMA write bandwidth is approximately 5.8 GB/s, representing a 136% improvement compared to the unoptimized system bandwidth. Additionally, in the randomized test scenario, the average read and write latencies improved by 15.12% and 23.96%, respectively.

关键词： Bandwidth Hardware Prefetching Data transfer field programmable gate arrays Clocks Task analysis Descriptors prefetch DMA FPGA multicore parallelism outstanding capability PCIe

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Highly Parallel CNN Accelerator for RepVGG-Like Network Training on FPGAs

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2025年第2期44卷 554-558页

作者： Guo, Chuliang Lou, Binglei Boland, David Leong, Philip H. W. Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou 310027 Peoples R China Harbin Inst Technol Sch Elect & Informat Engn Harbin 150001 Peoples R China Univ Sydney Sch Elect & Comp Engn Sydney NSW 2006 Australia

In this article, we propose a generic FPGA-based training accelerator tailored for RepVGG-like networks, which strikes a balance between maximizing training-time accuracy and minimizing inference-time latency. The proposed accelerator leverages fine-grain channel-level parallelism within computational units specially designed for multiple branches of the basic building block within the RepVGG-like network. Specifically, we employ a Conv block for forward Conv and backward deConv, along with a dilated Conv block, including a weight kernel partition scheme for efficient weight gradient calculation. Furthermore, we aggressively exploit a 2-stage coarse-grain task-level parallelism for low-latency CNN training: 1) parallelism among multiple branches of the basic building block of RepVGG and 2) parallelism between error back-propagation and weight gradient calculation in the backward path. Through experiments on the CIFAR-10 dataset using 16-bit fixed-point arithmetic, we demonstrate state-of-the-art batch 1 throughput of 150 GOPs for training and 183 GOPs for inference.

关键词： Training Parallel processing Task analysis Throughput field programmable gate arrays Accuracy Convolutional neural networks Convolutional neural network (CNN) training FPGA HLS RepVGG

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A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2025年第1期72卷 243-247页

作者： Wang, Jianfei Yang, Chen Hou, Jia Zhang, Fahong Meng, Yishuo Su, Yang Liu, Leibo Xi An Jiao Tong Univ Sch Microelect Xian 710049 Peoples R China Engn Univ Peoples Armed Police Sch Cryptog Engn Xian 710086 Peoples R China Tsinghua Univ Sch Integrated Circuits Beijing 100084 Peoples R China

To accelerate RNS-CKKS, little attention is paid to the acceleration of the operations on the edge-client. However, the devices used by the edge-client are often low-end and have limited resources and computing power, so the performance of RNS-CKKS encoding, decoding, encryption and decryption also needs to be improved. Consequently, we propose a compact and efficient hardware accelerator architecture named CAEA for these operations. In order to improve the compactness of CAEA, a reconfigurable butterfly unit is proposed, which considers both complex number arithmetic and integer modular arithmetic, so that FFT/IFFT and NTT/INTT can be executed on unified hardware processing elements without additional resource and waste. Moreover, in order to improve the computational efficiency, we also improved the dataflow of encoding, decoding, encryption, and decryption on CAEA to reduce the number of required operations and latency. CAEA is synthesized based on SMIC 40nm technology, and is also implemented on Xilinx Kintex-7 and Zynq UltraScale+ FPGA. Compared with the prior related works, in terms of performance, CAEA can achieve 2.01x speedup for encoding and decoding, 1.13x similar to 87.86x speedup for encryption, and 3.03x similar to 69.64x speedup for decryption. Compared with the state-of-the-art work, CAEA can achieve 1.06x similar to 4.96x improvement in terms of area efficiency.

关键词： Random access memory Encoding Encryption Polynomials Decoding Cryptography field programmable gate arrays CKKS FPGA accelerator encryption and decryption encoding and decoding

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Coherently averaged optical frequency comb spectroscopy with a single electro-optic modulator

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OPTICS LETTERS 2025年第2期50卷 654-657页

作者： Bresler, S. M. Reed, Z. D. Han, K. Hodges, J. T. Aksyuk, V. A. Lebrun, T. W. Long, D. A. Univ Maryland College Pk MD 20742 USA Natl Inst Stand & Technol Gaithersburg MD 20899 USA Theiss Res La Jolla CA 92037 USA

We present a new, to the best of our knowledge, approach for self-heterodyne optical frequency comb (OFC) spectroscopy in which a single Mach-Zehnder modulator is utilized to generate both an optical frequency comb and a frequencyshifted local oscillator. This method allows for coherent, time-domain averaging to be performed without the need for feedback mechanisms or software corrections. As an initial demonstration, we have measured acetylene rovibrational transition frequencies with coherently averaged comb spectra. Spectra averaged for less than 10 s yielded standard fit uncertainties for transition frequencies of less than 150 kHz, with deviations from literature values under 1.1 MHz, limited by pressure uncertainty. This approach has important implications for high-resolution spectroscopy, trace gas detection, and on-chip integration of electro-optic frequency similar technologies, are reserved.

关键词： Absorption spectroscopy Diode lasers field programmable gate arrays Fourier transforms Frequency combs Molecular spectroscopy

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ASIC Implementation of ASCON Lightweight Cryptography for IoT Applications

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2025年第1期72卷 278-282页

作者： Nguyen, Khai-Duy Dang, Tuan-Kiet Kieu-Do-Nguyen, Binh Le, Duc-Hung Pham, Cong-Kha Hoang, Trong-Thuc Univ Electrocommun Grad Sch Informat Syst Tokyo 1828585 Japan Vietnam Natl Univ Ho Chi Minh City Univ Sci Fac Elect & Telecommun Ho Chi Minh City 700000 Vietnam

The number of IoT devices has grown significantly in recent years, and edge computing in IoT is considered a new and growing trend in the technology industry. While cryptography is widely used to enhance the security of IoT devices, it also carries limitations such as resource constraints or latency. Therefore, lightweight cryptography (LWC) balances commensurate resource usage and maintaining security while minimizing system costs. The ASCON stands out among the LWC algorithms as a potential target for implementation and cryptoanalysis. It provides authenticated encryption with associated data (AEAD) and hashing functionalities in many variants, aiming for various applications. In this brief, we present an implementation of Ascon cryptography as a peripheral of a RISC-V System-on-a-Chip (SoC). The ASCON crypto core occupies 1,424 LUTs in FPGA and 17.4 kGE in 180nm CMOS technology while achieving 417 Gbits/J energy efficiency at a supply voltage of 1.0V and frequency of 2 MHz.

关键词： Ciphers Internet of Things field programmable gate arrays Hardware Encryption Cryptography Wireless sensor networks Table lookup Throughput Hash functions RISC-V lightweight ASCON ASIC

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FANNS: An FPGA-Based Approximate Nearest-Neighbor Search Accelerator

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第4期33卷 1197-1201页

作者： Yuan, Wei Jin, Xi Univ Sci & Technol China Dept Phys Hefei 230026 Peoples R China

Approximate nearest-neighbor search (ANNS) based on high-dimensional vectors has been extensively utilized in data science and neural networks. However, deploying ANNS in production systems requires minimal redundant computation, high recall rates, and low on-chip memory usage, which existing hardware accelerators fail to offer. We propose FANNS, a solution for ANNS based on high-dimensional vectors that can eliminate redundant computations and reuse on-chip data. Extensive evaluations show that FANNS achieves an average of 184.1x , 33.0x , 2.9x , and 2.5x better energy efficiency than CPUs, GPUs, and two state-of-the-art ANNS architectures, i.e., DF-GAS and Vstore, respectively.

关键词： Vectors Computer architecture Sorting Energy efficiency Nearest neighbor methods Graphics processing units Databases Data transfer Bandwidth field programmable gate arrays Approximate nearest-neighbor search (ANNS) field-programmable gate array (FPGA) hardware accelerator hardware architecture

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