检索结果-内蒙古大学图书馆

An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第5期33卷 1432-1436页

作者： Choi, Won Joon Lee, Myungguk Choi, Junung Cho, Jaeik Kim, Gain Kim, Byungsub Pohang Univ Sci & Technol Dept Elect Engn Pohang Si 37673 South Korea Samsung Elect Hwaseong Si 18448 South Korea Daegu Gyeongbuk Inst Sci & Technol Dept Elect Engn & Comp Sci Daegu 42988 South Korea Pohang Univ Sci & Technol Dept Elect Engn Dept Convergence IT Engn Dept Semicond Engn Pohang Si 37673 South Korea Pohang Univ Sci & Technol Grad Sch Semicond Technol Pohang Si 37673 South Korea Yonsei Univ Inst Convergence Res & Educ Adv Technol Seoul 03722 South Korea

Determining a channel's characteristics is a fundamental step for designing a high-speed link system. By identifying the properties of the channel, designers can gain insights into how to transmit a signal with low distortion and optimize a transceiver's architecture. As the channel's characteristics can be identified by analyzing its single-bit pulse response (PR), obtaining an accurate PR plot is critical for reliable channel characterization. Therefore, it is preferred to measure the PR in situ to minimize the parasitic effects. In this work, we introduce a novel approach for measuring PR in situ, designed to quickly and accurately generate undistorted plot results. To prove the efficacy of the proposed method, we designed an on-chip sampling scope circuit and fabricated a test chip in 28-nm CMOS technology. While being able to measure a distortion-free PR, the proposed method demonstrates a more than 10(5) times faster pulse acquisition rate than prior arts.

关键词： System-on-chip Semiconductor device measurement Distortion measurement Synchronization Clocks field programmable gate arrays Pulse measurements Shift registers Pulse generation Data processing Built-in self-test (BIST) channel characterization high-speed link mixed-signal circuit pulse response (PR)

来源：评论

学校读者我要写书评

暂无评论

PIMSR: An Energy-Efficient Processing-in-Memory Accelerator for 60 FPS 4K Super-Resolution

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2025年第4期72卷 623-627页

作者： Guan, Juntao Guo, Qinghui Li, Huanan Lai, Rui Ding, Ruixue Qian, Libo Zhu, Zhangming Xidian Univ Hangzhou Inst Technol Key Lab Analog Integrated Circuits & Syst Minist Educ Hangzhou 311200 Peoples R China Xidian Univ Sch Integrated Circuits Key Lab Analog Integrated Circuits & Syst Minist Educ Xian 710071 Peoples R China Xidian Univ Chongqing Innovat Res Inst Integrated Circuits Chongqing 400031 Peoples R China

Due to the huge computational load, CNN-based super-resolution solutions are hard to be deployed on resource-constrained edge devices. In this brief, we proposed a Processing-in-Memory based SR accelerator (PIMSR) that leverages direct simple memory access operations to supersede intensive multiply-add in convolution operators, thus fundamentally improving the energy efficiency. To address the storage explosion problem, we presented an index reparameterized strategy for shrinking the memory requirement of LUT-based PIMSR framework by 19.58x . Furthermore, an address remapping design is putted forward to solve the access conflict in overlap configuration, which greatly boosts the efficiency of memory access. The prototype validation on low-end XC7A200T FPGA indicates that our design yields a new record of energy efficiency up to 671.61 Mpixels/J, over 5.36x higher than existing deep learning based image processors, with extremely low hardware costs.

关键词： Table lookup Indexes field programmable gate arrays Energy efficiency Convolution Superresolution Registers Computational modeling Kernel Interpolation Convolutional neural network (CNN) field programmable gate array (FPGA) image super-resolution edge computing

来源：评论

学校读者我要写书评

暂无评论

Continuous Diagnostics for Powered Superconducting Circuits

引用

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 2025年第5期35卷

作者： Podzorny, T. Bednarek, M. J. Christensen, M. B. B. Calcoen, D. Denz, R. Ludwin, J. Steckert, J. Uythoven, J. CERN CH-1211 Geneva Switzerland European Org Nucl Res CH-1211 Geneva Switzerland Aalborg Univ DK-9220 Aalborg Denmark Polish Acad Sci Inst Nucl Phys PL-31342 Krakow Poland

Monitoring the electrical properties of superconducting devices in their unpowered state has proven essential for commissioning and fault diagnosis during LHC machine operation. Furthermore, continuous diagnostics of powered superconducting circuits in an operational or test environment has the potential to further improve the understanding of existing and possibly ageing facilities. In this paper, we demonstrate that the injection of a very low power and arbitrary stimulus allows continuous monitoring of the electrical properties of a superconducting magnet through all phases of powering. We compare the performance of this novel measurement system in three different states of a superconducting magnet: unpowered, during current ramping, and at a steady operating current. In addition, we compare the new method with the currently used diagnostics of the LHC superconducting magnets for the unpowered devices. Our results indicate that the presented method provides comparable results to the reference system, while allowing continuous probing of the energized superconducting device over extended periods of time.

关键词： Impedance Superconducting magnets Impedance measurement Current measurement Circuits Monitoring field programmable gate arrays Clocks Magnetic field measurement Frequency measurement Accelerator magnets impedance measurement and testing

来源：评论

学校读者我要写书评

暂无评论

Hybrid Number Theoretic Transform Architecture for Homomorphic Encryption

引用

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年

作者： Truong, Quang Dang Duong-Ngoc, Phap Lee, Hanho Inha Univ Dept Elect & Comp Engn Incheon 22212 South Korea Univ Danang Vietnam Korea Univ Informat & Commun Technol Danang 50000 Vietnam

Fully homomorphic encryption (FHE) is an innovative cryptographic technology that has the potential to protect the privacy and confidentiality of data in the untrusted environments, such as public clouds or external parties. However, due to the inclusion of time-consuming polynomial arithmetic, FHE remains a challenge for computationally heavy applications. The number theoretic transform (NTT) is widely used in HE to reduce the complexity of polynomial multiplication. Therefore, implementing NTT in hardware for FHE has been explored in prior studies. However, due to the high hardware resource requirements, especially with a large number of moduli, hardware architecture supporting both NTT and its inverse transform (INTT) is still missing. This brief presents a hardware architecture for $2<^>{17}$ NTT and INTT suitable for high-circuit depth CKKS-based HE schemes, satisfying both criteria of high speed and affordability for various FPGA platforms. The implementation results highlight that this design is area-efficient compared to the most related work and hardware-friendly for practical HE-based applications on FPGA devices.

关键词： Computer architecture Hardware Polynomials Transforms field programmable gate arrays Very large scale integration Information and communication technology Homomorphic encryption Frequency division multiplexing Arithmetic hybrid architecture lattice-based cryptography memory access pattern number theoretic transform (NTT) residue number system (RNS)

来源：评论

学校读者我要写书评

暂无评论

A programmable High-Precision Real-Time Optical Beamforming Network Based on Galois field

引用

IEEE PHOTONICS TECHNOLOGY LETTERS 2025年第9期37卷 520-523页

作者： Zhou, Jiehua Ding, Yan Yin, Zhuo Chen, Xiaoyang Ma, Xiao Xiao, Long Lei, Cheng Wuhan Univ Inst Technol Sci Wuhan 430072 Peoples R China China Ship Dev & Design Ctr Natl Key Lab Electromagnet Effect & Secur Marine E Wuhan 430064 Peoples R China

We propose a high-precision beam steering real-time control system that leverages optical true time delay (OTTD) based on serial $2\times 2$ optical switch differential delay pairs. The pre-designed OTTD system utilizes a three-layer structure including a host computer, main control module, and delay module, containing a set of coding rules for mapping delay to switch as well as reducing programming redundancy and a set of communication modules for on-chip communication and real-time control. To address the challenge of ultra-short fiber lengths, we introduce a method based on Galois field principles, exploiting phase periodicity. This approach allows us to determine fiber lengths without fabricating excessively short fibers, ensuring effective phase traversal and thus improving the system's flexibility. The experimental results show that the system can switch states in real-time within 0.24 ms, with an angular deflection range of 1 degrees between -60 degrees and 60 degrees in simulations, showing the potential of our method for flexible beamforming design.

关键词： Optical switches Optical fibers Delays Real-time systems Optical variables control field programmable gate arrays Phased arrays Optical device fabrication Optical fiber networks Laser beams 6G microwave photonics optical beamforming true time-delay real-time

来源：评论

学校读者我要写书评

暂无评论

Simplified Oblique Decision Tree Accelerator

引用

IEEE EMBEDDED SYSTEMS LETTERS 2025年第2期17卷 79-82页

作者： Choudhury, Rituparna Rafi Ahamed, Shaik Guha, Prithwijit SRM Univ AP Dept Elect & Commun Engn Amravati 522502 Andhra Pradesh India Indian Inst Technol Dept Elect & Elect Engn Gauhati 781039 India

In recent years, hardware platforms like field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs) are highly preferred for implementing machine learning algorithms in low-power or high-speed applications. This letter proposes a simplified oblique node decision tree algorithm. The classification is implemented on FPGA and ASIC for activity recognition and Parkinson's tremor detection. A mode number is used to choose the application mode. To provide better classification performance, efficient multiplier-less architectures have been used for power efficiency. This design operates at a maximum frequency of 167 MHz and has the lowest latency as compared to the existing hardware. It is also found to have very low resource consumption as compared to other existing high-speed architectures.

关键词： Vectors Hardware field programmable gate arrays Training Registers Computer architecture Classification algorithms arrays Switches Machine learning algorithms Application specific integrated circuit (ASIC) classification decision tree (DT) field programmable gate array (FPGA) machine learning (ML)

来源：评论

学校读者我要写书评

暂无评论

Dora: A Low-Latency Partial Reconfiguration Controller for Reconfigurable System

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2025年第1期72卷 268-272页

作者： Zhang, Guosheng Shao, Lisong Wu, Hanqian Gu, Xiaotian Zhang, Xinyi Southeast Univ Coll Software Engn Nanjing 210096 Peoples R China Southeast Univ Sch Elect Sci & Engn Nanjing 210096 Peoples R China Southeast Univ Sch Integrated Circuit Nanjing 210096 Peoples R China Phytium Technol High Performance R&D Dept Changsha 410028 Peoples R China

Dora, a low-latency field-programmable gate array (FPGA) partial reconfiguration (PR) controller, is proposed in this brief to address the latency challenge encountered by traditional solutions in highly real-time reconfigurable systems. First, based on the constructed refined cost model, key factors for minimizing latency in Host-to-FPGA reconfiguration process are analyzed. Subsequently, utilizing the established producer-consumer model, the reconfiguration mechanism (scatter gather-streaming-based hybrid transmission) and training method (adaptive overclocking of the Internal Configuration Access Port, ICAP) in Dora aim to enhance production of configuration bitstream while achieving efficient consumption. Ultimately, experiments demonstrate that Dora outperforms existing solutions in pivotal aspects: (i) It slashes FPGA resource utilization by over 60% while attaining a reconfiguration rate close to the theoretical peak of 99.6%, (ii) it reduces latency to just 11.1 ms, representing only 2.6% of the latency of the standard Xilinx solution, (iii) additionally, its open-source nature fosters broader adoption and utilization among the research community.

关键词： field programmable gate arrays Clocks Timing Costs Training Hardware Low latency communication FPGA reconfigurable system partial reconfiguration ICAP reconfiguration latency

来源：评论

学校读者我要写书评

暂无评论

High-Performance Instruction-Set Hardware Accelerator for Ring-Binary-LWE-Based Lightweight PQC

引用

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第5期33卷 1417-1421页

作者： He, Pengzhou Bao, Tianyou Xie, Jiafeng Villanova Univ Dept Elect & Comp Engn Villanova PA 19085 USA

Recent advances in hardware acceleration for postquantum cryptography (PQC) have also switched to lightweight PQC. Apart from the traditional hardware design methodology, instruction-set accelerator for PQC represents a new design trend but has not been explored on lightweight PQC. To fill the research gap, in this work, we present a novel instruction-set acceleration of a ring-binary-learning-with-errors (RBLWEs)-based PQC (RBLWE-based encryption (ENC), a promising lightweight scheme) on field-programmable gate array (FPGA). Key efforts include: 1) derivation of an algorithm for the major operation of RBLWE-ENC to facilitate instruction-set acceleration;2) development of the instruction-set accelerator, including the polynomial multiplication core designed from the derived algorithm;and 3) evaluation to showcase the efficiency of the proposed design. The proposed accelerator is efficient and complete in cryptographic operations, which can help further lightweight PQC development.

关键词： Polynomials Registers Adders field programmable gate arrays Encryption Very large scale integration Arithmetic Market research Loading Hardware acceleration field-programmable gate array (FPGA) hardware design instruction-set accelerator lightweight postquantum cryptography (PQC) ring-binary-learning-with-error-based encryption (RBLWE-ENC)

来源：评论

学校读者我要写书评

暂无评论

Low-complexity 24-h 29-km inter-island real-time FSO communication under strong turbulences

引用

OPTICS LETTERS 2025年第2期50卷 546-549页

作者： Guo, Meng Li, Bohan Wang, Yifan Lu, Zehui Xu, Dongye Xiang, Qirong Xiong, Lingyi Li, Changjin Duan, Shaoxiang Yao, Yuan Zhang, Hao Lin, Wei Liu, Haifneg Liu, Bo Nankai Univ Inst Modern Opt Coll Elect Informat & Opt Engn Tianjin 300350 Peoples R China Nankai Univ Tianjin Key Lab Optoelect Sensor & Sensing Network Tianjin 300350 Peoples R China Nankai Univ Tianjin Key Lab Microscale Opt Informat Sci & Tech Tianjin 300350 Peoples R China Southern Marine Sci & Engn Guangdong Lab Zhuhai 519000 Peoples R China Tianjin Univ Sci & Technol Coll Elect Informat & Automat Tianjin 300350 Peoples R China

Free space optical communication (FSOC) technology can be used for data transmission between ocean islands as backup wireless communication networks to cope with traffic surges and emergencies. In this paper, we experimentally demonstrate the results of a 24-h real-time single-wavelength 2.5-Gbps FSOC between two islands 29 km apart at a low altitude with low complexity. On-off keying signals generated by field-programmable gate array (FPGA) board and commercial low-cost SFP + optical modules are employed as transceiver signals. At the receiving end, a 250-mm large-aperture Cassegrain telescope and 105-mu m multi- mode fibers (MMFs) are utilized to reduce the scintillation index from 1.5 to 0.48 and from 0.55 to 0.25 under strong and weak fluctuations, respectively. The averaged receiving optical power, scintillation index, and average bit rate error (BER) are experimentally observed over a 24-hour period with an averaged transmitting power of 36 dBm. The experimental results show that the proportions reach 93.737c and 99.97c for BER below 1 x 10-6 and 1 x 10-3, respectively. (c) 2025 Optica Publishing Group. All rights, including for text and data mining (TDM), Artificial Intelligence (AI) training, and similar technologies, are reserved.

关键词： field programmable gate arrays Multimode fibers Optical signals Optical transceivers Scintillation index Wavelength division multiplexing

来源：评论

学校读者我要写书评

暂无评论

Multiport Remote JTAG Over Optical Fibers Under Radiation Environment

引用

IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 526-529页

作者： Nakao, M. Nakazawa, Y. Sudo, H. Honda, R. Taniguchi, N. High Energy Accelerator Res Org KEK Tsukuba 3050801 Japan Univ Tokyo Tokyo 1138654 Japan

The Joint Test Action Group (JTAG) protocol is a popular method to program field-programmable gate array (FPGA) devices where a more intelligent technology is not applicable. However, the original JTAG protocol is designed for a short-distance connection and is not necessarily suitable when the FPGA device is located in a remote radiation area. We developed a custom optical transmission technique for the JTAG protocol. A small receiver test board is developed based on discrete devices, and a multiport distributor is implemented on an FPGA board. We also developed a technique to overcome the latency due to serialization and cable length. We present the evaluation results and future applications.

关键词： field programmable gate arrays Protocols Clocks Transceivers Programming Universal Serial Bus Prototypes Organizations Physics Optical receivers Circuit emulation data acquisition systems field-programmable gate arrays (FPGAs) front-end electronics high-energy physics (HEP) optical signal processing radiation effects

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：