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Real-Time Digital Baseline Restoration for CCD Sensors With Implementation in FPGA

IEEE SENSORS JOURNAL 2024年第22期24卷 37104-37113页

作者： Feng, Qi Zhang, Hongfei Chen, Cheng Wang, Hui Wang, Jian Univ Sci & Technol China Dept Modern Phys State Key Lab Particle Detect & Elect Hefei 230026 Peoples R China Deep Space Explorat Lab Hefei 230088 Peoples R China

Charge-coupled device (CCD) sensors are the primary imaging sensors in scientific astronomical cameras, known for their exceptional channel uniformity. However, the unavoidable baseline drift during alternating current (ac) coupling leads to inconsistencies among pixels in the row direction, especially during high-speed readouts. Standard corrections are insufficient, posing challenges to astronomical observations. The digital correlated double sampling (DCDS) technology enables digital signal processing (DSP) for CCD readout. A real-time digital baseline restoration method was developed and implemented in a field-programmable gate array (FPGA). This method overcomes traditional limitations and can eliminate baseline drift error effectively. Furthermore, the performance of this method in terms of readout noise, channel gain, and nonlinearity was tested, confirming its potential for compensating for baseline drift error in scientific applications.

关键词： Charge coupled devices Sensors Image restoration Cameras Switches field programmable gate arrays Real-time systems Couplings CCD image sensors Noise Baseline camera charge-coupled device (CCD) digital correlated double sampling (DCDS) image sensors real time

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32-Bit Fixed and Floating-Point Hardware Implementation for Enhanced Inverter Control: Leveraging FPGA in Recurrent Neural Network Applications

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IEEE ACCESS 2024年 12卷 111097-111110页

作者： Hingu, Chanakya Fu, Xingang Vangala, Praneeth Mishan, Ramkrishna Fajri, Poria Univ Nevada Dept Elect & Biomed Engn Reno NV 89503 USA Texas A&M Univ Dept Elect Engn & Comp Sci Kingsville TX 78363 USA

Traditional microcontroller-based control systems increasingly face limitations due to their restricted capabilities and lack of parallel processing, creating bottlenecks in real-time energy optimization. This research introduces a novel approach to implementing a Recurrent Neural Network (RNN) model on a field-programmable gate Array (FPGA) board. By harnessing the FPGA's parallel processing power, the research aims to overcome these limitations and enhance the performance of inverters. The programming for a four-input, two-output RNN model featuring a Tangent hyperbolic (Tanh) activation function is designed for 32-bit fixed and floating-point operations using Intel Quartus Prime software. A crucial aspect of this study involves meticulous timing and resource analyses to optimize the design's performance on the FPGA. Furthermore, the digit and bit accuracy of the FPGA implementation is rigorously verified against MATLAB and ModelSim simulations, ensuring the reliability of the results. The proposed method of FPGA implementation not only demonstrates a cutting-edge technique for Neural Network applications but also sets a precedent for further explorations into various types of Neural Networks (NN). This research thus opens new avenues for the innovative application of FPGA technology in the field of NN, potentially revolutionizing the way these systems are designed and implemented.

关键词： field programmable gate arrays Artificial neural networks Inverters Hardware Recurrent neural networks Neural networks Matlab Neural network controller hardware implementation FPGA 32-bit fix and floating point implementation Tanh function LUT CORDIC

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A Priori-Knowledge-Free Real-Valued Capon-Like Method and Implementation on FPGA

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第12期71卷 6532-6543页

作者： Chen, Yili Fu, Zhe Li, Jianzhong Guangdong Univ Technol Sch Integrated Circuits Guangzhou 510000 Guangdong Peoples R China

Improving real-time computational efficiency is a major research direction in Direction-Of-Arrival (DOA) estimation. In this paper, a novel computationally efficient real-valued DOA estimator is presented, in which the estimation is performed without the need for EigenValue Decomposition (EVD) and therefore avoids estimating the source number in advance. Following the comparison between the traditional MUSIC algorithm and the Capon Method, we present a general form of DOA estimation, which reveals that the construction of the noise subspace in the traditional MUSIC algorithm derives from the activation function performed on the eigenvalues. Unlike the classic subspace-based algorithm, our proposed activation-like function eliminates the reliance on subspace decomposition, thereby removing the need for source number estimation and mitigating performance degradation caused by incorrect estimations. Moreover, existing real-valued DOA algorithms would estimate both the true DOAs and their corresponding mirror DOAs, and the space-shifting property is used to eliminate the mirror DOAs. In addition, the field programmable gate Array (FPGA) implementation for our proposed real-valued algorithm is developed, showing a dramatic reduction of the hardware resource consumption and computation burden compared with the complex-valued MUSIC. Experiments illustrate that our proposed algorithm is computationally more efficient, and achieves higher estimation resolution compared to the existing methods.

关键词： Direction-of-arrival estimation Estimation Multiple signal classification Covariance matrices field programmable gate arrays Signal processing algorithms Computational efficiency Direction-of-arrival (DOA) estimation subspace method field programmable gate array real-valued computation

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Simultaneous integration of pattern, frequency and polarization diversities in broadband programmable metasurface for computational imaging

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OPTICS EXPRESS 2024年第24期32卷 42964-42982页

作者： Du, Jiachen Liu, Baiyang Wu, Geng-bo Chan, Ka fai Chan, Chi hou Zhang, Qingfeng City Univ Hong Kong State Key Lab Terahertz & Millimeter Waves Kowloon Tat Chee Ave Hong Kong Peoples R China Southern Univ Sci & Technol Dept Elect & Elect Engn State Key Lab Opt Fiber & Cable Manufacture Techno Shenzhen Peoples R China Shenzhen Technol Univ Coll Big Data & Internet Shenzhen Peoples R China

The field diversity of a metasurface stands out as a crucial figure of merit for computational imaging. Conventional techniques typically leverage either pattern diversity through a programmable metasurface or frequency diversity due to dispersion response to enhance sensing capacity. Simultaneously employing pattern diversity and frequency diversity in programmable systems remains highly challenging and currently unattainable, primarily due to the absence of a broadband programmable metasurface. This paper proposes a 1-bit broadband programmable metasurface, enabling the simultaneous utilization of pattern diversity and frequency diversity to tackle this difficulty for computational imaging. The proposed programmable metasurface has a 1-bit phase response (corresponding to 0 degrees and 180 degrees) for each unit cell, which works from 15.5 GHz to 27.5 GHz (corresponding to 55.8% relative bandwidth). A computational imaging system is subsequently implemented using the designed metasurface and field-programmable gate array (FPGA) control board. The experimental results demonstrate that the implemented imaging system has significantly enhanced sensing capacity, thanks to the simultaneous utilization of pattern diversity and frequency diversity. Furthermore, we incorporate polarization to further improve the image quality for polarization-sensitive targets by a 90 degrees rotation of the metasurface system and modification of the control coding. (c) 2024 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement

关键词： Biomedical imaging Computational imaging field programmable gate arrays Imaging systems Phase diversity Synthetic aperture radar

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Prototype Design of the Readout System for NνDEx-100 Experiment

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2024年第11期71卷 2442-2448页

作者： Chen, Kai Lang, Lei Zhu, Dou Song, Xinyue Yang, Yongqiang Liang, Tianyu Li, Hongtao He, Ziyi Gao, Chaosong Liu, Jun Lu, Chengui Yang, Yichen Zhao, Chengxin Xiao, Le Zhang, Dongliang Wang, Hulin Cent China Normal Univ Key Lab Quark & Lepton Phys MOE Wuhan 430079 Peoples R China Chinese Acad Sci Inst Modern Phys Lanzhou 730000 Peoples R China

N nu DEx is an upcoming neutrino-less double-beta decay experiment. A first small-scale prototype, named N nu DEx-100, features a readout plane with a 0.9 m diameter situated at one end-cap of its time projection chamber (TPC). This plane hosts around 10000 charge measurement sensors requiring dedicated readout electronics. This paper introduces the prototype design of the readout electronics and its integration with the back-end data acquisition (DAQ) system, which is composed of dedicated firmware and software to handle the system control and data readout. In the front-end, the demonstration system is developed to house 19 sensors along with the necessary supporting circuitry. The functionality and performance of the entire demonstration system with Topmetal-S sensors are evaluated, and the ion measurement capability of the system has been confirmed by tracking particles irradiated from the( 241)Am alpha source.

关键词： Sensors Data acquisition field programmable gate arrays Ions Focusing Readout electronics Voltage Transceivers Sensor systems Pins Negative-ion time projection chamber (TPC) neutrino-less double-beta decay ( 0 nu beta beta ) readout electronics waveform digitization

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Analog High-Level Synthesis for field programmable Analog arrays

Analog High-Level Synthesis for Field Programmable Analog Ar...

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Opportunity Research Scholars Symposium (ORSS)

作者： Luke Hanks Cullen Lonergan Karsten Richardson Jennifer Hasler Pranav Mathews Afolabi Ige School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta Georgia USA

ISBN: (数字)9798350390698

ISBN: (纸本)9798350390704

In this paper, we describe our effort to extend the development of a standard framework for analog computing through further developing and integrating an existing high level synthesis (HLS) tool for analog system design. These Python and Scilab based tools allow designers to design and implement reconfigurable systems on field-programmable analog arrays (FPAA). In doing this, we can provide a way to have the same ease of development that digital integrated circuits (ICs) have with the field-programmable gate-array (FPGA). We describe the importance of analog computing, the state of the old tool flow, our contributions to upgrading the tool flow, and our demonstration of the working tools.

关键词： Phased arrays Digital integrated circuits field programmable analog arrays Logic gates High level synthesis Design tools field programmable gate arrays System analysis and design Standards Python

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DCryp-Unit: Crypto Hardware Accelerator Unit Design for Elliptic Curve Point Multiplication

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IEEE ACCESS 2024年 12卷 17823-17835页

作者： Alharbi, Adel R. Hazzazi, Mohammad Mazyad Jamal, Sajjad Shaukat Aljaedi, Amer Aljuhni, Abdullah Alanazi, Dalal J. Univ Tabuk Coll Comp & Informat Technol Tabuk 71491 Saudi Arabia King Khalid Univ Coll Sci Dept Math Abha 61413 Saudi Arabia Univ Tabuk Fac Sci Dept Math Tabuk 71491 Saudi Arabia

We propose a hardware-optimized design that implements a Montgomery Elliptic-curve point multiplication Algorithm over GF(2(233)) using Lopez-Dahab projective coordinates. Moreover, we propose a digit-parallel modular multiplier, which reduces clock cycles and improves throughput. Also, we provided how to use our proposed digit-parallel multiplier for post-quantum cryptography algorithms. In addition, we use the proposed digit-parallel multiplier with the square circuit to implement the Itoh-Tsujii inversion algorithm for modular inversion computation;this permits hardware resource minimization. An efficient finite-state machine controller is implemented for control functionalities. A figure of merit in throughput/area is defined for reasonable comparison to state-of-the-art. We provide implementation results after post-place-and-route on field-programmable gate array devices. On the Virtex-7 device, our design utilizes 3386 slices and requires 7218 clock cycles;it achieves a maximum frequency of 365 MHz and computes one point multiplication in 19.77 mu s . The total power consumption of our design is 2027 mW. The calculated values for throughput and figure of merit are 50.58Kbps and 14.93, respectively. Consequently, the implementation results and comparisons reveal our design's suitability for applications requiring area and throughput-optimized cryptographic implementations.

关键词： Hardware acceleration field programmable gate arrays Cryptography Computer architecture Throughput Elliptic curve cryptography Elliptic curves Binary elliptic curves point multiplication hardware design implementation FPGA

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FSpGEMM: A Framework for Accelerating Sparse General Matrix–Matrix Multiplication Using Gustavson’s Algorithm on FPGAs

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2024年第4期32卷 633-644页

作者： Tavakoli, Erfan Bank Riera, Michael Quraishi, Masudul Hassan Ren, Fengbo Arizona State Univ Tempe AZ 85287 USA

General sparse matrix-matrix multiplication (SpGEMM) is integral to many high-performance computing (HPC) and machine learning applications. However, prior field-programmable gate array (FPGA)-based SpGEMM accelerators either use the inner product algorithm with wasted and costly operations or Gustavson's algorithm with a cache-based hardware architecture suffering from long-latency cache miss penalties and limited to embedded devices. In this work, we propose framework for accelerating SpGEMM (FSpGEMM), an OpenCL-based SpGEMM framework for accelerating Gustvason's algorithm that includes an FPGA kernel implementing a throughput-optimized and scalable hardware architecture compatible with high-bandwidth memory (HBM) or traditional DDR-based memory. In addition, to address the irregular memory access patterns incurred by Gustavson's algorithm, we propose a new buffering scheme tailored to Gustavson's algorithm enabled by a new compressed sparse vector (CSV) format for representing sparse matrices and a row reordering technique as a preprocessing step to improve data reuse, and consequently, resource utilization. The proposed framework includes a host program implementing preprocessing functions for reordering input matrices and storing them in the proposed CSV format for further use. We implemented FSpGEMM using Intel FPGA SDK for OpenCL and experimented with a benchmark of sparse matrices selected from the SuiteSparse Matrix Collection on a Bittware 520N-MX FPGA board. The results show that the reordering technique improves the performance on average by 20.3% compared with the baseline. Finally, FSpGEMM outperforms the state-of-the-art (SOTA) FPGA implementation by an average of 2.23 $\times$ in terms of execution cycles with the same benchmark and memory system configuration for a fair comparison.

关键词： field programmable gate arrays Sparse matrices Hardware Memory management Graphics processing units Indexes Matrix converters field-programmable gate array (FPGA) general sparse matrix-matrix multiplication (SpGEMM) Gustavson's algorithm OpenCL reconfigurable computing

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CTFE: A High-Efficient Heterogeneous Cryptographic CGRA for Diverse Security Applications

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2025年第5期44卷 1793-1806页

作者： Le, Vu Trung Duong Pham, Hoai Luan Tran, Thi Hong Tran, Van Duy Vu, Tuan Hai Nakashima, Yasuhiko Nara Inst Sci & Technol Grad Sch Informat Sci Ikoma 6300192 Japan Osaka Metropolitan Univ Grad Sch Informat Osaka 5588585 Japan

Nowadays, cryptographic computation across various security applications necessitates the development of hardware that is not only fast and power-efficient but also flexible enough to support a range of cryptographic algorithms. Unfortunately, existing computing platforms for cryptography struggle to balance high flexibility, high performance, and low power consumption. To address these issues, this article introduces the crypto-tailored flexible engine (CTFE), a next-generation coarse-grained reconfigurable array (CGRA) for cryptography. Concretely, the CTFE incorporates four innovative ideas to achieve high flexibility and performance with high hardware efficiency: 1) processing element array (PEA) with dual-buffer lanes and multiplexer optimization;2) high flexibility Hyper-ALU;3) heterogeneous PEA;and 4) bi-tiered pipeline coordination. Real-time evaluation results on Xilinx ZCU102 FPGA at the System-on-Chip (SoC) level demonstrate that the CTFE is 1.13-14.3 times better in throughput and 55.3-14 232 times better in energy efficiency than state-of-the-art CPUs. Experiments on an ASIC 45 nm CMOS technology show that the CTFE consumes the power of 1.06 W, occupies an area of 2.77mm(2) , and operates at the frequency of 510 MHz. In comparison to existing CGRA solutions, CTFE outperforms 1.63-20.23 times in throughput and 1.61-73.2 times in area efficiency.

关键词： Cryptography Ciphers Security Hardware Hash functions Computer architecture Power demand Throughput field programmable gate arrays Elliptic curve cryptography Blockchain coarse-grained reconfigurable array (CGRA) cryptography FPGA society 5.0

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SCALES: SCALable and Area-Efficient Systolic Accelerator for Ternary Polynomial Multiplication

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2024年第2期23卷 243-246页

作者： Coulon, Samuel Bao, Tianyou Xie, Jiafeng Villanova Univ Dept Elect & Comp Engn Villanova PA 19085 USA

Polynomial multiplication is a key component in many post-quantum cryptography and homomorphic encryption schemes. One recurring variation, ternary polynomial multiplication over ring Z(q)/(x(n)+1) where one input polynomial has ternary coefficients {-1,0,1} and the other has large integer coefficients {0, $q-1$q-1}, has recently drawn significant attention from various communities. Following this trend, this paper presents a novel SCALable and area-Efficient Systolic (SCALES) accelerator for ternary polynomial multiplication. In total, we have carried out three layers of coherent interdependent efforts. First, we have rigorously derived a novel block-processing strategy and algorithm based on the schoolbook method for polynomial multiplication. Then, we have innovatively implemented the proposed algorithm as the SCALES accelerator with the help of a number of field-programmable gate array (FPGA)-oriented optimization techniques. Lastly, we have conducted a thorough implementation analysis to showcase the efficiency of the proposed accelerator. The comparison demonstrated that the SCALES accelerator has at least 19.0% and 23.8% less equivalent area-time product (eATP) than the state-of-the-art designs. We hope this work can stimulate continued research in the field.

关键词： Polynomials field programmable gate arrays Vectors Transforms Matrix decomposition Time complexity Systolic arrays Shift registers Proposals Process control Area-efficient block-processing FPGA scalable systolic hardware accelerator ternary polynomial multiplication

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