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Fast Update Algorithm With Reorder Mechanism for SRAM-Based Longest Prefix Matching on FPGA

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第1期71卷 420-424页

作者： Song, Xiaoyong Guo, Zhichuan Chinese Acad Sci Inst Acoust Natl Network New Media Engn Res Ctr Beijing 100190 Peoples R China Univ Chinese Acad Sci Sch Elect Elect & Commun Engn Beijing 100049 Peoples R China

Longest prefix matching (LPM) is often used in network forwarding and it is usually implemented by ternary content addressable memory (TCAM) on field programmable gate array (FPGA). The traditional SRAM based TCAM only has one clock cycle in search delay, but it has a non-negligible update latency. Different from the general TCAM words, the ternary bits in LPM words are arranged continuously from low bits to high, and the prefix lengths of words have some distribution characteristics on actual network traffics. In this brief, a design is proposed to reduce the update latency of LPM by fast update algorithm with reorder mechanism. The key idea is reorder LPM prefix and partition don't care bits into each sub-prefix evenly in SRAM based LPM, so that the update latency in each sub-table would be minimized and the whole update latency would be reduced. The design of this brief is implemented on Xilinx Kintex-7 field-programmable gate array. Compared to the prior methods, the update latency of LPM is reduced by at least half or more in most cases with our method. As far as we know, this is the fastest update mechanism in SRAM based LPM, which consumes the least possible clock cycles.

关键词： Random access memory field programmable gate arrays Clocks Partitioning algorithms Engines Pattern matching Memory management field programmable gate array (FPGA) SRAM-based TCAM longest prefix matching (LPM) update latency IP lookup

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FPGA implementation of power-lite Volterra-inspired neural network equalizer in 180-Gb/s net bitrate IMDD short-reach optical system

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OPTICS LETTERS 2024年第16期49卷 4573-4576页

作者： Jiang, Wenqing Guan, Xiaokai Huang, Luyao Xu, Yongxin Xie, Yunhao Hu, Weisheng Yi, Lilin Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn State Key Lab Adv Opt Commun Syst & Networks Shanghai 200240 Peoples R China China Telecom Res Inst Guangzhou Peoples R China

A white-box power-lite Volterra-inspired neural network (VINN) equalizer is proposed to solve the problem of (VNLE). By adjusting the granularity of the solution space, it conserves computational resources while maintaining nonlinear compensation capability. The performance of VINN is verified on a field-programmable gate array (FPGA) in a short-reach intensity modulation and direct detection (IMDD) system, and a 240-Gb/s real-time signal processing rate is achieved. Under the 25% overhead soft-decision threshold, we realize a record net rate of up to 180 Gb/s based on the FPGA. (c) 2024 Optica Publishing Group. All rights, training, and similar technologies, are reserved.

关键词： field programmable gate arrays Neural networks Optical signals Optical systems Signal processing Variable optical attenuators

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Pulse Synchronization Scheme for Undersea BWPT System Based on Simultaneous Wireless Power and Data Transfer Technology

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2025年第1期72卷 333-337页

作者： Da, Chaolai Li, Fang Wang, Lifang Tao, Chengxuan Li, Shufan Nie, Ming Chinese Acad Sci Inst Elect Engn Key Lab High Dens Electromagnet Power & Syst Beijing 100190 Peoples R China Univ Chinese Acad Sci Sch Elect Elect & Commun Engn Beijing 100049 Peoples R China

A novel pulse synchronization scheme is proposed in this brief based on simultaneous wireless power and data transfer (SWPDT) technology to address the pulse synchronization issue of the undersea bidirectional wireless power transfer (BWPT) system due to the special characteristics of the undersea environment. Accurate pulse synchronization can be implemented by adapting the software to the existing SWPDT system based on the DDQ coil. Furthermore, this brief proposes a phase lock scheme that can eliminate the issue of pulse false triggering, which is caused by the interference of the BWPT channel to the data channel. A prototype with an output power of 1 kW and a data rate of 1 Mb/s demonstrates the feasibility of the pulse synchronization scheme proposed in this brief. The work of this brief extends the application of SWPDT technology and also presents a new solution for pulse synchronization in the BWPT system.

关键词： Synchronization field programmable gate arrays Coils Accuracy Interference Demodulation Circuits Couplings Software Pulse width modulation Bidirectional wireless power transfer (BWPT) modulation and demodulation pulse synchronization simultaneous wireless power and data transfer (SWPDT) undersea wireless power transfer (UWPT)

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Lattice-Based Fault Attack and Defensive Strategies Targeting the SM2 Signature Algorithm

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ELECTRONICS LETTERS 2025年第1期61卷

作者： Shao, Cuiping Li, Wenzhe Li, Huiyun Liang, Jianing Shenzhen Univ Adv Technol Shenzhen Peoples R China Univ Chinese Acad Sci Beijing Peoples R China Chinese Acad Sci Shenzhen Inst Adv Technol Shenzhen Guangdong Peoples R China

Fault attacks targeting signature nonce pose a critical threat to elliptic curve digital signatures, potentially exposing private keys through non-invasive methods. This letter presents an efficient and practical defence strategy against lattice-based fault injection attacks on ephemeral nonce in the SM2 digital signature algorithm (SM2-DSA). Our proposed countermeasure effectively protects against such sophisticated lattice-based fault attacks while maintaining minimal overhead in both time and hardware resources. Specifically, our countermeasure incurs only a 0.8% time overhead and the area overhead for secure design does not exceed 1%. Our research provides valuable insights for evaluating the security of hardware implementations of SM2-DSA.

关键词： cryptography field programmable gate arrays integrating circuits

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The Pains of Hardware Security: An Assessment Model of Real-World Hardware Security Attacks

IEEE OPEN JOURNAL OF THE INDUSTRIAL ELECTRONICS SOCIETY

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IEEE OPEN JOURNAL OF THE INDUSTRIAL ELECTRONICS SOCIETY 2025年 6卷 603-617页

作者： Maragkou, Sofia Rappel, Lukas Dettmer, Hendrik Sauter, Thilo Jantsch, Axel TU Wien Inst Comp Technol ICT A-1040 Vienna Austria TUV Austria GMBH A-1230 Vienna Austria Univ Continuing Educ Krems Dept Integrated Sensor Syst A-2700 Wiener Neustadt Austria

From military applications to everyday devices, hardware (HW) security is more relevant than ever before. The supply chain of integrated circuits is global and involves multiple actors, which facilitate the implementation of various attacks. Its complexity increases the attack surfaces, violating not only the privacy of the users or even national security but also endangering human life. We review some of the publicly known HW attacks that have occurred and propose an assessment scheme for the attacks and the defense on hardware. Using this scheme, we relate the costs of attacks and defense and provide a structured landscape of HW attacks. To illustrate the utility of our assessment scheme, we apply it to a number of real-world and synthetic research cases. We observe a gap between the research use cases and the real-world attacks and envision that the comprehensive assessment of the attacks will enable the development of more suitable countermeasures. In addition, we revised the security policies for HW devices, and we conclude that the complexity and obscurity of the supply chain are key parameters impacting HW security, providing attack surfaces. Finally, we identify the demystification of the supply chain as the main strategy to mitigate this problem.

关键词： Hardware Supply chains Security Hardware security Fabrication field programmable gate arrays Software Microprogramming Costs Complexity theory Assessment scheme counterfeit chips hardware (HW) attacks HW security HW security policies HW Trojans real-world HW attacks side-channel analysis supply chain analysis

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Unleashing Network/Accelerator Co-Exploration Potential on FPGAs: A Deeper Joint Search

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2024年第10期43卷 3041-3054页

作者： Lou, Wenqi Gong, Lei Wang, Chao Qian, Jiaming Wang, Xuan Li, Changlong Zhou, Xuehai Univ Sci & Technol China Sch Software Engn Hefei 230026 Peoples R China Univ Sci & Technol China Suzhou Inst Adv Res Suzhou 215000 Peoples R China Univ Sci & Technol China Sch Comp Sci Hefei 230027 Peoples R China East China Normal Univ Sch Comp Sci Shanghai 200062 Peoples R China

Recently, algorithm-hardware (HW) co-exploration for neural networks (NNs) has become the key to obtaining high-quality solutions. However, previous efforts for field-programmable gate arrays (FPGAs) focus on neural architecture search (NAS) while lacking HW architecture search (HAS), thus limiting the full potential of co-design. Although expanding the scope of HAS offers performance potential, the exponentially increased joint search space presents a formidable challenge. To address this, we propose a deep and efficient framework NAF, which jointly searches for Networks and Accelerators for FPGAs in a balanced co-search space. First, we adjust the NAS space and then introduce a block-level bitwidth search on the software side. Meanwhile, we design a HW-friendly quantization algorithm to facilitate HW efficiency and accuracy. Second, we design a dataflow-configurable HW unit with computation and memory access optimizations for quantized multiplication. Based on this, we incorporate critical heterogeneous multicore architecture exploration on the HW side. Third, to enable rapid HW feedback in the enlarged HAS space, we perform resource and performance modeling and design a fast HW generation algorithm based on the genetic algorithm. Specifically, we apply optimization techniques, like mapping space pruning, greedy bandwidth allocation, and coarse-grained search, to speed up this process. We validate NAF in edge and cloud scenarios. Experimental results show that NAF efficiently explores a significantly larger joint space and provides high-quality solutions. Compared with previous state-of-the-art co-design works, the searched convolutional neural network-accelerator pairs improve the throughput by $2.07\times \sim 7.10\times $ and energy efficiency by $1.41\times \sim 2.27\times $ under similar accuracy on the ImageNet dataset.

关键词： Hardware field programmable gate arrays Multicore processing Computer architecture Quantization (signal) Artificial neural networks Software algorithms Convolutional neural network (CNN) field-programmable gate array (FPGA) software-hardware (HW) co-exploration

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Near-zero distortion in TCSPC at more than one photon per excitation period: experimental validation

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OPTICS LETTERS 2024年第17期49卷 4958-4961页

作者： Fratta, Gennaro Daniele, Piergiorgio Labanca, Ivan Acconcia, Giulia Rech, Ivan Politecn Milan Dipartimento Elettron Informaz & Bioingn Via Golgi 40 I-20133 Milan Italy

The time-correlated single-photon counting (TCSPC) technique is widely renowned for its capability of reconstructing rapid and weak light signals with exceptional sensitivity and sub-picosecond timing resolution. Unfortunately, the speed of TCSPC has been historically severely limited to avoid a phenomenon known as pileup distortion. For this reason, the count rate of a classic TCSPC acquisition channel is kept below a few percent of the laser excitation rate (usually 17c-57c). In this work, we experimentally validate a novel, to our knowledge, TCSPC theory recently reported that effectively overcomes such a limitation and finally achieves high-speed operation without distortion. Exploiting a singlephoton avalanche diode (SPAD), in this paper we show how to acquire additional information about the status of the system at run time, and by combining it with the classic TCSPC data histogram, we report how a count rate of approximately 607c of the excitation frequency with near-zero distortion can indeed be achieved with a commercial system. (c) 2024 Optica Publishing Group. All rights, including for text and data mining are reserved.

关键词： Analog to digital converters Diode lasers Distortion field programmable gate arrays Photon counting Single-photon avalanche diodes

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Zero-DCE xT: A Computational Approach to Addressing Low-Light Image Enhancement Challenges

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第9期71卷 4401-4405页

作者： Ahmadi, Candra Chen, Jiann-Liang Hsiao, Yu-Yi Natl Taiwan Univ Sci & Technol Dept Elect Engn Taipei 106335 Taiwan

In the dynamic field of digital image processing, effectively enhancing low-light images presents a significant challenge. This brief narrows its focus to the preservation of natural aesthetics in low-light enhancement. The knowledge gap identified is the need for an approach that balances visibility improvement with authentic color retention without computational burden. We introduce the Zero-DCE xT model, an evolution of the Zero-DCE framework, optimized for structure and function in low-light conditions. Our experimental work shows the Zero-DCE xT model's capability to significantly reduce prediction errors and improve image quality, achieving high scores in PSNR, VIF, and SSIM across various datasets. Notably, Zero-DCE xT combines visual appeal with computational efficiency, making it ideal for real-time applications. The implications of our findings suggest that the Zero-DCE xT model sets a new standard for low-light image processing, marrying robust performance with economical computation, and paving the way for future research in advanced imaging systems.

关键词： Image enhancement Computational efficiency Image color analysis Quantization (signal) Visualization Measurement field programmable gate arrays image quality low-light enhancement prediction error Zero-DCE xT

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Implementation in FPGA of Alternative Modulation Strategy for Energy Balancing Purposes

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第1期16卷 29-32页

作者： Reyes Severiano, Yesenia Aguayo Alquicira, Jesus De Leon Aldaco, Susana Carrillo Santos, Luis TecNM Cenidet Elect Engn Dept Cuernavaca 62490 Mexico

Currently, the study of energy balancing in cascaded multilevel inverter cells is desirable due to the growing interest in implementing systems that minimize losses, ensure delivery of the maximum amount of power to the load, contribute to system reliability, and at the same time minimize the use of resources for its implementation. One of the ways to carry out energy balancing without resorting to additional topology is by modifying conventional modulation techniques. In this letter, the FPGA implementation of modulation strategies for energy balancing purposes is carried out. First, three conventional techniques are addressed: 1) phase-shifted carrier disposition;2) level shift per carrier cycle;and 3) level shift per modulator cycle. Subsequently, the implementation of an alternative modulation strategy that performs energy balancing in the cascaded multilevel inverter, minimizing the use of digital resources, is presented.

关键词： Modulation Codes Multilevel inverters Switches field programmable gate arrays Clocks Voltage Cascaded multilevel inverter field-programmable gate array (FPGA) modulation technique power balance total harmonic distortion (THD)

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Stepped Waveform Time-Modulated Multibeam Array With Beam Suppression Functionality

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IEEE ANTENNAS AND WIRELESS PROPAGATION LETTERS 2024年第9期23卷 2638-2642页

作者： Chen, Qiaoyu Zhang, Jin-Dong Cai, Ming-Xuan Luo, Deng-Yue Wu, Wen Fang, Da-Gang Nanjing Univ Sci & Technol Sch Elect & Opt Engn Lab Near Range RF Sensing ICs & Microsyst NJUST Minist Educ Nanjing 210094 Peoples R China

Time-modulated array (TMA) naturally generates a large number of sidebands to achieve multibeam radiation. Conventional multibeam TMAs using rectangular modulation signals lack design flexibility, and recent high-flexibility designs are mostly theoretical without experimental validation. To balance flexibility and feasibility, this letter proposes a stepped waveform multibeam TMA with beam suppression functionality. It uses in-phase/quadrature (I/Q) time modulators with digital attenuators and 0/pi phase shifters to independently generate stepped waveforms in both in-phase and quadrature channels. These waveforms can fit various complex modulation signals, enabling the realization of diverse multibeam radiations and the suppression of specific beams. Experimental verification is conducted on the same TMA hardware system, achieving a 5-beam TMA and a 4-beam TMA by adjusting the time-modulated signals. The suppressed beams achieve a suppression level of up to -36 dB, making it effective for anti-interference.

关键词： Amplitude modulation Attenuators Hardware field programmable gate arrays Interference Phase modulation Frequency modulation Anti-interference beam suppression in-phase/quadrature (I/Q) modulation multibeam antenna time-modulated array (TMA)

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