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Development of FPGA-Based Nuclear Electronics Using NI MyRIO Hardware for Small-Scale Radiation Detector Systems

IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 380-384页

作者： Hai, Vo Hong Phuc, Nguyen Tri Toan Trang, Hoang Thi Kieu Loan, Truong Thi Hong Sang, Phan Le Hoang Univ Sci VNUHCM Fac Phys & Engn Phys Dept Nucl Phys Ho Chi Minh City 700000 Vietnam

This study presents advancements in coincidence electronics and a pulse height analyzer (PHA) utilizing commercial field-programmable gate array (FPGA)-based hardware for radiation scintillation detectors. The hardware, based on a cost-effective NI myRIO device, integrates an FPGA, ARM Cortex-A9 processor, analog input (AI), digital input and output (DIO), and USB/wireless connectivity with a host computer. LabVIEW codes developed on the LabVIEW platform are implemented in the NI myRIO hardware for seamless integration and interfacing with a computer. The performance of the FPGA-based coincidence electronics is assessed through an experimental setup measuring the gamma-gamma angular distribution of a 22Na radioisotope source. Similarly, the FPGA-based PHA is tested with a CsI(Tl) detector, and its energy resolution is compared to a commercial EASY-MCA 2 K from AMETEK Inc.

关键词： Detectors field programmable gate arrays Hardware Radiation detectors Clocks Logic gates Energy measurement Computer interfaces Pulse measurements Nuclear electronics Angular distribution coincidence energy spectrum pulse height analyzer scintillator detector

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An Energy-Efficient FPGA Accelerator for Swin Transformer

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第6期33卷 1774-1778页

作者： Wang, Yuefei Mao, Wendong Shi, Huihong Sha, Jin Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210093 Peoples R China Sun Yat Sen Univ Sch Integrated Circuits Guangzhou 510275 Peoples R China

Recently, transformers have shown strong performance in tasks such as computer vision and natural language processing. Notably, Swin Transformer has gained significant attention for its low computational complexity and impressive performance in computer vision tasks, due to its window attention mechanism and hierarchical architecture. However, these features also make hardware deployment more complicated. In this brief, we present an energy-efficient field-programmable gate array (FPGA) accelerator for Swin Transformer to support the hierarchical architecture and execute the window attention. First, we introduce a systolic array with alterable datapath (SAAD) to conduct the window attention. Second, we split the patch merging operation and design a data rearrangement module, which reduces the computing latency induced by the data rearrangement in Swin Transformer. Third, we present a parallelized dual-array dataflow to support different computing operations in Swin Transformer. We implement the accelerator on the Xilinx XCZU19EG platform. The proposed architecture achieves a throughput per digital signal processing (DSP) of 0.630 giga operations per second (GOPS)/DSP, which is 1.94x higher than existing works.

关键词： Transformers Computer architecture field programmable gate arrays Random access memory Merging Systolic arrays Attention mechanisms Windows Optimization Convolution Computer vision deep learning field-programmable gate array (FPGA) hardware accelerator Swin Transformer

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Pulse Synchronization Scheme for Undersea BWPT System Based on Simultaneous Wireless Power and Data Transfer Technology

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2025年第1期72卷 333-337页

作者： Da, Chaolai Li, Fang Wang, Lifang Tao, Chengxuan Li, Shufan Nie, Ming Chinese Acad Sci Inst Elect Engn Key Lab High Dens Electromagnet Power & Syst Beijing 100190 Peoples R China Univ Chinese Acad Sci Sch Elect Elect & Commun Engn Beijing 100049 Peoples R China

A novel pulse synchronization scheme is proposed in this brief based on simultaneous wireless power and data transfer (SWPDT) technology to address the pulse synchronization issue of the undersea bidirectional wireless power transfer (BWPT) system due to the special characteristics of the undersea environment. Accurate pulse synchronization can be implemented by adapting the software to the existing SWPDT system based on the DDQ coil. Furthermore, this brief proposes a phase lock scheme that can eliminate the issue of pulse false triggering, which is caused by the interference of the BWPT channel to the data channel. A prototype with an output power of 1 kW and a data rate of 1 Mb/s demonstrates the feasibility of the pulse synchronization scheme proposed in this brief. The work of this brief extends the application of SWPDT technology and also presents a new solution for pulse synchronization in the BWPT system.

关键词： Synchronization field programmable gate arrays Coils Accuracy Interference Demodulation Circuits Couplings Software Pulse width modulation Bidirectional wireless power transfer (BWPT) modulation and demodulation pulse synchronization simultaneous wireless power and data transfer (SWPDT) undersea wireless power transfer (UWPT)

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Lattice-Based Fault Attack and Defensive Strategies Targeting the SM2 Signature Algorithm

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ELECTRONICS LETTERS 2025年第1期61卷

作者： Shao, Cuiping Li, Wenzhe Li, Huiyun Liang, Jianing Shenzhen Univ Adv Technol Shenzhen Peoples R China Univ Chinese Acad Sci Beijing Peoples R China Chinese Acad Sci Shenzhen Inst Adv Technol Shenzhen Guangdong Peoples R China

Fault attacks targeting signature nonce pose a critical threat to elliptic curve digital signatures, potentially exposing private keys through non-invasive methods. This letter presents an efficient and practical defence strategy against lattice-based fault injection attacks on ephemeral nonce in the SM2 digital signature algorithm (SM2-DSA). Our proposed countermeasure effectively protects against such sophisticated lattice-based fault attacks while maintaining minimal overhead in both time and hardware resources. Specifically, our countermeasure incurs only a 0.8% time overhead and the area overhead for secure design does not exceed 1%. Our research provides valuable insights for evaluating the security of hardware implementations of SM2-DSA.

关键词： cryptography field programmable gate arrays integrating circuits

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The Pains of Hardware Security: An Assessment Model of Real-World Hardware Security Attacks

IEEE OPEN JOURNAL OF THE INDUSTRIAL ELECTRONICS SOCIETY

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IEEE OPEN JOURNAL OF THE INDUSTRIAL ELECTRONICS SOCIETY 2025年 6卷 603-617页

作者： Maragkou, Sofia Rappel, Lukas Dettmer, Hendrik Sauter, Thilo Jantsch, Axel TU Wien Inst Comp Technol ICT A-1040 Vienna Austria TUV Austria GMBH A-1230 Vienna Austria Univ Continuing Educ Krems Dept Integrated Sensor Syst A-2700 Wiener Neustadt Austria

From military applications to everyday devices, hardware (HW) security is more relevant than ever before. The supply chain of integrated circuits is global and involves multiple actors, which facilitate the implementation of various attacks. Its complexity increases the attack surfaces, violating not only the privacy of the users or even national security but also endangering human life. We review some of the publicly known HW attacks that have occurred and propose an assessment scheme for the attacks and the defense on hardware. Using this scheme, we relate the costs of attacks and defense and provide a structured landscape of HW attacks. To illustrate the utility of our assessment scheme, we apply it to a number of real-world and synthetic research cases. We observe a gap between the research use cases and the real-world attacks and envision that the comprehensive assessment of the attacks will enable the development of more suitable countermeasures. In addition, we revised the security policies for HW devices, and we conclude that the complexity and obscurity of the supply chain are key parameters impacting HW security, providing attack surfaces. Finally, we identify the demystification of the supply chain as the main strategy to mitigate this problem.

关键词： Hardware Supply chains Security Hardware security Fabrication field programmable gate arrays Software Microprogramming Costs Complexity theory Assessment scheme counterfeit chips hardware (HW) attacks HW security HW security policies HW Trojans real-world HW attacks side-channel analysis supply chain analysis

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Robust Impedance Emulation for Transmission Line Interface in Power-Hardware-in-the-Loop Applications: Optimal Filter Approach

IEEE OPEN JOURNAL OF THE INDUSTRIAL ELECTRONICS SOCIETY

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IEEE OPEN JOURNAL OF THE INDUSTRIAL ELECTRONICS SOCIETY 2025年 6卷 158-169页

作者： Rimorov, Dmitry Forbes, James Richard Tremblay, Olivier Gagnon, Richard Hydroquebec Res Inst Power Syst Simulat Div Varennes PQ J3X 1S1 Canada Hydroquebec Res Inst Varennes PQ J3X 1S1 Canada McGill Univ Mech Engn Montreal PQ H3A 0G4 Canada

Power-hardware-in-the-loop (PHIL) simulation infrastructure is an invaluable tool for testing and validating emerging technologies expected to be connected to power grids. As such, PHIL closed-loop stability is a crucial factor to consider when designing its numerical interface. Recent work has shown that the transmission line method provides a robust solution to the PHIL interface stability problem while achieving a high level of PHIL closed-loop performance. However, to fully utilize its advantages, it requires a fast impedance emulation control loop. To solve this problem, this article proposes an H-infinity optimal filter approach for characteristic impedance emulation, which allows a systematic and tractable design procedure and produces a robust controller. Robust stability and performance are assessed through the positive realness check and by virtue of the structured singular value. The proposed method and the resulting controller are compared to an existing approach and validated on a 3-kVA, 208-V PHIL experimental testbed with different types of the device under test, including a residential solar inverter. The results demonstrate significant performance improvements that are crucial for the future megawatt-scale PHIL infrastructure.

关键词： Impedance Emulation Robust stability Iron Power harmonic filters field programmable gate arrays Current measurement Systematics Robustness Pulse width modulation H-infinity control optimal filtering power-hardware-in-the-loop (PHIL) simulation virtual impedance

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A Ultra-Low Cost and Accurate AMC Algorithm and Its Hardware Implementation

IEEE OPEN JOURNAL OF THE COMPUTER SOCIETY

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IEEE OPEN JOURNAL OF THE COMPUTER SOCIETY 2025年第1期6卷 460-467页

作者： Zhao, Yuqin Deng, Tiantai Gavin, Bill Ball, Edward A. Seed, Luke Univ Sheffield Sch Elect & Elect Engn Sheffield England

Automatic Modulation Classification (AMC) is one of the most important applications in the SDR field, which requires both accuracy and critical real-time processing. To address the challenges of speed and accuracy, this article presents a low-cost, and accurate AMC algorithm and its FPGA implementation that can achieve both fast and accurate results at the same time. This work focuses on achieving high accuracy at high SNRs and acceptable accuracy at low SNRs in a short processing time with extremely low power and recourse consumption. In this design, the CAMC algorithm is optimized to fit the FPGA characteristics to further improve the performance, and the computing demands of which could be saved over 94% compared with other state-of-the-art designs. Meanwhile, the CAMC FPGA implementation could save over 82% of the resource utilization and over 94% of the power consumption while a higher accuracy of 56% at 0 dB and 100% above 6 dB could still be performed at a 9.74x faster speed compared with the fastest AMC FPGA design so far.

关键词： field programmable gate arrays Hardware Training Modulation Power demand Optimization Classification algorithms Signal classification cognitive radio classification FPGA sparse matrices optimization modulation communication

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FPGA-Based Synchronization of Frequency-Domain Interferometer for QKD

IEEE TRANSACTIONS ON QUANTUM ENGINEERING

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IEEE TRANSACTIONS ON QUANTUM ENGINEERING 2025年第1期6卷 1-10页

作者： Chandra, Nishanth Krishnamurthy, Pradeep Kumar Indian Inst Technol Dept Elect Engn Kanpur 208016 India

In this article, we propose and experimentally demonstrate a novel synchronization method for quantum key distribution (QKD) systems. The method consists of maximizing the visibility of frequency-domain interference of optical sidebands about an optical carrier at the receiver node. The sidebands are generated by phase modulation of the optical carrier by an radio-frequency (RF) signal whose phase can be dynamically varied. The phase-variable RF signal is generated by the field-programmable gate array (FPGA) at the transmitter and the receiver using GTX transceivers. In order to facilitate this, we use square waveforms for RF signal instead of the conventional sinusoidal signals. We derive mathematical expressions for sideband power as a function of the phase difference between RF signals at transmitter and receiver. The phase is adjusted using dynamic phase shifter module, implemented by the FPGA. We propose a complete workflow that allows transmitter and receiver synchronization to within 12.6 ps directly over the quantum channel of QKD systems. Once synchronized, the same system can be switched over to quantum transmission by user-defined time delay. The workflow was implemented on a Xilinx Kintex-7 KC705 FPGA board. We studied the robustness of our technique by evaluating the stability of the interferometer over an operation of 10 min with standard deviation of interference to be less than 9% of the mean detection amplitude.

关键词： Synchronization Amplitude modulation field programmable gate arrays Radio frequency Optical modulation Optical interferometry RF signals Optical receivers Interference Clocks Clock synchronization field-programmable gate array (FPGA) frequency-coded quantum key distribution (FC-QKD) GTX transceiver quantum communication quantum cryptography quantum key distribution (QKD)

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FPGA implementation of low complexity super resolution scaling architecture for UHD display systems

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INTERNATIONAL JOURNAL OF ENGINEERING SYSTEMS MODELLING AND SIMULATION 2025年第2期16卷 63-75页

作者： Janardhan, Chidadala Ramanaiah, K. Venkata Babulu, K. Jawaharlal Nehru Technol Univ Kakinada Dept Elect & Commun Engn Kakinada 533003 Andhra Prades India Yogivemana Univ YSR Engn Coll Dept Elect & Commun Engn Proddatur 516361 Andhra Prades India Jawaharlal Nehru Technol Univ Gurajada Dept Elect & Commun Engn Vizianagaram 535003 Andhra Prades India

Ultra high definition (UHD) technology has been changing the entertainment industry significantly and its content is severely short of supply due to limited content creators or hard to access due to insufficient network bandwidth. Recent improvements in CMOS image sensor technology, multimedia applications traditional standard display (SD) systems are not sufficient to display high-quality images. Conventional FPGA-based SR methods will exhibit more complexity and requires more hardware resources to perform. This paper describes low complexity super resolution scaling architecture (SRSA) for UHD systems. In our proposed method, bi-cubic interpolation is used for reconstruction the low-frequency image to high-frequency images, these bi-cubic interpolations will have the capability to interpolate 16 nearest neighbours of a pixel. In addition to that high-frequency patches are overlapped to construct super resolutions images with using kernel algorithm. The proposed system generates the output image at 1,600 x 1,600 sizes from 800 x 800 image size. The proposed SRSA super-resolution technique is modelled in Verilog HDL and synthesised in Xilinx Zynq-7000 series FPGA and shown the comparison of area, delay, and power. From the simulation results, the performance of the proposed method can compete over the state of the art methods.

关键词： image interpolation super resolution image resolution field programmable gate arrays image restoration

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Single-Path High-Resolution Digital PWM Architectures With Cascadability of Delay Lines

IEEE OPEN JOURNAL OF POWER ELECTRONICS

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IEEE OPEN JOURNAL OF POWER ELECTRONICS 2025年 6卷 130-143页

作者： Hajiheidari, Marziyeh Fushekati, Joel Emad, Mohammad Vermulst, Bas J. D. van Duivenbode, Jeroen Huisman, Henk Eindhoven Univ Technol Dept Elect Engn Power Elect Lab PELe NL-5612 AZ Eindhoven Netherlands

This paper introduces two new single-path and cascaded High-Resolution Digital Pulse Width Modulation (HRDPWM) architectures. The proposed single-path architecture uses fewer FPGA resources to achieve the same resolution as conventional dual-path architectures. Moreover, the generated HRDPWM signal is independent of the Place-And-Route (PAR) algorithm applied by the synthesis tool, as well as temperature and voltage variations. The proposed cascaded architecture can be used to increase the DPWM resolution without raising the system clock frequency or, alternatively, to reduce the FPGA system clock frequency (relaxing timing challenges) without lowering the resolution. Both architectures have been implemented and verified using a mid-range Artix-7 FPGA with both triangular and sawtooth carriers. A time resolution of 39 ps has been achieved for the cascaded HRDPWM architecture with a sawtooth carrier and a system clock of 400 MHz. Additionally, a GaN-based synchronous buck converter is designed and implemented to evaluate the performance of the proposed HRDPWM architectures in a real application. It is demonstrated that bothhldead time and duty cycle can be modified with high accuracy and resolution and updated twice per switching cycle.

关键词： Clocks Signal resolution field programmable gate arrays Delay lines Delays Pulse width modulation Propagation delay Power electronics Switching frequency Switches Digital pulse width modulation (DPWM) delay line high resolution (HR) high switching frequency

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