The chance that a freeway will breakdown, transition from a free-flow to a congested state, is normally assumed to increase with an increase in traffic volume V (vehicles per unit time). In this paper, this assumption...
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ISBN:
(纸本)9781509064847
The chance that a freeway will breakdown, transition from a free-flow to a congested state, is normally assumed to increase with an increase in traffic volume V (vehicles per unit time). In this paper, this assumption is challenged. Traffic density K (vehicles per unit length) proves to be a better predictor. Diffusion or stochastic differential equation (SDE) modeling is used to substantiate the claim. SDE modeling is especially useful in explaining the role that traffic noise (volatility) plays in breakdown. The SDE models take advantage of the unique properties of the geometric Brownian motion (gBM) and Ornstein-Uhlenbeck (OU) model structures. The breakdown probability model of pi(K) and delay models provide accurate forecasts.
The paper will present a continuation of our investigation [1] in implementing a solderless assembly process for electronics. The addressed technology is known as the OCCAM process and was patented by Verdant Industri...
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ISBN:
(纸本)9781538605820
The paper will present a continuation of our investigation [1] in implementing a solderless assembly process for electronics. The addressed technology is known as the OCCAM process and was patented by Verdant Industries [2]. We present our proof of feasibility, at least for a prototyping phase on a single connection layer. Different from the original process that employs for the interconnection tracks a chemical (electroless) copper metallization, we will use a new conductive paste, especially developed for printed tracks. [3]. Beside the qualitative description of technological steps required to produce the OCCAM module, we will present also some quantitative results on the resistance of tracks printed with this conductive paste.
Wideband wireless communications base stations could benefit from efficient arithmetic algorithms for cost effective digital baseband computations. Power amplifiers are ubiquitous in such systems and exhibit nonlinear...
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ISBN:
(纸本)9781467350518
Wideband wireless communications base stations could benefit from efficient arithmetic algorithms for cost effective digital baseband computations. Power amplifiers are ubiquitous in such systems and exhibit nonlinearity, causing spectral growth and in-band distortion, which in turn increase error rates. A digital predistorter compensates for nonlinear effects in the power amplifier by transforming the signal with a complex-valued polynomial (linearization). This requires a fast and efficient evaluation scheme for complex polynomials. In this paper, digit-serial techniques for evaluating linearization transformations are presented. Our contributions include algorithmic techniques for increasing throughput and experimental results for FPGAs.
Music genre classification is one of the most important element of the music information retrieval (MIR) community. In this paper, we present a music genre classification system using field programmable gate arrays (F...
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ISBN:
(纸本)9781509067305
Music genre classification is one of the most important element of the music information retrieval (MIR) community. In this paper, we present a music genre classification system using field programmable gate arrays (FPGA) and dedicated DSP processors. The proposed system uses FPGA based acoustic feature extraction of mel frequency cepstral coefficients (MFCC) and dynamic time warping (DTW) based classifier using TMS320C6713 floating point processor. We successfully implemented MFCC extraction algorithm on Spartan 6 FPGA clocked at 150 MHz with support from TMS320C6713 floating point processor followed by DTW based matching engine. The paper attempts to implement music genre classification algorithm in hardware, yielding competitive performance in music information retrieval applications.
Spike generation and routing is typically the most energy-demanding operation in neuromorphic hardware built using spiking neurons. Spiking neural networks running on neuromorphic hardware, however, often use rate-cod...
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ISBN:
(纸本)9781467368537
Spike generation and routing is typically the most energy-demanding operation in neuromorphic hardware built using spiking neurons. Spiking neural networks running on neuromorphic hardware, however, often use rate-coding where the neurons spike rate is treated as the information-carrying quantity. Rate-coding is a highly inefficient coding scheme with minimal information content in each spike, which requires the transmission of a large number of spikes. In this paper, we describe an alternative type of spiking networks based on temporal coding where neuron spiking activity is very sparse and information is encoded in the time of each spike. We implemented the proposed networks on an FPGA platform and we use these sparsely active spiking networks to classify MNIST digits. The network FPGA implementation produces the classification output using only few tens of spikes from the hidden layer, and the classification result is obtained very quickly, typically within 1-3 synaptic time constants. We describe the idealized network dynamics and how these dynamics are adapted to allow an efficient implementation on digital hardware. Our results illustrate the importance of making use of the temporal dynamics in spiking networks in order to maximize the information content of each spike, which ultimately leads to reduced spike counts, improved energy efficiency, and faster response times.
This paper proposes a novel method for performing square root operation on floating-point numbers represented in IEEE-754 single-precision (binary32) format. The method is implemented using Harmonized Parabolic Synthe...
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ISBN:
(纸本)9781728133911
This paper proposes a novel method for performing square root operation on floating-point numbers represented in IEEE-754 single-precision (binary32) format. The method is implemented using Harmonized Parabolic Synthesis. It is implemented with and without pipeline stages individually and synthesized for two different Xilinx FPGA boards. The implementations show better resource usage and latency results when compared to other similar works including Xilinx intellectual property (IP) that uses the CORDIC method. Any method calculating the square root will make approximation errors. Unless these errors are distributed evenly around zero, they can accumulate and give a biased result. An attractive feature of the proposed method is the fact that it distributes the errors evenly around zero, in contrast to CORDIC for instance. Due to the small size, low latency, high throughput, and good error properties, the presented floating-point square root unit is suitable for high performance embedded systems. It can be integrated into a processor's floating point unit or be used as a stand-alone accelerator.
The paper presents hardware efficient design of digital signal processing (DSP) based bit synchronizer and lock detector circuit for bi-phase data. The system is developed for one of the payload of Chandrayaan-1 missi...
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ISBN:
(纸本)9781424424085
The paper presents hardware efficient design of digital signal processing (DSP) based bit synchronizer and lock detector circuit for bi-phase data. The system is developed for one of the payload of Chandrayaan-1 mission, and tested for its performance. Apart from the implementation, paper describes the mathematical modeling of bit synchronizer. The whole design is accommodated in a single Actel-1280 FPGA. A comparison has been carried out between the developed lock detector circuit and the traditional I-2 - Q(2) lock detector and results are presented here. Paper also highlights the programmable nature of the design and methods to reduce the hardware requirement.
In this work, we study the problem of two-encoder multiterminal source coding with side information under logarithmic loss distortion measure. We establish a single-letter characterization of the rate-distortion regio...
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ISBN:
(纸本)9781509040964
In this work, we study the problem of two-encoder multiterminal source coding with side information under logarithmic loss distortion measure. We establish a single-letter characterization of the rate-distortion region of this model in the discrete memoryless case. The proof of the converse relies heavily on that of Courtade-Weissman rate-distortion region of the classic two-encoder multiterminal distributed source coding without side information;and extends it to the case in which the decoder has access to a side information stream that is statistically dependent on the sources that need to be compressed. We also apply our result to the so-called Information Bottleneck Method and establish the optimal tradeoff between complexity and accuracy of the prediction in this setting.
In this paper, we present a timing and frequency synchronization scheme and its FPGA implementation for IEEE 802.11a WLAN systems. In the scheme, an efficient double auto-correlation method based on short training sym...
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ISBN:
(纸本)0769520812
In this paper, we present a timing and frequency synchronization scheme and its FPGA implementation for IEEE 802.11a WLAN systems. In the scheme, an efficient double auto-correlation method based on short training symbols is used for timing synchronization. The performance of the proposed method is comparable or even superior to that of the conventional timing synchronization method under multipath fading channels. By averaging the correlation over four short training symbols, the accuracy of frequency synchronization using short training symbols can be improved to a level that the fine frequency synchronization process using long training symbols in the conventional scheme would not be needed. Thus both timing and frequency synchronization can be achieved using short training symbols alone to reduce computational complexity and overhead. Furthermore, the hardware architecture of the proposed synchronization scheme is developed. The synchronizer is mainly made up of correlator, angle calculator and peak detector, which are implemented by an iterative process, a CORDIC circuit and a finite state machine, respectively. Such an architecture results in low implementation complexity and low computational latency.
This paper proposes an improved time delay digital tanlock loop (TDTL) system in which a feedforward loop is used to initialize the loop filter memory so as to enhance the acquisition speed of the system. The feedforw...
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ISBN:
(纸本)9781467312608
This paper proposes an improved time delay digital tanlock loop (TDTL) system in which a feedforward loop is used to initialize the loop filter memory so as to enhance the acquisition speed of the system. The feedforward loop is used to estimate the value of the steady-state frequency of the input signal which is subsequently loaded into the memory of the loop filter. The system was simulated and tested using Simulink/Matalb using frequency step and FSK modulation. Further, the system was implemented using an FPGA and testing results indicate an ample improvement in the acquisition speed over the original TDTL system.
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