The electrical characteristics of Ti/p-Si Ge contacts with Ti thicknesses of 3nm and 5nm have been investigated in this paper. Ti N was used as a cap layer on Ti. It is observed that as Ti film becomes thinner, Ti/pSi...
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ISBN:
(纸本)9781467397209
The electrical characteristics of Ti/p-Si Ge contacts with Ti thicknesses of 3nm and 5nm have been investigated in this paper. Ti N was used as a cap layer on Ti. It is observed that as Ti film becomes thinner, Ti/pSi Ge contact resistivity(ρ) increases, but its Schottky barrier height(SBH) decreases, which does not coincide with the regular ρc-SBH dependence. Using Ti N/p-Si Ge as a control sample, it is concluded that when Ti film is thinned down to nm scale, the contact property is strongly influenced by Ti N cap layer.
A baseband multi-input, multi-output (MIMO) multi-carrier code division multiple access (MC-CDMA) downlink system meeting wideband CDMA (WCDMA) bandwidth requirements is simulated and its receiver part is implemented ...
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ISBN:
(纸本)9781424477425
A baseband multi-input, multi-output (MIMO) multi-carrier code division multiple access (MC-CDMA) downlink system meeting wideband CDMA (WCDMA) bandwidth requirements is simulated and its receiver part is implemented into a fieldprogrammablegate array (FPGA). The receiver was designed by integrating an existing single-input, single-output (SISO) fixed-point MC-CDMA receiver with an existing floating-point MIMO receiver. The receiver employs temporal multiplexing in order to use a single Vertical Bell Laboratories LAyered Space-Time (V-BLAST) detector. Simulation results of a complete MIMO MC-CDMA system show improvements over the SISO case. Implementation results show that it is possible to implement this receiver design into a single FPGA device.
Node level heterogeneous architectures have become attractive during the last decade for several reasons: Compared to traditional symmetric CPUs, they offer high real-application performance and can be energy and/or c...
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ISBN:
(纸本)9781467303422
Node level heterogeneous architectures have become attractive during the last decade for several reasons: Compared to traditional symmetric CPUs, they offer high real-application performance and can be energy and/or cost efficient. In this paper, we give an overview of the state-of-the-art in heterogeneous computing, focusing on commonly found architectures: The Cell Broadband Engine Architecture (CBEA), NVidia graphics processing units (GPUs), and field programmable gate arrays (FPGAs) accelerators solutions from Maxeler MaxNodes (MAX) and SGI systems (RASC). We present a review of hardware, available software tools for each solution, a quantitative and a qualitative comparison of the architectures, and give our view on the future of heterogeneous computing.
Material characteristics (optical gain/absorption, refractive index change) of GeSn/SiGeSn quantum wells in mid-IR region is theoretically investigated based on many-body theory. The strategies for designing quantum w...
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ISBN:
(纸本)9781509065714
Material characteristics (optical gain/absorption, refractive index change) of GeSn/SiGeSn quantum wells in mid-IR region is theoretically investigated based on many-body theory. The strategies for designing quantum wells having large material gain or absorption under applied electric field are discussed.
Shrinking transistor sizes are jeopardizing the reliability of runtime reconfigurable field programmable gate arrays (FPGAs), making them increasingly sensitive to aging effects such as Negative Bias Temperature Insta...
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ISBN:
(数字)9783981926347
ISBN:
(纸本)9783981926347
Shrinking transistor sizes are jeopardizing the reliability of runtime reconfigurable field programmable gate arrays (FPGAs), making them increasingly sensitive to aging effects such as Negative Bias Temperature Instability (NBTI). This paper introduces a reliability-aware floorplanner which is tailored to multi-context, coarse-grained, runtime reconfigurable architectures (CGRRAs) and seeks to extend their Mean Time to Failure (MTTF) by balancing the usage of processing elements (PEs). The proposed method is based on a Mixed Integer Linear Programming (MILP) formulation, the solution to which produces appropriately-balanced mappings of workload to PEs on the reconfigurable fabric, thereby mitigating aging-induced lifetime degradation. Results demonstrate that, as compared to the default reliability-unaware floorplanning solutions, the proposed method achieves an average MTTF increase of 2.5x without introducing any performance degradation.
In this paper, we consider an adaptive node and power simultaneous scheduling (ANPSS) strategy for target tracking in distributed multiple radar systems. For all of the available nodes, with full resources allocation,...
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ISBN:
(纸本)9780996452700
In this paper, we consider an adaptive node and power simultaneous scheduling (ANPSS) strategy for target tracking in distributed multiple radar systems. For all of the available nodes, with full resources allocation, minimizing estimation mean-square error (MSE) may exceed the predetermined system tracking performance goal and cause unnecessary resources consumption. Therefore, tracking performance driven resource allocation schemes for multiple radar systems are proposed. For a predefined estimation MSE threshold, the total transmitted energy is minimized by optimally scheduling node and power resources with the required tracking accuracy. For a given total power budget, the attainable tracking MSE is minimized by optimizing node and power allocation among the transmit radars. The Bayesian Cramer-Rao lower bound (BCRLB) is used as a performance metric. The resulting optimization problems are solved through Zoutendijk method of feasible directions (ZMFD). Numerical results demonstrate that significant resource savings could be obtained through the proposed schemes.
Exoskeletons have been developed for a wide range of applications, from the military to the medical field, with the aim of augmenting human performance or compensating for neuromuscular deficiencies. However, to empow...
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ISBN:
(纸本)9781538622964
Exoskeletons have been developed for a wide range of applications, from the military to the medical field, with the aim of augmenting human performance or compensating for neuromuscular deficiencies. However, to empower the high number of degrees of freedom of the human body, they often employ a high number of motors, increasing the size, weight and power consumption of the system. We hereby present an actuation strategy to empower our elbow exosuit that adopts a single motor to drive multiple, independently actuated, degrees of freedom. This paradigm, known as One-to-many, is achieved using a modular design where each module comprises a clutchable mechanism that allows to convert a single directional motion from the prime mover to a selectable bidirectional output. Moreover, the mechanism has a locking feature that enables the wearer of the exoskeleton to hold a static load with a minimal power consumption. We present a simple controller for the clutchable unit based on a finite-state machine model, and evaluate its performance for varying input velocities. The system is shown to have a bandwidth of 1.5 Hz, sufficient for daily elbow movements, whilst retaining a compact design.
State-of-the-art local feature descriptors like SIFT or SURF require a significant amount of computational power which prevents their usage in applications with real time constraints. Despite recent efforts to simplif...
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ISBN:
(纸本)9781612844558
State-of-the-art local feature descriptors like SIFT or SURF require a significant amount of computational power which prevents their usage in applications with real time constraints. Despite recent efforts to simplify the calculation of feature descriptors, a faster computation comes often to the disadvantage of weakening the invariance to rotation or scale. Recently, Tola et al. introduced DAISY, a new local feature descriptor for wide-baseline matching across stereo image pairs. It is shown that DAISY outperforms SIFT in terms of matching accuracy while being computed significantly faster. This paper takes on the idea of DAISY by proposing a rotational invariant extension of the descriptor, called O-DAISY, and outlining its implementation on FPGA to achieve real time performance. The results are benchmarked against its original version and against the widely used descriptors BRIEF and SURF on a standardized image set.
We introduce fibred type-theoretic fibration categories which are fibred categories between categorical models of Martin-L of type theory. Fibred type- theoretic fibration categories give a categorical description of ...
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ISBN:
(纸本)9781509030187
We introduce fibred type-theoretic fibration categories which are fibred categories between categorical models of Martin-L of type theory. Fibred type- theoretic fibration categories give a categorical description of logical predicates for identity types. As an application, we show a relational parametricity result for homotopy type theory. As a corollary, it follows that every closed term of type of polymorphic endofunctions on a loop space is homotopic to some iterated concatenation of a loop.
In the paper we present generic hardware verification structures for efficient testing of the custom processor cores in FPGA devices. Hardware verification environment consists of hardware debug structures: control ma...
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ISBN:
(纸本)9789532330816
In the paper we present generic hardware verification structures for efficient testing of the custom processor cores in FPGA devices. Hardware verification environment consists of hardware debug structures: control machine, memory access port, input and output data buffers and interface logic. The verification structures are integrated and synthesized with the processor core under test and implemented on the FPGA device. The structures can be customized and easily integrated in the hardware development flow. A software support for the hardware verification consists of a data acquisition driver running on the server with HTML5 graphical interface. The software enables either local testing or setup of a remote laboratory for testing of the processor cores. The application of the remote laboratory in the educational process is presented. The presented hardware verification structures are optimized for testing the soft programmable processor cores and are vendor independent. The software support is based on open languages and protocols and the scripting tools enable quick customization. We present advantages of our solution compared to commercial general purpose on-chip logical analyzers. The benefit of our approach is that it can be used with the standard programmable design tools on the low cost platforms and provides two abstraction levels of debugging.
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