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检索条件"主题词=Field Programmable Gate Arrays"

共 41416 条记录，以下是4971-4980 订阅

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circFA: a FPGA-based circular RNA aligner

circFA: a FPGA-based circular RNA aligner

引用

IEEE EMBS International Conference on Biomedical and Health Informatics (BHI)

作者： Zeni, Alberto Peverelli, Francesco Cabri, Enrico Di Tucci, Lorenzo Cerina, Luca Santambrogio, Marco D. Politecn Milan Dipartimento Elettron Informaz & Bioingn Milan Italy

ISBN: (纸本)9781728108483

Circular RNAs (CircRNAs) are a widespread form of Non-Coding RNAs (ncRNAs). Although circular RNAs have been known for a long time, it is only recently that their therapeutic implications are being investigated. Research has shown that they are suitable candidates to be genetic biomarkers for different types of cancer since they are implied in Carcinogenesis. However, their identification involves a computationally intensive and very long process. This represents a serious obstacle to their ability to provide a fast and accurate life-saving diagnosis. Here we present Circular RNA FPGA Aligner (circFa), a hardware implementation of an alignment algorithm designed for the circular RNAs identification protocol. Our solution aims to reduce diagnosis time and produces a pharmacological therapy tailored to the specific patient using his genetic information. CircFA implements the same scalable version of the Smith-Waterman (SW) algorithm with affine gaps employed by Bowtie2, a state of the art tool for sequence alignment, on field programmable gate Array (FPGA). Our design shows a speedup over the software version of SW of 8.8x, and a speedup of 1.95x over a parallelized multicore version of the same software. Our architecture also shows a significant increase in power efficiency with an increase of 80.96x and 17.96x with respect to the single core and multicore software respectively.

关键词： Computer architecture Kernel Hardware field programmable gate arrays Software algorithms RNA

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A Trigger System Based on Fast Sampling ADCs - Implementation and Tests

A Trigger System Based on Fast Sampling ADCs - Implementatio...

引用

IEEE Nuclear Science Symposium/Medical Imaging Conference (NSS/MIC)/18th International Workshop on Room-Temperature Semiconductor X-Ray and Gamma-Ray Detectors

作者： Marciniewski, P. Plucinski, P. Fransson, K. Heijkenskojld, L. Kupsc, A. Zlomanczuk, J. Wolke, M. Calen, H. Johansson, T. Hoistad, B. Erven, W. Wuestner, P. Kleines, H. Hejny, V. Coderre, D. Uppsala Univ Inst Phys & Astron Uppsala Sweden Forschungszentrum Juelich Cent Inst Elect Julich Germany Forschungszentrum Juelich Inst Nucl Phys Julich Germany

ISBN: (纸本)9781467301206

A Trigger System for a multi-detector setup is presented. The system takes advantage of the newly developed continuous-sampling 16-channel, 12-bit, 160-Msps ADC modules. The ADCs are equipped with programmable logic (FPGA) and perform on-line digital "charge" integration, resolve pile-ups and compute arrival times of detector signals with an accuracy of 1.5 ns. A fast trigger data lane connects the ADC units to a Trigger Module using optical links. Each Trigger Module features 16 optical interfaces (SFP) running at 2 Gb/s input data rate and can be used for evaluating trigger decisions or as a DAQ unit. The Trigger system was implemented in the WASA@COSY experiment, performing on-line event reconstruction, including complex detector calibration, delivering triggers based on multiplicity of tracks fulfilling deposited energy, scattering angle and Delta E/E criteria. Depending on the trigger algorithm used, the trigger latency measured from the actual detector signal to the trigger output amounts to 1.3 - 1.5 mu s.

关键词： Boolean functions DAQ system Data structures Europe FPGA Optical devices Optical fiber communication analogue-digital conversion calibration complex detector calibration continuous-sampling ADC module data acquisition fast sampling ADC system fast trigger data lane field programmable gate arrays high energy physics instrumentation computing input data rate multidetector setup nuclear electronics on-line digital charge integration process on-line event reconstruction method optical links plastic scintillator detector solid scintillation detectors time 1.5 ns trigger algorithm trigger circuits trigger system

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Stability Analysis of the Slip Mode Frequency Shift Islanding Detection in Single Phase PV Inverters 26

Stability Analysis of the Slip Mode Frequency Shift Islandin...

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26th IEEE International Symposium on Industrial Electronics (ISIE)

作者： Mohammadpour, Bahador Zareie, Milad Eren, Suzan Pahlevani, Majid Solantro Semicond Corp Ottawa ON Canada Queens Univ ECE Dept Kingston ON Canada Univ Calgary ECE Dept Calgary AB Canada

ISBN: (纸本)9781509014125

This paper presents the stability analysis of the slip mode frequency shift (SMS) islanding detection technique. The developed mathematical model is based on the precise dynamical equations of the closed-loop control system for a grid-connected inverter. In particular, singular perturbation theory is used to divide the closed-loop dynamics into subsections with different rates of change. It is proven that this system complies with the mathematical conditions of the singular perturbation theory, and then the system stability analyzed accordingly. Also, the stability analysis has been performed for two modes of operation: the grid-connected mode and the islanded mode. Experimental results are presented to validate the analysis.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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"Chameleon" software defined control platform

引用

11th International Conference on Computer Aided Systems Theory

作者： Handzlik, Adam Jablonski, Andrzej Microtech Int Ltd Fabryczna Fabryczna 13 Str PL-53609 Wroclaw Poland Wroclaw Univ Technol Fac Elect PL-50370 Wroclaw Poland

ISBN: (纸本)9783540758662

This paper presents a basic concept, development and implementation of software tool designated for programming of field programmable gate arrays. However, the programming scheme does not employ typical VHDL or Verilog languages but dedicated PLC-like software environment producing both execution code and hardware configuration for the for FPCA chip. As a result the project has created PLC language defined control system implemented in an FPGA structure. Verification tests were performed on Xilinx Spartan II platform and finally were converted into Spartan III chip family. Although verification tests were run using development boards the real life embedded application is now developed.

关键词： signal processing architectures control platform development innovative reprogrammable technology field programmable gate arrays IP core virtual programmable Logic Controller

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Renovate High Performance User-level Stacks' Innovation Utilizing Commodity Network Adaptors

Renovate High Performance User-level Stacks' Innovation Util...

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IEEE Symposium on Computers and Communications (ISCC)

作者： Miao, Mao Luo, Xiaohui Ren, Fengyuan Cheng, Wenxue Xie, Jing Li, Wenzhuo Liu, Xiaolan Tsinghua Univ Dept Comp Sci & Technol Natl Lab Informat Sci & Technol Beijing Peoples R China

ISBN: (纸本)9781538616291

Today's data center servers are equipped with high speed and complex network adaptors, featuring an array of functions, e.g. hardware TX/RX queues, packet filters, rate limiters, etc. Recent work like IX, Arrakis, MultiStack has made us rekindle the user-level network stacks' innovation utilizing these commodity network adaptors. In this paper, we revisit the idea to move stacks' design from in-kernel shared space into user-level application-specific dedicated one, for high performance and ease of development and deployment. We provide an unified control plane TAPM to exploit and manage the hardware adaptors' resources, and a dedicated data plane hwTAP to support different user-level stacks. TAPM and hwTAP highlight the utilization of hardware features from commodity network adaptors, to support the innovation of different user-level stacks. Experiments show that the hardware switching module can keep the input rate without any overheads and costs. TAPM could configure the hwTAP dynamically. Our run-to-completion user-level stack also achieves high throughput and low latency.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A Nine-context programmable Optically Reconfigurable gate Array with Semiconductor Lasers

A Nine-context Programmable Optically Reconfigurable Gate Ar...

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19th Great Lakes Symposium on VLSI 2009

作者： Kubota, Shinya Watanabe, Minoru Shizuoka Univ Hamamatsu Shizuoka 4328561 Japan

ISBN: (纸本)9781605585222

Recently, optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser array, have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSIs. Consequently, ORGAs with more than tera-gate capacity will be realized by exploiting the storage capacity of a holographic memory. However, compared with current field programmable gate arrays (FPGAs), conventional ORGAs have an important shortcoming: they are not reprogrammable after fabrication because, to reprogram ORGAs, a holographic memory must be disassembled from its ORGA package, reprogrammed outside of the ORGA package using a holographic memory writer, and then implemented onto the ORGA package with high precision beyond the capability of manual assembly. To remove that daunting problem, this paper presents a nine-context programmable ORGA and its writer. Furthermore, this paper presents discussion of the availability of this architecture and future plans based on experimental results.

关键词： field programmable gate arrays Holographic memory Optically reconfigurable gate arrays

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Performance Improvement of a Laser Cladding System through FPGA-Based Control

Performance Improvement of a Laser Cladding System through F...

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ICELIE/IES Industry Forum/37th Annual Conference of the IEEE Industrial-Electronics-Society (IECON)

作者： Colodron, Pablo Farina, Jose Rodriguez-Andina, Juan J. Vidal, Felix Mato, Jose L. Angeles Montealegre, Ma Univ Vigo Dept Elect Technol Vigo 36310 Spain AIMEN Technol Ctr Porrino Spain

ISBN: (纸本)9781612849720

Laser cladding is a material processing technique widely used in industry for part reconstruction, coating or rapid prototyping, among other fields. Although it is sometimes applied as an open-loop technique, closed-loop control is mandatory in applications where homogeneous results are required, because the type, size, and geometry of the part being treated influence the process. The inherent non-repetitiveness of the technique makes it necessary a control of process parameters, such as laser power, fast and accurate enough according to the features of the melt pool. In a previous work, an FPGA-based measurement system was proposed to efficiently monitor the laser cladding process. This paper reports on the extension of that system to implement an enhanced control of the process, which allows the limitations of the PC-based solutions being currently used in industry to be overcome. Experimental results obtained in an industrial part reconstruction system using different part dimensions are presented, demonstrating the performance improvement achieved with regard to existing systems. The proposed solution can be applied to the treatment of small parts or complex geometries, for which the performance of PC-based systems is not good enough.

关键词： Cameras Control systems field programmable gate arrays Laser beams Measurement by laser beam Powders Power lasers

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MoS₂ Negative Capacitance FETs with CMOS-Compatible Hafnium Zirconium Oxide 75

MoS<sub>2</sub> Negative Capacitance FETs with CMOS-Compatib...

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75th Annual Device Research Conference (DRC)

作者： McGuire, Felicia A. Lin, Yuh-Chen Rayner, Bruce Franklin, Aaron D. Duke Univ Dept Elect & Comp Engn Durham NC 27708 USA Kurt J Lesker Co Pittsburgh PA 15025 USA Duke Univ Dept Chem Durham NC 27708 USA

ISBN: (纸本)9781509063284

The attractiveness of negative capacitance field-effect transistors (NC-FETs) stems from their ability to enable a subthreshold swing (SS) below the 60 mV/decade thermal limit at room temperature - a direct effect of the step-up voltage amplifier behavior of the ferroelectric [1]. This effect has been shown to yield sub-60 mV/dec SS in several Si-based NC-FETs [2-4]; however, as Si-based devices become increasingly difficult to scale, it is pertinent to explore alternative materials for NC-FETs that offer scalability in voltage as well as size [5]. One promising alternative channel material is the 2D transition metal dichalcogenide (TMD, such as MoS₂), which offer sub-nm thinness and a more stable channel capacitance that, when coupled with the NC-effect, could produce steep switching over a broad range of current. To date, the only demonstration of an NC-FET with a 2D channel used a polymeric ferroelectric, resulting in a lack of stability and CMOS-compatibility despite superb low-voltage switching [6]. In this work, we demonstrate 2D NC-FETs using MoS₂ with CMOS-compatible hafnium zirconium oxide (HfZrO₂ or HZO) as the ferroelectric to achieve repeatable and sustained sub-60 mV/dec switching.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A Scalable and Compact Systolic Architecture for Linear Solvers

A Scalable and Compact Systolic Architecture for Linear Solv...

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IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Ong, Kevin S. H. Fahmy, Suhaib A. Ling, Keck-Voon Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore

ISBN: (纸本)9781479936090

We present a scalable design for accelerating the problem of solving a dense linear system of equations using LU Decomposition. A novel systolic array architecture that can be used as a building block in scientific applications is described and prototyped on a Xilinx Virtex 6 FPGA. This solver has a throughput of around 3.2 million linear systems per second for matrices of size N= 4 and around 80 thousand linear systems per second for matrices of size N= 16. In comparison with similar work, our design offers up to a 12-fold improvement in speed whilst requiring up to 50% less hardware resources. As a result, a linear system of size N= 64 can be implemented on a single FPGA, whereas previous work was limited to a size of N= 12 and resorted to complex multi-FPGA architectures to scale. Finally, the scalable design can be adapted to different sized problems with minimum effort.

关键词： Linear system Scalability matrices Solvers ARCHITECTURE Linear system of equations Building construction field programmable gate arrays Throughput array structure

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Spread, then Target, and Advertise in Waves: Optimal Capital Allocation Across Advertising Channels

Spread, then Target, and Advertise in Waves: Optimal Capital...

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Information Theory and Applications Workshop (ITA)

作者： Eshghi, Soheil Preciado, Victor M. Sarkar, Saswati Venkatesh, Santosh S. Zhao, Qing D'Souza, Raissa Swami, Ananthram Yale Univ Sch Elect Engn New Haven CT 06520 USA Yale Univ YINS New Haven CT 06520 USA Univ Penn Sch Elect & Syst Engn Philadelphia PA 19104 USA Cornell Univ Sch Elect & Comp Engn Ithaca NY 14853 USA Univ Calif Davis Dept Comp Sci Davis CA 95616 USA Univ Calif Davis Dept Mech & Aerosp Engn Davis CA 95616 USA Army Res Lab Adelphi MD 20783 USA

ISBN: (纸本)9781509052936

We obtain optimal strategies for the allocation of influence budget across multiple channels and across time for an external influencer, e.g., a political campaign, seeking to maximize its effect on an election given a network of agents with linear consensus-seeking opinion dynamics. We show that for a general set of objective functions, the optimal influence strategy at every time uses all channels at either their maximum rate or not at all. Furthermore, we prove that the number of switches between these extremes is bounded above both by a term that is typically much smaller than the number of agents. This means that the optimal influence strategy is to exert maximum effort in waves for every channel, and then cease effort and let the effects propagate. We also show that at the beginning, the total cost-adjusted reach of a channel determines its relative value, while targeting matters more closer to election time. We demonstrate that the optimal influence structures are easily computable in several practical cases. We explicitly characterize the optimal controls for the case of linear objective functions via a closed form. Finally, we see that in the canonical election example, identifying late-deciders approximately determines the optimal campaign resource allocation strategy.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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