A high-speed architecture for bit serial modular multiplication is presented. The design of this array is highly regular, allowing the specific logic and routing resources available in field programmable gate arrays (...
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A high-speed architecture for bit serial modular multiplication is presented. The design of this array is highly regular, allowing the specific logic and routing resources available in field programmable gate arrays (FPGAs) to be exploited. Furthermore, an optimised array is presented which exploits the reprogrammability of the FPGA, such that a longer bit length can be implemented on the same FPGA.
field programmable gate arrays (FPGA) with antifuse elements are preferred in aerospace applications due to their non-volatility and demonstrated radiation hardness. Because aerospace applications typically involve lo...
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field programmable gate arrays (FPGA) with antifuse elements are preferred in aerospace applications due to their non-volatility and demonstrated radiation hardness. Because aerospace applications typically involve long operating life, there is a requirement to store un-programmed antifuse FPGA parts for long periods and program them when necessary to support the system. No study on the long term reliability of un-programmed antifuse FPGAs in the storage environment is reported in literature. In this paper, antifuse structures, programming process, and failure mechanisms of antifuse FPGAs are discussed. A failure modes, mechanisms and effects (FMMEA) analysis was performed for storage conditions and critical failure mechanisms were identified. High temperature storage tests of a select number of antifuse FPGAs were performed to accelerate the identified failure mechanisms. These parts were subsequently programmed and yield data was analyzed to determine the effects of high temperature storage. (C) 2013 Elsevier Ltd. All rights reserved.
This letter describes a CAD system for automatic implementation of FIR filters on Xilinx field programmable gate arrays (FPGA). Given the frequency specifications, this software package designs an FIR filter, optimize...
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This letter describes a CAD system for automatic implementation of FIR filters on Xilinx field programmable gate arrays (FPGA). Given the frequency specifications, this software package designs an FIR filter, optimizes the filter coefficients in the power of two coefficient space, and implements it on FPGA chips. The FPGA specific mapping techniques used to increase speed are discussed. The performance of the typical filters that were implemented is presented.
Number plate (NP) binarization and adjustment are important preprocessing stages in automatic number plate recognition (ANPR) systems and are used to link the number plate localization (NPL) and character segmentation...
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Number plate (NP) binarization and adjustment are important preprocessing stages in automatic number plate recognition (ANPR) systems and are used to link the number plate localization (NPL) and character segmentation stages. Successfully linking these two stages will improve the performance of the entire ANPR system. We present two optimized low-complexity NP binarization and adjustment algorithms. Efficient area/speed architectures based on the proposed algorithms are also presented and have been successfully implemented and tested using the Mentor Graphics RC240 FPGA development board, which together require only 9% of the available on-chip resources of a Virtex-4 FPGA, run with a maximum frequency of 95.8 MHz and are capable of processing one image in 0.07 to 0.17 ms. (C) 2013 SPIE and IS&T [DOI: 10.1117/***.22.1.013009]
In this work, we demonstrate the use of a fieldprogrammablegate Array (FPGA) as a physical platform for realizing chaotic delay differential equations (DDE). Moreover, using our platform, we also experimentally stud...
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In this work, we demonstrate the use of a fieldprogrammablegate Array (FPGA) as a physical platform for realizing chaotic delay differential equations (DDE). Moreover, using our platform, we also experimentally study the synchronization between two time delayed systems. We illustrate two different experimental approaches - one is hardware co-simulation (using a Digilent Atlys with a Xilinx Spartan-6 FPGA) and the other is analog output (using a Terasic DE-2115 with an Altera Cyclone IV E FPGA).
This paper discusses the future of field programmable gate arrays (FPGA) from the viewpoint of Ivo Bolsens, chief technology officer at Xilinx. Bolsens believes that the best design features for dealing with the effec...
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This paper discusses the future of field programmable gate arrays (FPGA) from the viewpoint of Ivo Bolsens, chief technology officer at Xilinx. Bolsens believes that the best design features for dealing with the effects of Moore's Law and submicron devices are all in FPGAs. These devices also have a number of built-in advantages when it comes to programmability. Inherent parallelism keeps clock rate down in the MHz range, and transistor counts can be contained by dynamically reconfiguring parts of a circuit. To address the issue of Moore's Law in FPGA design, Bolsens thinks the answer lies in moving up the abstraction level and exploiting FPGA's inherent reprogrammability to simplify the whole design experience.
An R phi trigger was developed using the eight doublet layers of axial fibers in the new Central Fiber Tracker for the DO Upgrade Detector at Fermilab [1]. This trigger must be formed in less than 500 nsec and distrib...
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An R phi trigger was developed using the eight doublet layers of axial fibers in the new Central Fiber Tracker for the DO Upgrade Detector at Fermilab [1]. This trigger must be formed in less than 500 nsec and distributed to other parts of the detector for a level 1 trigger decision. The high speed is achieved by using massively parallel AND/OR logic realized in state-of-the-art field programmable gate arrays, FPGAs. The programmability of the FPGAs allows corrections to the track roads for the as-built detector and for dynamically changing the transverse momentum threshold. To reduce the number of fake tracks at high luminosity, the narrowest possible roads must be used which pushes the total number of roads into the thousands. Monte Carlo simulations of the track trigger were run to develop the trigger algorithms and a vendor specific commercially available simulator was used to develop and test the FPGA programming.
Reliability and precision are very important in space, medical, and industrial robot control applications. Recently, researchers have tried to increase the reliability and precision of the robot control implementation...
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Reliability and precision are very important in space, medical, and industrial robot control applications. Recently, researchers have tried to increase the reliability and precision of the robot control implementations. High precision calculation of inverse kinematic color based object recognition, and parallel robot control based on field programmable gate arrays (FPGA) are combined in the proposed system. The precision of the inverse kinematic solution is improved using the coordinate rotation digital computer (CORDIC) algorithm based on double precision floating point number format. Red, green, and blue (RGB) color space is converted to hue saturation value (HSV) color space, which is more convenient for recognizing the object in different illuminations. Moreover, to realize a smooth operation of the robot arm, a parallel pulse width modulation (PWM) generator is designed. All applications are simulated, synthesized, and loaded in a single FPGA chip, so that the reliability requirement is met. The proposed method was tested with different objects, and the results prove that the proposed inverse kinematic calculations have high precision and the color based object recognition is quite successful in finding coordinates of the objects.
Three-dimensional mixed-mode device simulation is used to investigate the dock upset in an antifuse FPGA device. Two versions of the clock circuit were simulated, the original and the redesigned,vith improved SEU hard...
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Three-dimensional mixed-mode device simulation is used to investigate the dock upset in an antifuse FPGA device. Two versions of the clock circuit were simulated, the original and the redesigned,vith improved SEU hardness, The threshold LET of each version was simulated both at static and during transition. Compared to the test data, the simulated results consistently underestimate the LETth. The difference between LETth at static and during transition is relatively small. This disagrees with the previous speculation that the clock upset is due to heavy-ion strikes very close to the clock edge. Efforts were also made to optimize the simulation methodology to reduce the simulation time for practicality.
New fast and highly complex 'field programmable gate arrays' allow the design of sophisticated decision logic within the trigger latency time of Particle Detectors. As an example we show the Jet Determination ...
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ISBN:
(纸本)076950843X
New fast and highly complex 'field programmable gate arrays' allow the design of sophisticated decision logic within the trigger latency time of Particle Detectors. As an example we show the Jet Determination of the Hera-H1 detector at DESY (Deutsches Elektronen Synchrotron) Hamburg. It has to calculate all existing localized energy depositions (jets) in the calorimeter and deliver the result, sorted according to energy. The system is implemented by a network of three times 440 high density FPGA's which have to deliver the results in less than 1 mus. The computing power of the system is equivalent to 70 Billion operations per second.
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