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FPGA Acceleration With Hessian-Based Comprehensive Intra-Layer Mixed-Precision Quantization for Transformer Models

IEEE ACCESS 2025年 13卷 70282-70297页

作者： Byun, Woohong Woo, Jongseok Mukhopadhyay, Saibal Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA Samsung Display Co Ltd Mobile Display Design Team Yongin 17096 South Korea

Recent advancements in using FPGAs as co-processors for language model acceleration, particularly for energy efficiency and flexibility, face challenges due to limited memory capacity. This limitation hinders the deployment of transformer-based language models. To address this challenge, we propose a novel software-hardware co-optimization framework that integrates Hessian-based intra-layer mixed-precision quantization with a runtime bit-configurable FPGA accelerator. Our proposed Hessian-based row-wise weight quantization addresses hardware inefficiencies in traditional parameter-wise and channel-wise approaches by enabling mixed-precision weight matrices to be split into two uniform-precision matrices, thereby simplifying hardware requirements. Additionally, our Query-Key coupled attention activation quantization optimally aligns precision within each outer product pair in attention calculations, reducing hardware complexity and memory management overhead. Our concurrent quantization method balances the benefits of row-wise weight quantization and Query-Key coupled activation quantization while maximizing energy efficiency through multi-precision optimization. To support this algorithm, we design a multi-precision FPGA accelerator capable of handling both 2(n)-based and non-2(n) mixed-precision operations. It is implemented on a single Xilinx ZCU102 FPGA board, operating at 200MHz with a power consumption of 15.08W during inference on the 110-million-parameter BERT-Base and 345-million-parameter GPT-2 Medium transformer models. Coupled with the proposed algorithm and dataflow optimization, it enables on-chip storage of all necessary parameters, minimizing off-chip memory access. Experimental results demonstrate that our FPGA accelerator significantly outperforms existing solutions, achieving energy efficiency improvements ranging from 2.22 x to 17.23 x over state-of-the-art FPGA accelerators.

关键词： Quantization (signal) Hardware field programmable gate arrays Transformers Energy efficiency Optimization Memory management Computational modeling Accuracy Sparse matrices Accelerator activation BERT FPGA hardware acceleration Hessian language model mixed-precision NLP quantization transformer

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A Tracking-Based High-Speed Demodulation Method for Fiber Bragg Grating Sensing System Based on Wavelength-Tunable Laser in Space Application

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷

作者： Zhu, Yunhong Wang, Le Wang, Du Dong, Mingli Lou, Xiaoping Zhu, Lianqing Beijing Informat Sci & Technol Univ Key Lab Minist Educ Optoelect Measurement Technol Beijing 100016 Peoples R China Guangzhou Nansha Intelligent Photon Sensing Res In Guangzhou 511462 Peoples R China Beijing Informat Sci & Technol Univ Beijing Lab Opt Fiber Sensing & Syst Beijing 100016 Peoples R China Beijing Univ Technol Sch Mech & Energy Engn Beijing 100124 Peoples R China

The vibration measurement of spacecraft structures in space applications has raised higher requirements for the demodulation frequency of the fiber Bragg grating (FBG) demodulator. In this article, a tracking-based high-speed demodulation method for FBG sensing systems based on the wavelength-tunable laser is proposed. The wavelength-tunable laser only scans wavelengths near the latest wavelength of each FBG sensor. The scanning range is constantly updated to achieve wavelength tracking, and the FBG demodulator continuously outputs the center wavelengths of the FBG sensors. The influence of multiple parameters on the demodulation frequency is simulated for the traditional full wavelength range scanning demodulation method and the proposed method. An FBG sensing system for measuring vibration was established. The demodulation frequencies are 14 and 560 Hz when using these two methods, which coincide with the simulation results. The FBG sensing system can accurately measure vibration frequency below 200 Hz with a maximum error of 0.528 Hz. Thus, the proposed method significantly increases the demodulation frequency by 40 times compared to the traditional method and provides an effective approach to achieve high-speed demodulation of the FBG demodulator.

关键词： Demodulation Fiber gratings Lasers Sensors Reflection Fiber lasers field programmable gate arrays Wavelength measurement Vibration measurement Measurement by laser beam Demodulation frequency demodulation method fiber Bragg gratings (FBGs) tracking-based demodulation wavelength-tunable laser

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FPGA implementation of low complexity super resolution scaling architecture for UHD display systems

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INTERNATIONAL JOURNAL OF ENGINEERING SYSTEMS MODELLING AND SIMULATION 2025年第2期16卷 63-75页

作者： Janardhan, Chidadala Ramanaiah, K. Venkata Babulu, K. Jawaharlal Nehru Technol Univ Kakinada Dept Elect & Commun Engn Kakinada 533003 Andhra Prades India Yogivemana Univ YSR Engn Coll Dept Elect & Commun Engn Proddatur 516361 Andhra Prades India Jawaharlal Nehru Technol Univ Gurajada Dept Elect & Commun Engn Vizianagaram 535003 Andhra Prades India

Ultra high definition (UHD) technology has been changing the entertainment industry significantly and its content is severely short of supply due to limited content creators or hard to access due to insufficient network bandwidth. Recent improvements in CMOS image sensor technology, multimedia applications traditional standard display (SD) systems are not sufficient to display high-quality images. Conventional FPGA-based SR methods will exhibit more complexity and requires more hardware resources to perform. This paper describes low complexity super resolution scaling architecture (SRSA) for UHD systems. In our proposed method, bi-cubic interpolation is used for reconstruction the low-frequency image to high-frequency images, these bi-cubic interpolations will have the capability to interpolate 16 nearest neighbours of a pixel. In addition to that high-frequency patches are overlapped to construct super resolutions images with using kernel algorithm. The proposed system generates the output image at 1,600 x 1,600 sizes from 800 x 800 image size. The proposed SRSA super-resolution technique is modelled in Verilog HDL and synthesised in Xilinx Zynq-7000 series FPGA and shown the comparison of area, delay, and power. From the simulation results, the performance of the proposed method can compete over the state of the art methods.

关键词： image interpolation super resolution image resolution field programmable gate arrays image restoration

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FPGA-Accelerated YOLOX With Enhanced Attention Mechanisms for Real-Time Wildfire Detection on AAVs

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷

作者： Elhence, Anubhav Panda, Anubhav Chamola, Vinay Sikdar, Biplab BITS Pilani Dept Elect & Elect Engn Pilani 333031 India BITS Pilani APPCAIR Pilani 333031 India Natl Univ Singapore NUS Dept Elect & Commun Engn Singapore 119077 Singapore

Real-time wildfire detection is crucial for enabling prompt intervention and minimizing environmental and economic damages;however, deploying high-accuracy detection models on resource-constrained platforms such as autonomous aerial vehicles (AAVs) presents significant challenges due to limitations in computational capacity and power availability. In this article, we propose layerwise channel attention module (LCAM)-YOLOX, an enhanced object detection framework that integrates an LCAM into the YOLOX architecture to improve detection accuracy while maintaining computational efficiency. The model is optimized for deployment on FPGA platforms through 8-bit integer quantization, facilitating efficient inference on devices with limited resources. We implement and evaluate the LCAM-YOLOX model on the Xilinx Kria KV260 FPGA platform, demonstrating that it achieves a quantized mean average precision (mAP) of 78.11%, outperforming other state-of-the-art models such as YOLOv3, YOLOv5, and YOLOX-m. Moreover, the LCAM-YOLOX model processes at 195 frames per second (FPS) using a single DPU core on the KV260, exceeding real-time processing requirements while consuming only 10.45 W of power, which translates to the highest performance per watt ratio among the tested platforms. These results highlight the suitability of the KV260 FPGA as an optimal choice for deploying high-performance, energy-efficient wildfire detection models on AAVs, enabling real-time monitoring in resource-constrained environments.

关键词： Wildfires Computational modeling Feature extraction Real-time systems field programmable gate arrays Autonomous aerial vehicles Accuracy Biological system modeling Quantization (signal) Computer architecture Aerial robotics computer vision for other robotic applications energy and environment-aware automation field robots hardware-software co-design intelligent transportation systems quantized neural networks

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Dynamic Tsetlin Machine Accelerators for On-Chip Training Using FPGAs

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Mao, Gang Rahman, Tousif Maheshwari, Sidharth Pattison, Bob Shao, Zhuang Shafik, Rishad Yakovlev, Alex Newcastle Univ Sch Engn Microsyst Res Grp Newcastle Upon Tyne NE1 7RU England IIT Jammu Jammu 181221 Jammu & Kashmir India

The increased demand for data privacy and security in machine learning (ML) applications has put impetus on effective edge training on Internet-of-Things (IoT) nodes. Edge training aims to leverage speed, energy efficiency and adaptability within the resource constraints of the nodes. Deploying and training Deep Neural Networks (DNNs)-based models at the edge, although accurate, posit significant challenges from the back-propagation algorithm's complexity, bit precision trade-offs, and heterogeneity of DNN layers. This paper presents a Dynamic Tsetlin Machine (DTM) training accelerator as an alternative to DNN implementations. DTM utilizes logic-based on-chip inference with finite-state automata-driven learning within the same field programmable gate Array (FPGA) package. Underpinned on the Vanilla and Coalesced Tsetlin Machine algorithms, the dynamic aspect of the accelerator design allows for a run-time reconfiguration targeting different datasets, model architectures, and model sizes without resynthesis. This makes the DTM suitable for targeting multivariate sensor-based edge tasks. Compared to DNNs, DTM trains with fewer multiply-accumulates, devoid of derivative computation. It is a data-centric ML algorithm that learns by aligning Tsetlin automata with input data to form logical propositions enabling efficient Look-up-Table (LUT) mapping and frugal Block RAM usage in FPGA training implementations. The proposed accelerator offers 2.54x more Giga operations per second per Watt (GOP/s per W) and uses 6x less power than the next-best comparable design.

关键词： Training field programmable gate arrays Inference algorithms Heuristic algorithms Hardware Artificial neural networks Computer architecture Learning automata Computational modeling System-on-chip Edge training coalesced tsetlin machines dynamic tsetlin machines embedded FPGA machine learning accelerator on-chip learning logic-based-learning

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TYLOR: TDC-Based Low-Overhead Synthesizable Power SCA Countermeasure on FPGAs

IEEE DESIGN & TEST

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IEEE DESIGN & TEST 2025年第3期42卷 94-102页

作者： Titti, Samarth Shivakumar Saurabh, Harshit Das, Debayan Indian Inst Sci Bengaluru 560012 India

Editor's notes: Side-channel attacks enable an adversary to retrieve secret key from a cryptographic hardware through statistical analysis of physical parameters, such as power. This article presents a low-cost robust defense against this attack using a novel power compensation mechanism. -Swarup Bhunia, University of Florida, USA

关键词： field programmable gate arrays Security Power demand Clocks Integrated circuit modeling Hardware design languages Fluctuations Voltage fluctuations Logic gates Logic Side-Channel Attacks (SCA) Correlational Power Attack (CPA) field programmable gate arrays (FPGA) Circuit Level Countermeasures

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A Logic Circuit-Based Intrusion Detection System Using a Dendritic Neural Model Ensemble

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IEEE COMPUTATIONAL INTELLIGENCE MAGAZINE 2025年第2期20卷 20-32页

作者： Ji, Junkai Jin, Haochang Zhao, Jiajun Lin, Qiuzhen Li, Jianqiang Zhu, Zexuan Shenzhen Univ Shenzhen 518060 Peoples R China

An intrusion detection system (IDS) plays a crucial role in network security by distinguishing hostile activities from network traffic. Conventional hardware-based IDS architectures have high throughput and low energy consumption but suffer from poor detection accuracy. By contrast, software-based systems using machine learning and deep learning techniques can significantly improve detection accuracy. Nevertheless, owing to the implementation requirements of von Neumann computer architectures, their long inference time makes them unsuitable for application to large networks and high-bandwidth connections. To address this issue, this study proposes a novel dendritic neural model ensemble for intrusion detection. A logic circuit-based IDS is designed based on mutual information-based feature selection and ensemble learning algorithms. The IDS consists of logic gates, comparators, shift registers, and accumulators and was successfully implemented in a field programmable gate array (FPGA) device. Experimental results reveal that the proposed IDS shows both higher detection accuracy and higher detection speed than the state-of-the-art detection methods on two modern intrusion detection datasets. Therefore, it can be regarded as a powerful and efficient IDS in practical applications. The source code is available at https://***/DNM/.

关键词： Accuracy Computational modeling Intrusion detection Computer architecture Logic gates Throughput Shift registers Logic Integrated circuit modeling field programmable gate arrays

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Enhancing Wireless PHY With Adaptive OFDM and Multiarmed Bandit Learning on Zynq System-on-Chip

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第6期33卷 1651-1664页

作者： Singh, Neelam Darak, Sumit J. IIIT Delhi Algorithms Architecture Lab New Delhi 110020 India IIIT Delhi Dept Elect & Commun New Delhi 110020 India

In this work, we present an intelligent and reconfigurable wireless physical layer (PHY) that dynamically adjusts the transmission parameters for a given radio frequency (RF) environment. The proposed PHY is based on orthogonal frequency division multiplexing (OFDM) and can dynamically augment OFDM with a finite impulse response (FIR) low-pass filter to improve the out-of-band emissions (OOBE). To make these adaptations intelligently, we employ multiarmed bandit (MAB)-based online learning algorithms, specifically upper confidence bound with control variate (UCB-CV). UCB-CV enhances traditional UCB by incorporating additional information such as interference level and transmit power, allowing it to manage interference more effectively. These algorithms are integrated into the PHY of an FPGA-based OFDM transceiver on the Zynq system-on-chip (SoC), facilitating real-time decision-making based on side-channel interference and other parameters. Our comparative analysis highlights the enhanced performance of the UCB-CV algorithm over the traditional UCB in terms of reducing the bit-error rate (BER) and managing interference more effectively. Unlike the traditional UCB, UCB-CV leverages side information through a control variate approach, incorporating the coefficient of variation (CV) into reward estimation to better handle interference. Additionally, we underline the advantages of filtered-OFDM (FOFDM) compared to standard OFDM. Notably, FOFDM significantly reduces OOBE by 20-75 dBW/Hz and improves BER. In environments with high interference, UCB-CV achieves a throughput improvement of 29.54% compared to UCB.

关键词： OFDM Interference Throughput Wireless communication Transceivers Real-time systems Heuristic algorithms Modulation field programmable gate arrays Wireless sensor networks Adaptive physical layer dynamic partial reconfiguration (DPR) filtered-OFDM (FOFDM) FPGA intelligent reconfigurable PHY architecture machine learning multiarmed bandit (MAB) orthogonal frequency division multiplexing (OFDM) upper confidence bound (UCB)-control variate Zynq system-on-chip (SoC)

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Turbo-FHE: Accelerating Fully Homomorphic Encryption With FPGA and HBM Integration

IEEE DESIGN & TEST

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IEEE DESIGN & TEST 2025年第3期42卷 86-93页

作者： Nassar, Hassan Bauer, Lars Henkel, Jorg Karlsruhe Inst Technol Chair Embedded Syst D-76131 Karlsruhe Germany

Editor's notes: Homomorphic encryption offers a solution to escalating privacy and security concerns when the data are processed in the cloud. In this article, the authors propose an accelerator for homomorphic en... 详细信息

关键词： field programmable gate arrays Polynomials Noise Homomorphic encryption arrays Memory management Accuracy Three-dimensional displays Bandwidth Software

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Single-Path High-Resolution Digital PWM Architectures With Cascadability of Delay Lines

IEEE OPEN JOURNAL OF POWER ELECTRONICS

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IEEE OPEN JOURNAL OF POWER ELECTRONICS 2025年 6卷 130-143页

作者： Hajiheidari, Marziyeh Fushekati, Joel Emad, Mohammad Vermulst, Bas J. D. van Duivenbode, Jeroen Huisman, Henk Eindhoven Univ Technol Dept Elect Engn Power Elect Lab PELe NL-5612 AZ Eindhoven Netherlands

This paper introduces two new single-path and cascaded High-Resolution Digital Pulse Width Modulation (HRDPWM) architectures. The proposed single-path architecture uses fewer FPGA resources to achieve the same resolution as conventional dual-path architectures. Moreover, the generated HRDPWM signal is independent of the Place-And-Route (PAR) algorithm applied by the synthesis tool, as well as temperature and voltage variations. The proposed cascaded architecture can be used to increase the DPWM resolution without raising the system clock frequency or, alternatively, to reduce the FPGA system clock frequency (relaxing timing challenges) without lowering the resolution. Both architectures have been implemented and verified using a mid-range Artix-7 FPGA with both triangular and sawtooth carriers. A time resolution of 39 ps has been achieved for the cascaded HRDPWM architecture with a sawtooth carrier and a system clock of 400 MHz. Additionally, a GaN-based synchronous buck converter is designed and implemented to evaluate the performance of the proposed HRDPWM architectures in a real application. It is demonstrated that bothhldead time and duty cycle can be modified with high accuracy and resolution and updated twice per switching cycle.

关键词： Clocks Signal resolution field programmable gate arrays Delay lines Delays Pulse width modulation Propagation delay Power electronics Switching frequency Switches Digital pulse width modulation (DPWM) delay line high resolution (HR) high switching frequency

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