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OPTICS CONTINUUM 2025年第3期4卷 522-534页

作者： Jin, Jianli Shang, Qianlong Zhang, Hailong Lu, Huimin Univ Sci & Technol Beijing Sch Comp & Commun Engn Beijing 100083 Peoples R China Univ Sci & Technol Beijing Shunde Innovat Sch Foshan 528399 Peoples R China

Visible light communication (VLC) integrates with Ethernet technology as a nextgeneration wireless access solution for the "last mile," offering vast potential for short-range indoor communications. This paper designs a field programmable gate array (FPGA) based visible light Ethernet communication system that converts Ethernet signals into visible light signals. The system dynamically reduces the signal rate to maintain network efficiency through functional modules, including network interface design, flow control, rate adaptation with a peak rate of 100 Mbps, and VLC transmission/reception control logic. Simulation and experimental results show that the system can support Ethernet connections at rates below 100 Mbps and effectively adapts to deteriorating optical channel conditions, ensuring stable communication in real-world environments.

关键词： field programmable gate arrays Light sources Optical signals Signal transmission Systems design Visible light communications

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Low-Power Subgraph Isomorphism at the Edge Using FPGAs

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IEEE ACCESS 2025年 13卷 67127-67135页

作者： Bosio, Roberto Brignone, Giovanni Urso, Teodoro Lazarescu, Mihai T. Lavagno, Luciano Pasini, Paolo Politecn Torino Dept Elect & Telecommun I-10129 Turin Italy

Subgraph matching is a significant problem in several fields, including like social network analysis, chemical compound search, and fraud detection. While current solutions using CPU, graphics processing units (GPUs), and data center field-programmable gate arrays (FPGAs) deliver high performance, they consume significant power, making them unsuitable for resource-constrained edge environments. This article introduces a novel low-power FPGA accelerator that enables efficient subgraph matching using a small FPGA-based accelerator through three main innovations: a flexible two-level hash table architecture that minimizes memory accesses, a caching mechanism that reduces on-chip memory requirements, and a dynamic first-in first-out (FIFO) queue that efficiently buffers partial results. Experimental results on five real-world graphs show that the accelerator reduces energy consumption by an average of ${75 \,\, \times }$ compared to state-of-the-art CPU solutions, and ${107 \,\, \times }$ compared to GPU solutions, demonstrating that complex graph operations can be performed efficiently using even a small accelerator implemented on a reconfigurable platform.

关键词： field programmable gate arrays Graphics processing units Matched filters Hash functions Central Processing Unit System-on-chip Parallel processing Memory management Throughput Space exploration Graph theory FPGA high-level synthesis cache query

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Enabling Model-Based Design for Real-Time Spike Detection

IEEE OPEN JOURNAL OF ENGINEERING IN MEDICINE AND BIOLOGY

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IEEE OPEN JOURNAL OF ENGINEERING IN MEDICINE AND BIOLOGY 2025年 6卷 312-319页

作者： Di Florio, Mattia Bornat, Yannick Care, Marta Cota, Vinicius Rosa Buccelli, Stefano Chiappalone, Michela Univ Genoa Dept Informat Bioengn Robot Syst Engn DIBRIS I-16145 Genoa Italy Univ Bordeaux Lab Integrat Mat Syst IMS Bordeaux INP CNRS UMR 5218 F-33405 Talence France IRCCS Osped Policlin San Martino I-16132 Genoa Italy Ist Italiano Tecnol Rehab Technol Lab I-16163 Genoa Italy

Goal: This study addresses the inherent difficulties in the creation of neuroengineering devices for real-time neural signal processing, a task typically characterized by intricate and technically demanding processes. Beneath the substantial hardware advancements in neurotechnology, there is often rather complex low-level code that poses challenges in terms of development, documentation, and long-term maintenance. Methods: We adopted an alternative strategy centered on Model-Based Design (MBD) to simplify the creation of neuroengineering systems and reduce the entry barriers. MBD offers distinct advantages by streamlining the design workflow, from modelling to implementation, thus facilitating the development of intricate systems. A spike detection algorithm has been implemented on a commercially available system based on a field-programmable gate Array (FPGA) that combines neural probe electronics with configurable integrated circuit. The entire process of data handling and data processing was performed within the Simulink environment, with subsequent generation of hardware description language (HDL) code tailored to the FPGA hardware. Results: The validation was conducted through in vivo experiments involving six animals and demonstrated the capability of our MBD-based real time processing (latency <= 100.37 s) to achieve the same performances of offline spike detection. Conclusions: This methodology can have a significant impact in the development of neuroengineering systems by speeding up the prototyping of various system architectures. We have made all project code files open source, thereby providing free access to fellow scientists interested in the development of neuroengineering systems.

关键词： Hardware design languages Software packages Codes field programmable gate arrays Computer architecture Hardware Signal processing algorithms Neural engineering Signal processing Computational modeling in vivo experiments HDL coder field-programmable gate Array (FPGA) neuroengineering

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Energy-Efficient and Secure Edge AI

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IEEE NANOTECHNOLOGY MAGAZINE 2025年第2期19卷 5-6页

作者： Yeo, Kiat Seng

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FPGA-Based Real-Time Road Object Detection System Using mmWave Radar

IEEE SENSORS LETTERS

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IEEE SENSORS LETTERS 2025年第4期9卷

作者： Mohan, Anand Meena, Hemant Kumar Wajid, Mohd Srivastava, Abhishek Malaviya Natl Inst Technol Dept Elect Engn Jaipur 302017 India Aligarh Muslim Univ Dept Elect Engn Aligarh 202002 India Int Inst Informat Technol Hyderabad Ctr VLSI Design Embedded Syst Technol Hyderabad 500032 India

This letter presents the development of a real-time object detection system using frequency modulated continuous wave millimeter-wave (mmWave) radar signals and the python productivity for zynq ultrascale + mpsocs (PYNQ-ZU) field-programmable gate array (FPGA) board, which is widely used in advanced driving assistance system and robotic applications. A hardware FPGA platform serves as a valid embedded architecture for the purpose of validating object detection and recognition applications. We used our experiment's point cloud images to apply different machine learning models to detect these objects. Using a top-view (TV) filter to convert 3-D point cloud images into 2-D representations made object detection more accurate. Following the use of filtration techniques, we extracted features from the filtered 2-D image using the visual geometry group (VGG) 16 model. We then assessed four machine learning models for object detection and found that the support vector machine (SVM) model and logistic regression (LR) had better results, obtaining an accuracy of 97%. Our proposed work uses mmWave radar, TV filter, VGG 16 Model, and LR to highly increase object detection accuracy over existing methods.

关键词： Radar Object detection Radar detection Point cloud compression Millimeter wave radar field programmable gate arrays Accuracy Radar imaging Millimeter wave communication Feature extraction Sensor applications field-programmable gate array (FPGA) board mmWave radar machine learning object detection PYNQ-ZU point cloud images support vector machine (SVM) VGG 16 model

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FOG: Fast Octree Generator for LiDAR Point Clouds

IEEE SENSORS LETTERS

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IEEE SENSORS LETTERS 2025年第1期9卷

作者： Roriz, Ricardo Costa, Diogo Ekpanyapong, Mongkol Gomes, Tiago Univ Minho ALGORITMI Res Ctr LASI P-4800058 Guimaraes Portugal Asian Inst Technol Sch Engn & Technol Pathum Thani 12120 Thailand

As the need for realistic and immersive 3-D representations of the environment continues to increase across various industries, finding efficient ways to represent data has become paramount. A well-known approach to partitioning 3-D space into a structured data format is the use of octrees, primarily due to their efficiency in handling both sparse and dense 3-D data. This method is particularly useful in applications involving automotive light detection and ranging (LiDAR) sensors, which are widely used in autonomous driving systems for their ability to capture detailed spatial information in real-time. This letter introduces the fast octree generator (FOG) algorithm, a novel approach for generating octrees from 3-D LiDAR point clouds that leverages hardware acceleration. FOG achieves a performance improvement of up to 88.8% compared to PCL's octree implementation, enabling real-time octree generation for high-end sensors on embedded platforms.

关键词： Octrees Three-dimensional displays Point cloud compression Sensors Image reconstruction Laser radar Codes Real-time systems PSNR field programmable gate arrays Sensor applications 3-D light detection and ranging (LiDAR) field-programmable gate array (FPGA) octree

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A web-based three-dimensional modeling system for human abdominal organs by using computed tomography scans

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JOURNAL OF RADIATION RESEARCH AND APPLIED SCIENCES 2025年第1期18卷

作者： Zeng, Hui Xu, Xianfu Wei, Wei Zhang, Xuejun Zhang, Shan Liang, Bohui Liang, Mingxian Wu, Dongbo Liu, Xiaojing Guangxi Univ Sch Comp Elect & Informat Nanning 530004 Peoples R China China Railway Nanning Bur Grp Co Ltd Informat Technol Inst Nanning Peoples R China Guangxi Univ Guangxi Key Lab Multimedia Commun Network Technol Nanning Peoples R China Wuzhou Hosp Tradit Chinese Med Wuzhou Peoples R China Liuzhou Workers Hosp Liuzhou Peoples R China Inst Artificial Intelligence & Big Data Applicat G Nanning Peoples R China

3D modeling is a crucial step in computer-aided diagnosis and virtual surgery. Current deep learning-based 3D organ modeling requires the collection of large datasets and extended training times, which makes rapid modeling difficult to achieve. To address this issue, we propose a hardware-accelerated 3D modeling system based on edge detection. We optimized the existing segmentation algorithms and introduced a new surrounding tissue removal algorithm to improve segmentation accuracy. Additionally, we developed a hardware-accelerated system that speeds up computationally intensive algorithms and deployed it on an edge server. A web application was developed to enable 3D modeling on a web platform. We evaluated the performance of the proposed system by comparing its processing time and modeling quality for three different slice sizes with the baseline system. Experimental results demonstrate that, compared to the baseline system, the hardware-accelerated 3D modeling system produced models with the same accuracy as the baseline, while reducing processing time by 6.4%, 17.5%, and 46.2%, respectively, for the three different sizes of CT images.

关键词： Edge computing field programmable gate arrays Hardware acceleration Image segmentation Three-dimensional modeling ZYNQ

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A Delay-Free Decoupling Method for FPGA-Based Real-Time Simulation of Power Electronic Systems

IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN INDUSTRIAL E...

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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN INDUSTRIAL ELECTRONICS 2025年第1期6卷 391-402页

作者： Yang, Yiming Xu, Jin Wang, Keyou Wu, Pan Li, Zirun Li, Guojie Shanghai Jiao Tong Univ Key Lab Control Power Transmiss & Convers Minist Educ Shanghai 200240 Peoples R China North China Branch State Grid Beijing 100053 Peoples R China

The decoupling method based on the natural or inserted artificial delays, when applied to the simulation of power electronic (PE) systems, may encounter challenges such as inadequate length of delay lines or numerical instability and precision issues due to the high-frequency voltage/current variations at interfaces. To deal with the challenge, a delay-free decoupling method is proposed in this article. The method reduces both the dimension of matrix multiplication and the number of switch state combinations without sacrificing numerical stability and compresses the calculation progress by representing the decoupled system with the discrete state-space equation. The PE system is decoupled at the series/parallel interface of submodules, treating currents as boundary variables linked to each submodule's extended port. A preliminary formula for these variables is derived by simultaneously solving nodal voltage equations and kirchhoff voltage laws (KVL) equations. Submodule solutions are compacted and parallelized based on the discrete state-space equations. These equations are then substituted back and decomposing boundary variables into independent segments, to achieve parallelization of boundary variable solutions. The proposed method is validated through real-time simulation of cascaded PE systems on an field programmable gate array (FPGA) platform with a 250 ns time step. Results show that it achieves high precision compared to nondecoupled systems in power systems computer aided design (PSCAD) across diverse transient conditions. Additionally, it boosts the simulation scale by roughly 2-7 times on the FPGA-based platform compared to nondecoupled nodal analysis.

关键词： Real-time systems Mathematical models Sparse matrices field programmable gate arrays Switches Delays Accuracy Voltage Switching circuits Parallel processing Delay-free decoupling EMT field programmable gate array (FPGA) modular multilevel converter (MMC) power electronic transformer (PET) real-time simulation

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Hardware-in-the-Loop Real-Time Transient Emulation of Large-Scale Renewable Energy Installations Based on Hybrid Machine Learning Modeling

IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN INDUSTRIAL E...

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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN INDUSTRIAL ELECTRONICS 2025年第2期6卷 468-478页

作者： Chen, Ruogu Cheng, Tianshi Lin, Ning Liang, Tian Dinavahi, Venkata Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2V4 Canada Powertech Labs Inc Surrey BC V3W 7R7 Canada RTDS Technol Inc Winnipeg MB R3T 2E1 Canada CSG Elect Power Res Inst Co Ltd Guangzhou 510663 Peoples R China

For the integration of large-scale renewable energy resources into power grids, the complex and dynamic behavior of inverter-based resources (IBRs), such as wind farms, photovoltaic (PV) arrays, and battery energy storage systems (BESSs), poses significant challenges. Traditional models often fall short of feasibly simulating these resources at scale. This article introduces a hybrid machine learning approach, employing multilayer perceptrons (MLPs) and gated recurrent units (GRUs), to effectively simulate IBRs. The hybrid models combine MLPs and GRUs to capture the transients of IBRs. An extensive dataset, including environmental data, load profiles, and fault instances, was used for training and validation. The source of this dataset was the computational electromagnetic transient (EMT) models of IBRs and validated results. A test system was developed to integrate a microgrid comprising batched ML-based IBR modules into a large-scale ac-dc system, which is based on the IEEE 118-bus system. The system is deployed on a field-programmable gate array (FPGA) board, highlighting the viability of real-time, hardware-accelerated emulations. The results show that the hybrid ML methodology accurately represents large-scale IBRs and predicts transient behaviors in integrated grids, offering crucial insights for the future planning, operation, and control of ac-dc grids, especially those with high renewable energy integration.

关键词： Computational modeling Transient analysis Integrated circuit modeling Renewable energy sources field programmable gate arrays Logic gates Machine learning Artificial neural networks (ANN) battery energy storage electromagnetic transients faster-than-real-time gated recurrent units field programmable gate arrays (FPGAs) hardware-in-the-loop (HIL) inverter-based resources (IBRs) machine learning (ML) multilayer perceptron (MLP) photovoltaic (PV) transient behavior wind farms

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Novel four dimensional hyperchaotic system: analysis, adaptive control, analog and digital circuit design

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International Journal of Information Technology (Singapore) 2025年第2期17卷 1137-1145页

作者： Suneja, Kriti Pandey, Neeta Pandey, Rajeshwari Department of Electronics and Communication Engineering Delhi Technological University Delhi India

In this paper, a new four-dimensional hyperchaotic system (HCS), with quadratic nonlinearities, has been proposed. The chaotic dynamical behaviors of the proposed system and its dynamic properties such as Lyapunov exponents, Kaplan Yorke dimension and dissipativity have been examined. To explore the proposed systems’ applications in communication world, adaptive self-synchronization scheme has also been put forward. The electronic realizability of the proposed system is examined in both analog and digital domains. The analog realization is based on Current Feedback Operational Amplifier (CFOA) while the field programmable gate Array (FPGA) is used for digital one. The proposed HCS has some important features namely simple model, simple circuitry, minimum component count and sensitive with passive components that signifies the advantages for the signal processing circuit and its applications. © Bharati Vidyapeeth's Institute of Computer Applications and Management 2024.

关键词： Current feedback operational amplifier field programmable gate arrays Hyperchaos Lyapunov exponents Nonlinear dynamic systems

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