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Opportunity Research Scholars Symposium (ORSS)

作者： Luke Hanks Cullen Lonergan Karsten Richardson Jennifer Hasler Pranav Mathews Afolabi Ige School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta Georgia USA

ISBN: (数字)9798350390698

ISBN: (纸本)9798350390704

In this paper, we describe our effort to extend the development of a standard framework for analog computing through further developing and integrating an existing high level synthesis (HLS) tool for analog system design. These Python and Scilab based tools allow designers to design and implement reconfigurable systems on field-programmable analog arrays (FPAA). In doing this, we can provide a way to have the same ease of development that digital integrated circuits (ICs) have with the field-programmable gate-array (FPGA). We describe the importance of analog computing, the state of the old tool flow, our contributions to upgrading the tool flow, and our demonstration of the working tools.

关键词： Phased arrays Digital integrated circuits field programmable analog arrays Logic gates High level synthesis Design tools field programmable gate arrays System analysis and design Standards Python

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DCryp-Unit: Crypto Hardware Accelerator Unit Design for Elliptic Curve Point Multiplication

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IEEE ACCESS 2024年 12卷 17823-17835页

作者： Alharbi, Adel R. Hazzazi, Mohammad Mazyad Jamal, Sajjad Shaukat Aljaedi, Amer Aljuhni, Abdullah Alanazi, Dalal J. Univ Tabuk Coll Comp & Informat Technol Tabuk 71491 Saudi Arabia King Khalid Univ Coll Sci Dept Math Abha 61413 Saudi Arabia Univ Tabuk Fac Sci Dept Math Tabuk 71491 Saudi Arabia

We propose a hardware-optimized design that implements a Montgomery Elliptic-curve point multiplication Algorithm over GF(2(233)) using Lopez-Dahab projective coordinates. Moreover, we propose a digit-parallel modular multiplier, which reduces clock cycles and improves throughput. Also, we provided how to use our proposed digit-parallel multiplier for post-quantum cryptography algorithms. In addition, we use the proposed digit-parallel multiplier with the square circuit to implement the Itoh-Tsujii inversion algorithm for modular inversion computation;this permits hardware resource minimization. An efficient finite-state machine controller is implemented for control functionalities. A figure of merit in throughput/area is defined for reasonable comparison to state-of-the-art. We provide implementation results after post-place-and-route on field-programmable gate array devices. On the Virtex-7 device, our design utilizes 3386 slices and requires 7218 clock cycles;it achieves a maximum frequency of 365 MHz and computes one point multiplication in 19.77 mu s . The total power consumption of our design is 2027 mW. The calculated values for throughput and figure of merit are 50.58Kbps and 14.93, respectively. Consequently, the implementation results and comparisons reveal our design's suitability for applications requiring area and throughput-optimized cryptographic implementations.

关键词： Hardware acceleration field programmable gate arrays Cryptography Computer architecture Throughput Elliptic curve cryptography Elliptic curves Binary elliptic curves point multiplication hardware design implementation FPGA

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FSpGEMM: A Framework for Accelerating Sparse General Matrix–Matrix Multiplication Using Gustavson’s Algorithm on FPGAs

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2024年第4期32卷 633-644页

作者： Tavakoli, Erfan Bank Riera, Michael Quraishi, Masudul Hassan Ren, Fengbo Arizona State Univ Tempe AZ 85287 USA

General sparse matrix-matrix multiplication (SpGEMM) is integral to many high-performance computing (HPC) and machine learning applications. However, prior field-programmable gate array (FPGA)-based SpGEMM accelerators either use the inner product algorithm with wasted and costly operations or Gustavson's algorithm with a cache-based hardware architecture suffering from long-latency cache miss penalties and limited to embedded devices. In this work, we propose framework for accelerating SpGEMM (FSpGEMM), an OpenCL-based SpGEMM framework for accelerating Gustvason's algorithm that includes an FPGA kernel implementing a throughput-optimized and scalable hardware architecture compatible with high-bandwidth memory (HBM) or traditional DDR-based memory. In addition, to address the irregular memory access patterns incurred by Gustavson's algorithm, we propose a new buffering scheme tailored to Gustavson's algorithm enabled by a new compressed sparse vector (CSV) format for representing sparse matrices and a row reordering technique as a preprocessing step to improve data reuse, and consequently, resource utilization. The proposed framework includes a host program implementing preprocessing functions for reordering input matrices and storing them in the proposed CSV format for further use. We implemented FSpGEMM using Intel FPGA SDK for OpenCL and experimented with a benchmark of sparse matrices selected from the SuiteSparse Matrix Collection on a Bittware 520N-MX FPGA board. The results show that the reordering technique improves the performance on average by 20.3% compared with the baseline. Finally, FSpGEMM outperforms the state-of-the-art (SOTA) FPGA implementation by an average of 2.23 $\times$ in terms of execution cycles with the same benchmark and memory system configuration for a fair comparison.

关键词： field programmable gate arrays Sparse matrices Hardware Memory management Graphics processing units Indexes Matrix converters field-programmable gate array (FPGA) general sparse matrix-matrix multiplication (SpGEMM) Gustavson's algorithm OpenCL reconfigurable computing

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SCALES: SCALable and Area-Efficient Systolic Accelerator for Ternary Polynomial Multiplication

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2024年第2期23卷 243-246页

作者： Coulon, Samuel Bao, Tianyou Xie, Jiafeng Villanova Univ Dept Elect & Comp Engn Villanova PA 19085 USA

Polynomial multiplication is a key component in many post-quantum cryptography and homomorphic encryption schemes. One recurring variation, ternary polynomial multiplication over ring Z(q)/(x(n)+1) where one input polynomial has ternary coefficients {-1,0,1} and the other has large integer coefficients {0, $q-1$q-1}, has recently drawn significant attention from various communities. Following this trend, this paper presents a novel SCALable and area-Efficient Systolic (SCALES) accelerator for ternary polynomial multiplication. In total, we have carried out three layers of coherent interdependent efforts. First, we have rigorously derived a novel block-processing strategy and algorithm based on the schoolbook method for polynomial multiplication. Then, we have innovatively implemented the proposed algorithm as the SCALES accelerator with the help of a number of field-programmable gate array (FPGA)-oriented optimization techniques. Lastly, we have conducted a thorough implementation analysis to showcase the efficiency of the proposed accelerator. The comparison demonstrated that the SCALES accelerator has at least 19.0% and 23.8% less equivalent area-time product (eATP) than the state-of-the-art designs. We hope this work can stimulate continued research in the field.

关键词： Polynomials field programmable gate arrays Vectors Transforms Matrix decomposition Time complexity Systolic arrays Shift registers Proposals Process control Area-efficient block-processing FPGA scalable systolic hardware accelerator ternary polynomial multiplication

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Fast Update Algorithm With Reorder Mechanism for SRAM-Based Longest Prefix Matching on FPGA

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第1期71卷 420-424页

作者： Song, Xiaoyong Guo, Zhichuan Chinese Acad Sci Inst Acoust Natl Network New Media Engn Res Ctr Beijing 100190 Peoples R China Univ Chinese Acad Sci Sch Elect Elect & Commun Engn Beijing 100049 Peoples R China

Longest prefix matching (LPM) is often used in network forwarding and it is usually implemented by ternary content addressable memory (TCAM) on field programmable gate array (FPGA). The traditional SRAM based TCAM only has one clock cycle in search delay, but it has a non-negligible update latency. Different from the general TCAM words, the ternary bits in LPM words are arranged continuously from low bits to high, and the prefix lengths of words have some distribution characteristics on actual network traffics. In this brief, a design is proposed to reduce the update latency of LPM by fast update algorithm with reorder mechanism. The key idea is reorder LPM prefix and partition don't care bits into each sub-prefix evenly in SRAM based LPM, so that the update latency in each sub-table would be minimized and the whole update latency would be reduced. The design of this brief is implemented on Xilinx Kintex-7 field-programmable gate array. Compared to the prior methods, the update latency of LPM is reduced by at least half or more in most cases with our method. As far as we know, this is the fastest update mechanism in SRAM based LPM, which consumes the least possible clock cycles.

关键词： Random access memory field programmable gate arrays Clocks Partitioning algorithms Engines Pattern matching Memory management field programmable gate array (FPGA) SRAM-based TCAM longest prefix matching (LPM) update latency IP lookup

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FPGA implementation of power-lite Volterra-inspired neural network equalizer in 180-Gb/s net bitrate IMDD short-reach optical system

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OPTICS LETTERS 2024年第16期49卷 4573-4576页

作者： Jiang, Wenqing Guan, Xiaokai Huang, Luyao Xu, Yongxin Xie, Yunhao Hu, Weisheng Yi, Lilin Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn State Key Lab Adv Opt Commun Syst & Networks Shanghai 200240 Peoples R China China Telecom Res Inst Guangzhou Peoples R China

A white-box power-lite Volterra-inspired neural network (VINN) equalizer is proposed to solve the problem of (VNLE). By adjusting the granularity of the solution space, it conserves computational resources while maintaining nonlinear compensation capability. The performance of VINN is verified on a field-programmable gate array (FPGA) in a short-reach intensity modulation and direct detection (IMDD) system, and a 240-Gb/s real-time signal processing rate is achieved. Under the 25% overhead soft-decision threshold, we realize a record net rate of up to 180 Gb/s based on the FPGA. (c) 2024 Optica Publishing Group. All rights, training, and similar technologies, are reserved.

关键词： field programmable gate arrays Neural networks Optical signals Optical systems Signal processing Variable optical attenuators

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Pulse Synchronization Scheme for Undersea BWPT System Based on Simultaneous Wireless Power and Data Transfer Technology

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2025年第1期72卷 333-337页

作者： Da, Chaolai Li, Fang Wang, Lifang Tao, Chengxuan Li, Shufan Nie, Ming Chinese Acad Sci Inst Elect Engn Key Lab High Dens Electromagnet Power & Syst Beijing 100190 Peoples R China Univ Chinese Acad Sci Sch Elect Elect & Commun Engn Beijing 100049 Peoples R China

A novel pulse synchronization scheme is proposed in this brief based on simultaneous wireless power and data transfer (SWPDT) technology to address the pulse synchronization issue of the undersea bidirectional wireless power transfer (BWPT) system due to the special characteristics of the undersea environment. Accurate pulse synchronization can be implemented by adapting the software to the existing SWPDT system based on the DDQ coil. Furthermore, this brief proposes a phase lock scheme that can eliminate the issue of pulse false triggering, which is caused by the interference of the BWPT channel to the data channel. A prototype with an output power of 1 kW and a data rate of 1 Mb/s demonstrates the feasibility of the pulse synchronization scheme proposed in this brief. The work of this brief extends the application of SWPDT technology and also presents a new solution for pulse synchronization in the BWPT system.

关键词： Synchronization field programmable gate arrays Coils Accuracy Interference Demodulation Circuits Couplings Software Pulse width modulation Bidirectional wireless power transfer (BWPT) modulation and demodulation pulse synchronization simultaneous wireless power and data transfer (SWPDT) undersea wireless power transfer (UWPT)

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Lattice-Based Fault Attack and Defensive Strategies Targeting the SM2 Signature Algorithm

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ELECTRONICS LETTERS 2025年第1期61卷

作者： Shao, Cuiping Li, Wenzhe Li, Huiyun Liang, Jianing Shenzhen Univ Adv Technol Shenzhen Peoples R China Univ Chinese Acad Sci Beijing Peoples R China Chinese Acad Sci Shenzhen Inst Adv Technol Shenzhen Guangdong Peoples R China

Fault attacks targeting signature nonce pose a critical threat to elliptic curve digital signatures, potentially exposing private keys through non-invasive methods. This letter presents an efficient and practical defence strategy against lattice-based fault injection attacks on ephemeral nonce in the SM2 digital signature algorithm (SM2-DSA). Our proposed countermeasure effectively protects against such sophisticated lattice-based fault attacks while maintaining minimal overhead in both time and hardware resources. Specifically, our countermeasure incurs only a 0.8% time overhead and the area overhead for secure design does not exceed 1%. Our research provides valuable insights for evaluating the security of hardware implementations of SM2-DSA.

关键词： cryptography field programmable gate arrays integrating circuits

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The Pains of Hardware Security: An Assessment Model of Real-World Hardware Security Attacks

IEEE OPEN JOURNAL OF THE INDUSTRIAL ELECTRONICS SOCIETY

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IEEE OPEN JOURNAL OF THE INDUSTRIAL ELECTRONICS SOCIETY 2025年 6卷 603-617页

作者： Maragkou, Sofia Rappel, Lukas Dettmer, Hendrik Sauter, Thilo Jantsch, Axel TU Wien Inst Comp Technol ICT A-1040 Vienna Austria TUV Austria GMBH A-1230 Vienna Austria Univ Continuing Educ Krems Dept Integrated Sensor Syst A-2700 Wiener Neustadt Austria

From military applications to everyday devices, hardware (HW) security is more relevant than ever before. The supply chain of integrated circuits is global and involves multiple actors, which facilitate the implementation of various attacks. Its complexity increases the attack surfaces, violating not only the privacy of the users or even national security but also endangering human life. We review some of the publicly known HW attacks that have occurred and propose an assessment scheme for the attacks and the defense on hardware. Using this scheme, we relate the costs of attacks and defense and provide a structured landscape of HW attacks. To illustrate the utility of our assessment scheme, we apply it to a number of real-world and synthetic research cases. We observe a gap between the research use cases and the real-world attacks and envision that the comprehensive assessment of the attacks will enable the development of more suitable countermeasures. In addition, we revised the security policies for HW devices, and we conclude that the complexity and obscurity of the supply chain are key parameters impacting HW security, providing attack surfaces. Finally, we identify the demystification of the supply chain as the main strategy to mitigate this problem.

关键词： Hardware Supply chains Security Hardware security Fabrication field programmable gate arrays Software Microprogramming Costs Complexity theory Assessment scheme counterfeit chips hardware (HW) attacks HW security HW security policies HW Trojans real-world HW attacks side-channel analysis supply chain analysis

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A Practical Design of Single-Slope ADC With Improved Dynamic Range on FPGA

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第5期72卷 1810-1818页

作者： Zhang, Jianfeng Wang, Yonggang Zhang, Keyi Qi, Xinren Univ Sci & Technol China Dept Modern Phys State Key Lab Particle Detect & Elect Hefei 230026 Anhui Peoples R China

The development of field-programmable gate array (FPGA)-based analog-to-digital converters (ADCs) helps to improve system integration, shorten development cycles, and reduce costs. One realization of this is the single-slope ADC, which uses a ramp waveform to intersect the input signal, converting the input voltage into a measurable time interval for digitization. Although existing designs are capable of waveform digitization, there remains considerable potential for further research in terms of design practicality, flexibility, and performance. This article presents an implementation that advances current designs in three aspects. First, by decoupling the ADC sampling clock from the time-to-digital converter (TDC) clock, the ADC's sampling rate can be reconfigured without the need for firmware resynthesis. Second, the two cross points within a single sampling cycle are combined to convert voltage into pulsewidth for measurement, significantly simplifying the firmware design. Finally, a mapping calibration between time and voltage is applied to improve the ADC linearity while maintaining the widest possible dynamic range. The proposed ADC was implemented on a Xilinx UltraScale+ FPGA for performance evaluation at a 200-MS/s sampling rate and 10-bit resolution. Test results show that the ADC achieves a measurement range of 70-1770 mV with an effective number of bits (ENOB) of 7.2. The differential nonlinearity (DNL) ranges from -0.23 to 0.23 LSB, and the integral nonlinearity (INL) ranges from -1.95 to 1.33 LSB. This ADC design requires no off-chip components, is not susceptible to FPGA placement and routing, and can be implemented as an intellectual property (IP) core, allowing end-users to integrate it into systems without requiring in-depth knowledge of ADC design.

关键词： Voltage measurement Clocks field programmable gate arrays Dynamic range Pulse measurements Calibration Delays Costs Temperature measurement Physics Analog-to-digital converter (ADC) field-programmable gate array (FPGA) time-to-digital converter (TDC)

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