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检索条件"主题词=Field Programmable Gate Arrays"

共 41416 条记录，以下是4991-5000 订阅

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MUSIC GENRE CLASSIFICATION USING SPATAN 6 FPGA AND TMS320C6713 DSK

MUSIC GENRE CLASSIFICATION USING SPATAN 6 FPGA AND TMS320C67...

引用

IEEE International Conference on Signal Processing and Communication (ICSPC)

作者： Saju, Solomon Rajan, Rajeev Jayan, A. R. Rajiv Gandhi Inst Technol Dept Elect & Commun Engn Kottayam Kerala India

ISBN: (纸本)9781509067305

Music genre classification is one of the most important element of the music information retrieval (MIR) community. In this paper, we present a music genre classification system using field programmable gate arrays (FPGA) and dedicated DSP processors. The proposed system uses FPGA based acoustic feature extraction of mel frequency cepstral coefficients (MFCC) and dynamic time warping (DTW) based classifier using TMS320C6713 floating point processor. We successfully implemented MFCC extraction algorithm on Spartan 6 FPGA clocked at 150 MHz with support from TMS320C6713 floating point processor followed by DTW based matching engine. The paper attempts to implement music genre classification algorithm in hardware, yielding competitive performance in music information retrieval applications.

关键词： Mel frequency cepstral coefficient field programmable gate arrays Filter banks Signal processing algorithms Matlab Microsoft Windows Feature extraction

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Fast Classification Using Sparsely Active Spiking Networks 50

Fast Classification Using Sparsely Active Spiking Networks

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Mostafa, Hesham Pedroni, Bruno U. Sheik, Sadique Cauwenberghs, Gert Univ Calif San Diego Inst Neural Computat La Jolla CA 92093 USA Univ Calif San Diego Dept Bioengn La Jolla CA USA Univ Calif San Diego BioCircuits Inst La Jolla CA USA

ISBN: (纸本)9781467368537

Spike generation and routing is typically the most energy-demanding operation in neuromorphic hardware built using spiking neurons. Spiking neural networks running on neuromorphic hardware, however, often use rate-coding where the neurons spike rate is treated as the information-carrying quantity. Rate-coding is a highly inefficient coding scheme with minimal information content in each spike, which requires the transmission of a large number of spikes. In this paper, we describe an alternative type of spiking networks based on temporal coding where neuron spiking activity is very sparse and information is encoded in the time of each spike. We implemented the proposed networks on an FPGA platform and we use these sparsely active spiking networks to classify MNIST digits. The network FPGA implementation produces the classification output using only few tens of spikes from the hidden layer, and the classification result is obtained very quickly, typically within 1-3 synaptic time constants. We describe the idealized network dynamics and how these dynamics are adapted to allow an efficient implementation on digital hardware. Our results illustrate the importance of making use of the temporal dynamics in spiking networks in order to maximize the information content of each spike, which ultimately leads to reduced spike counts, improved energy efficiency, and faster response times.

关键词： Neurons field programmable gate arrays Hardware Training Biological neural networks Encoding Adaptation models

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Association Analysis of Nonlinear Saturation Characteristics Based on High-speed and High-output Photodetectors 17

Association Analysis of Nonlinear Saturation Characteristics...

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17th International Conference on Numerical Simulation of Optoelectronic Devices NUSOD

作者： Liu, Jingzhao Huang, Yongqing Fei, JiaRui Liu, Kai Duan, Xiaofeng Ren, Xiaomin Beijing Univ Posts & Telecommun State Key Lab Informat Photon & Opt Commun Beijing Peoples R China

ISBN: (纸本)9781509053230

With the development of optical communication system, the nonlinear saturation characteristics of photodetectors are necessary to consider. We observed the 1-dB compression current as DC photocurrent saturation point under high power illumination in PIN-PDs. Meanwhile, a new method of measuring AC saturated output power in the time domain is proposed. The quantitative relationship between DC saturation point and AC saturation point is given.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A Diffusion Model to Explain and Forecast Freeway Breakdown and Delay 5

A Diffusion Model to Explain and Forecast Freeway Breakdown ...

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5th IEEE International Conference on Models and Technologies for Intelligent Transportation Systems (MT-ITS)

作者： Ossenbruggen, Paul J. Univ New Hampshire Dept Civil Engn Durham NH 03824 USA

ISBN: (纸本)9781509064847

The chance that a freeway will breakdown, transition from a free-flow to a congested state, is normally assumed to increase with an increase in traffic volume V (vehicles per unit time). In this paper, this assumption is challenged. Traffic density K (vehicles per unit length) proves to be a better predictor. Diffusion or stochastic differential equation (SDE) modeling is used to substantiate the claim. SDE modeling is especially useful in explaining the role that traffic noise (volatility) plays in breakdown. The SDE models take advantage of the unique properties of the geometric Brownian motion (gBM) and Ornstein-Uhlenbeck (OU) model structures. The breakdown probability model of pi(K) and delay models provide accurate forecasts.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Automated Placement for Parallelized FPGA FFTs

Automated Placement for Parallelized FPGA FFTs

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IEEE 19th Annual International Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Gowda, Suraj Parsons, Aaron Jarnot, Robert Werthimer, Dan Univ Calif Berkeley EECS Berkeley CA 94720 USA Univ Calif Berkeley Astron Berkeley CA 94720 USA CALTECH Jet Prop Lab Pasadena CA 91125 USA Univ Calif Berkeley Space Sci Lab Berkeley CA 94720 USA

ISBN: (纸本)9780769543017

We present an automated placement algorithm for a high-bandwidth, streaming fast Fourier transform (FFT) generated using an open-source core generator. For radio spectral line analysis, we generate a 2048-point FFT for a standard commercial FPGA high-bandwidth spectrometer, which can process 16 digital samples per cycle simultaneously (streaming). Our placement algorithm enables this system to operate at 375 MHz and process a 6 GHz sampling rate, nearly 85% of the theoretical maximum FPGA clock rate. This algorithm is a special case of the junction tree algorithm from machine learning, and allows our design to support a 25% faster clock than the standard Xilinx toolflow implementation while using 50% less CPU time to compile. This gain is equivalent to gains induced by floorplanning with no hand placement.

关键词： Algorithm design and analysis Digital signal processing Discrete Fourier transforms FFT FPGA FPGA high-bandwidth spectrometer field programmable gate arrays Junctions Optimization Partitioning algorithms automated placement automated placement fast Fourier transform fast Fourier transforms field programmable gate arrays junction tree algorithm machine learning open-source core generator parallel algorithms parallelized FPGA FFT radio spectral line analysis spectrometer

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IEEE International Conference on Fuzzy Systems (FUZZ-IEEE)

作者： Cherif, Sahar Baklouti, Nesrine Snasel, Vaclav Alimi, Adel M. Natl Engn Sch Sfax Res Grp Intelligent Machines REGIM Lab Sfax Tunisia

ISBN: (纸本)9781509060344

Fuzzy Similarity Measure (FSM) is one of the most used techniques for classification, pattern recognition or knowledge reduction. While many type-1 FSMs exist, few ones exist for type-2 fuzzy sets. In this paper, we introduce three similarity measures between Interval Type-2 Fuzzy Sets (IT-2 FSs) as an extension of some distance measures between Intuitionistic Fuzzy Sets (IFSs). Many definitions and properties are exposed in order to prove that the formulas presented are indeed similarity measures. Experimental results are presented, comparison with other existing type-2 FSMs is done and interpretation is given in order to satisfy FSM properties.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Low-latency FPGA Based Financial Data Feed Handler

Low-latency FPGA Based Financial Data Feed Handler

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IEEE 19th Annual International Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Pottathuparambil, Robin Coyne, Jack Allred, Jeffrey Lynch, William Natoli, Vincent Univ N Carolina Reconfigurable Comp Syst Lab Charlotte NC 28223 USA Stone Ridge Technol Bel Air MD 21015 USA

ISBN: (纸本)9780769543017

Financial exchanges provide real time data feeds containing trade, order and status information to brokers, traders and other market makers. ITCH is one such market data feed that is disseminated by the NASDAQ exchange. The work presented in this paper describes an FPGA based ITCH feed handler and processing system. The handler, built on the Stone Ridge RDX-11 hardware platform with a combination of HDL and ImpulseC, accepts and processes ITCH packets at line speed with extremely low latency. Our implementation parses sixteen different stock symbols in the feed and generates an outbound packet on the NASDAQ one second heartbeat. The unit was tested with an artificial feed that could be adjusted in speed to simulate market surges. The system demonstrated a turnaround latency of 2.7 mu s with very little variation for all tested feed rates. The CPU equivalent demonstrated 38 +/- 22 mu s (1x rate) with a long tail illustrating the variability inherent to processing by the host O/S. The FPGA solution demonstrated ultra-low, deterministic latency and was able to continue processing data at the line rate limit.

关键词： Algorithm design and analysis Bridges FPGA FPGA Feeds field programmable gate arrays Generators HDL Hardware ITCH ITCH feed handler ImpulseC Low-latency Trading Monitoring NASDAQ exchange data handling data processing deterministic latency field programmable gate arrays financial data feed handler financial data processing financial exchanges hardware description languages processing system stock markets

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Creating a Serial Driver Chip for Commanding Robotic Arms

Creating a Serial Driver Chip for Commanding Robotic Arms

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Federated Conference on Computer Science and Information Systems (FedCSIS)

作者： Szabo, Roland Gontean, Aurel Politehn Univ Timisoara Fac Elect & Telecommun Dept Appl Elect Timisoara Romania

ISBN: (纸本)9781467344715

In this paper we shall present a serial driver chip creation on FPGA. We created this serial driver chip for the RS-232 interface and we programmed it to 115200 baud rate to be able to communicate with the Lynxmotion AL5 type robotic arms. This serial driver chip was made for bidirectional communication to be able to send and receive SCPI (Standard Commands for programmable Instruments) commands on the serial interface. If we create the layout of this chip we can create our own ASIC (Application-Specific Integrated Circuit) and this way we shall have a standalone chip which can control a robotic arm.

关键词： robotic arm baud rate serial I/O RS-232 interface Computer chips DNA Microarrays bidirection communication commands Drivers Serial Publications layouts field programmable gate arrays application specific integrated circuits SCRAM

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Remote Inter-Chip Power Analysis Side-Channel Attacks at Board-Level 37

Remote Inter-Chip Power Analysis Side-Channel Attacks at Boa...

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37th IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

作者： Schellenberg, Falk Gnad, Dennis R. E. Moradi, Amir Tahoori, Mehdi B. Ruhr Univ Bochum Horst Gortz Inst IT Secur Bochum Germany KIT Inst Comp Engn Karlsruhe Germany

ISBN: (纸本)9781450359504

The current practice in board-level integration is to incorporate chips and components from numerous vendors. A fully trusted supply chain for all used components and chipsets is an important, yet extremely difficult to achieve, prerequisite to validate a complete board-level system for safe and secure operation. An increasing risk is that most chips nowadays run software or firmware, typically updated throughout the system lifetime, making it practically impossible to validate the full system at every given point in the manufacturing, integration and operational life cycle. This risk is elevated in devices that run 3rd party firmware. In this paper we show that an FPGA used as a common accelerator in various boards can be reprogrammed by software to introduce a sensor, suitable as a remote power analysis side-channel attack vector at the board-level. We show successful power analysis attacks from one FPGA on the board to another chip implementing RSA and AES cryptographic modules. Since the sensor is only mapped through firmware, this threat is very hard to detect, because data can be exfiltrated without requiring inter-chip communication between victim and attacker. Our results also prove the potential vulnerability in which any untrusted chip on the board can launch such attacks on the remaining system.

关键词： field programmable gate arrays Power supplies Side-channel attacks Software Voltage measurement Supply chains

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Profiling BCI users based on contralateral activity to improve kinesthetic motor imagery detection 8

Profiling BCI users based on contralateral activity to impro...

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8th International IEEE/EMBS Conference on Neural Engineering (NER)

作者： Rimbert, Sebastien Lindig-Leon, Cecilia Bougrain, Laurent INRIA Neurosys Team F-54600 Villers Les Nancy France Univ Lorraine Artificial Intelligence & Complex Syst LORIA UMR 7503 F-54506 Vandoeuvre Les Nancy France LORIA CNRS UMR 7503 Neurosys Team F-54506 Vandoeuvre Les Nancy France

ISBN: (纸本)9781509046034

Kinesthetic motor imagery (KMI) tasks induce brain oscillations over specific regions of the primary motor cortex within the contralateral hemisphere of the body part involved in the process. This activity can be measured through the analysis of electroencephalographic (EEG) recordings and is particularly interesting for Brain-Computer Interface (BCI) applications. The most common approach for classification consists of analyzing the signal during the course of the motor task within a frequency range including the alpha band, which attempts to detect the Event-Related Desynchronization (ERD) characteristics of the physiological phenomenon. However, to discriminate right-hand KMI and left-hand KMI, this scheme can lead to poor results on subjects for which the lateralization is not significant enough. To solve this problem, we propose that the signal be analyzed at the end of the motor imagery within a higher frequency range, which contains the EventRelated Synchronization (ERS). This study found that 6 out of 15 subjects have a higher classification rate after the KMI than during the KMI, due to a higher lateralization during this period. Thus, for this population we can obtain a significant improvement of 13% in classification taking into account the users lateralization profile.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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