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2024 International Conference on Mechatronic Engineering and Artificial Intelligence, MEAI 2024

作者： Wang, Ruichuang Zhang, Minghu Feng, Zhiguang Zhou, Houping Wuhan Digital Engineering Institute Wuhan430205 China College of Intelligent Science and Engineering Harbin Engineering University Harbin150001 China

ISBN: (纸本)9781510689176

The pulse width parameter of integrated circuits is an important technical indicator for measuring the system's high-speed performance and rapid response capabilities, directly affecting the device's response speed and accuracy. Achieving traceability of integrated circuit time characteristic parameters is fundamental to ensuring the core performance of the system. The pulse width calibration device for integrated circuit testing systems calibrates the system by reproducing the behavior model of the parameters. Traditional waveform generation methods typically rely on cyclical reading of waveform memory, resulting in complex system designs, high storage resource usage, and lower waveform accuracy. To address these issues, a standard pulse width and rise/fall time waveform generation module based on an "FPGA + DAC" architecture has been designed. By directly utilizing the timing logic resources of the FPGA, multiple data modules are set up to generate waveform data in parallel, making waveform parameter adjustment more flexible and reducing waveform generation response time. Additionally, with the integration of an internal time parameter correction module, the accuracy and stability of the generated signal's time parameters are further improved, meeting the requirements for high-precision calibration. © 2025 SPIE.

关键词： Data conversion Pulse signals Clocks Calibration Integrated circuits field programmable gate arrays Signal generators Error control coding System integration Interference (communication)

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field-programmable photonic arrays

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OPTICS EXPRESS 2018年第21期26卷 27265-27278页

作者： Perez, Daniel Gasulla, Ivana Capmany, Jose Univ Politecn Valencia ITEAM Res Inst Camino Vera E-46022 Valencia Spain

We propose a new programmable integrated photonic device, the field programmable Photonic Array, which follows a similar rationale as that of field programmable gate arrays and field programmable Analog arrays in electronics. This high-level concept, basic photonic building blocks, design principles, and technology and physical implementation are discussed. Experimental evidence of its feasibility is also provided. (C) 2018 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

关键词： field programmable gate arrays Mach Zehnder interferometers Optical amplifiers Quantum information processing Semiconductor optical amplifiers Waveguide modes

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Large-Scale field-programmable Analog arrays

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PROCEEDINGS OF THE IEEE 2020年第8期108卷 1283-1302页

作者： Hasler, Jennifer Georgia Inst Technol Sch Elect & Comp Engn ECE Atlanta GA 30332 USA

Large-scale field-programmable analog array (FPAA) devices could enable ubiquitous analog or mixed-signal low-power sensor to processing devices similar to the ubiquitous implementation of the existing field-programmable gate array (FPGA) devices. Design tools enable high-level synthesis to gate/transistor design targeting today's FPGA devices and the opportunity for analog or mixed-signal applications with FPAA devices. This discussion will illustrate the FPAA concepts and FPAA history. The development of FPAAs enables the development of multiple potential metrics, and these metrics illustrate future FPAA device directions. The system-on-chip (SoC) FPAA devices illustrate the IC capabilities, computation, tools, and resulting hardware infrastructure. SoC FPAA device generation has enabled analog computing with levels of abstraction for application design.

关键词： field programmable analog arrays field programmable gate arrays Routing Computer architecture Logic gates Random access memory Analog-digital integrated circuits analog integrated circuits CMOS integrated circuits field-programmable analog arrays (FPAAs) field-programmable gate arrays (FPGAs)

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Implementing fine grain processor arrays on field-programmable logic

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INTEGRATED COMPUTER-AIDED ENGINEERING 2000年第1期7卷 53-66页

作者： Vassányi, I Univ Veszprem Dept Informat Syst H-8200 Veszprem Hungary

The structure of field programmable gate arrays (FPGAs) naturally fits that of fine grain array algorithms. The paper investigates the geometrical and layout-related implementation problems of FPGA-based processor arrays. A general methodology for implementing parametrized array processors on FPGAs is presented. Then, a detailed layout algorithm is proposed. A new feature of the algorithm is the uniform treatment of inter- and intra-module nets that allows the layout of the basic processor to be optimized with respect to the critical path of the whole, arbitrarily large processor array. The approach is demonstrated on a massively parallel processor array for binary morphology.

关键词： ARRAY PROCESSORS PROCESSOR massively parallel processors Formal logic field programmable gate arrays placement algorithm microparticles algorithms layouts

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Long-gauge ultra-weak FBG strain sensor insensitive to structural defects: numerical simulation and experimental verification

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Optics Express 2025年第11期33卷 24098-24113页

作者： Jianjun Pan Wei Hou Jinpeng Jiang Yan Yang Yaerken Alifu Jingling Hu Chang Liu National Engineering Research Center of Fiber Optic Sensing Technology and Networks Wuhan University of Technology Wuhan 430070 China School of Information Engineering Wuhan University of Technology Wuhan 430070 China

Strain monitoring of concrete structures with surface defects and material inhomogeneity is a challenge in the field of structural monitoring. In this paper, based on the characteristics of long-gauge structure and ultra-weak fiber Bragg grating (UWFBG) array, a strain sensor array with long distance and low requirement for structural surface flatness is proposed. The main measurement principle of the sensor is to convert the continuous strain of the measured structure into the average strain of each UWFBG, which can suppress the strain mutation phenomenon caused by structural defects. In the simulation, the long-gauge sensor can effectively reduce the interference of the defect on the strain data, and the sensitivity of the sensor to the structural defect gradually decreases with the increase of the gauge length. In the experimental tests, the sensor proposed in this paper can accurately reflect the surface strain field distribution and the overall deformation of the concrete structure compared with the traditional point-type fiber Bragg grating (FBG) sensor.

关键词： Composite materials Fiber Bragg grating sensors Fiber Bragg gratings field programmable gate arrays Finite element method Numerical simulation

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A Very Compact and a Threshold Implementation of uBlock for Internet of Things

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Tsinghua Science and Technology 2025年第5期30卷 2270-2283页

作者： Botao Liu Ming Tang Key Laboratory of Aerospace Information Security and Trusted Computing of Ministry of Education School of Cyber Science and Engineering Wuhan University Wuhan China

The rapid proliferation of Internet of Things (IoT) devices necessitates lightweight cryptographic algorithms and their secure physical implementations. Masking, as a provably secure countermeasure against Side-Channel Attacks (SCA), has been extensively studied in the context of lightweight cryptography algorithms. Currently, some cryptographers have proposed a low-cost Threshold Implementation (TI) of the uBlock algorithm. However, their approach suffers from significant area overhead due to the inefficient serial and pipelined implementation of uBlock's Pshufb-Xor (PX) network structure. To address this issue, we develop a new serial and pipelined implementation method that optimizes the area of the uBlock algorithm. Based on this optimization, we implement a 2-share TI scheme for uBlock that requires minimal area resources and does not need fresh randomness. Compared to the state-of-the-art appoach, our method reduces slice area by 63.4% on field programmable gate arrays (FPGA) platform and gate Equivalent (GE) area by 17.2% on Application-Specific Integrated Circuit (ASIC) platform for the unprotected implementation. For the protected implementation, our method reduces slice area by 41.5% and GE area by 14.0%. Finally, our protection scheme is validated using the automated tool PROLEAD and evaluated with Test Vector Leakage Assessment (TVLA), achieving first-order glitch-extended probing security.

关键词： Buildings Side-channel attacks Logic gates Germanium Vectors Hardware Internet of Things Protection field programmable gate arrays Optimization

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130+ ps Coincident Time Resolution With 20-mm Crystal Length Using 28-nm Xilinx FPGA

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IEEE TRANSACTIONS ON RADIATION AND PLASMA MEDICAL SCIENCES 2025年第1期9卷 1-10页

作者： Wang, Fei Zhou, Jiawen Weng, Ziyi Cai, Chao Xie, Qingguo Huazhong Univ Sci & Technol Coll Life Sci & Technol Wuhan 430074 Peoples R China

The coincidence time resolution (CTR) is of paramount importance in positron emission tomography (PET) as it can directly determine the imaging resolution. In this article, a 130+ ps CTR with 20-mm crystal length is achieved using AMD FPGA platform. Three steps are proposed to achieve a high CTR. First, a low-noise amplifier (LNA) is used on fast output signals that are used for time sampling. This can equivalently lower the configured threshold for leading edge discriminator and therefore further mitigate the time walk effect. Second, a new time-to-digital converter (TDC) architecture that achieves less than 1-LSB integral nonlinearity (INL) and differential nonlinearity (DNL) without any calibration tricks are introduced. This TDC can yield salient INL performance, which can deliver consistent performance in time sampling and hence better CTR. Last but not least, a resource-efficient energy characterization method is proposed. This approach utilizes only one TDC chain to sample all trigger times for pulse reconstruction. This not only saves up to 75% chain resources but also minimizes sampling errors due to heterogeneity properties when involving multiple TDC chains. A prototype using 28-nm Kintex 7 FPGA is implemented and 130+ ps CTR is achieved.

关键词： Crystals Standards Positron emission tomography field programmable gate arrays Plasmas Linearity Image resolution Coincident time resolution (CTR) FPGA time-to-digital converter (TDC)

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Hierarchical Embedded System Based on FPGA for Classification of Respiratory Diseases

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IEEE Access 2025年 13卷 93017-93032页

作者： Trong-Thanh Han Kien Le Trung Phuong Nguyen Anh Anh Do Trung School of Electrical and Electronic Engineering Hanoi University of Science and Technology Hanoi Vietnam Department of Science and Technology Management and International Cooperation Posts and Telecommunications Institute of Technology Hanoi Vietnam

Objectives: This research aims to design and develop a hierarchical embedded system that utilizes respiratory sound features for diagnosing COPD and other respiratory disorders. The system is engineered to achieve high accuracy and efficiency while minimizing energy consumption, making it suitable for deployment in mobile devices or embedded systems. Methods: Lung sounds are segmented into individual breathing cycles. Thirty-nine main respiratory features in the time and frequency domains are extracted and organized into four layers. The Random Forest algorithm and Artificial Neural Network are fine-tuned with the dataset and applied to disease classification. The first layer contains recorded information, while the second and third layers contain features extracted from fixed-length sound segments classified via Random Forest. The fourth layer utilizes Wavelet Transform to convert breathing patterns into Spectrogram images, which the Artificial Neural Network processes for disease diagnosis. The system is implemented on the Xilinx PYNQ-Ultra96-V2 FPGA development board. Results: The system achieves the highest accuracy of 98.81% for five disease classes: COPD, Healthy, URTI, Bronchitis, and Pneumonia, and saves 52.5% of energy consumption compared to CPU-GPU-based traditional methods. Conclusion: This study demonstrates the effectiveness of the proposed method in diagnosing COPD and other respiratory disorders. The hierarchical embedded system is designed with high accuracy and energy efficiency, with potential real-world applications to support clinical diagnosis.

关键词： Feature extraction Mel frequency cepstral coefficient Chronic obstructive pulmonary disease Accuracy Lungs field programmable gate arrays Support vector machines Convolutional neural networks Classification algorithms Machine learning

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Fault Detection in Blowfish Algorithm Using FPGA-Based Modified Decision Tree Approach

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IEEE Access 2025年 13卷 90591-90600页

作者： Joseph Anthony Prathap Mithileysh Sathiyanarayanan Department of Electrical and Electronic Engineering City St George’s University of London London England U.K.

This research article identifies the fault occurrence in the blowfish cryptography algorithm using a modified Decision Tree classifier. Though there are several cryptography algorithms, the symmetric blowfish algorithm is considered for its high performance, compatibility, security, and ease of implementation. When utilized in real applications, the attack in the bit transmission either at the encryption or at the decryption might affect its authentication and security. This demands automatic fault identification within the blowfish algorithm using a modified Decision tree. This work includes attack induction and identification of the same using the developed modified decision tree-based equality checker circuit. The proposed method involves the development of an equality-checker-based decision tree algorithm to form 12 sections for the 16 iterations from the encryption and decryption process of the blowfish algorithm. The FPGA device implements the proposed method to validate the real-time feasibility. Also, the System on Chip IC layout is developed for the proposed method to analyze the parameters of power and area using the EDA tools. The utilization of FPGA in indicating the attack of the blowfish algorithm is evaluated for its high-performance capability that has low latency and higher throughput for the 64-bit design resolution.

关键词： Encryption Decision trees S Box field programmable gate arrays Fault diagnosis Ciphers Security Real-time systems Hardware Circuit faults

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Integrated lithium niobate photonics for high-speed quantum key distribution

Optica Quantum

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Optica Quantum 2025年第2期3卷 195-200页

作者： Zhihao Lin Yuanfei Gao Lai Zhou Huihong Yuan Yuntao Zhu Zhongjin Lin Wei Zhang Yidong Huang Xin-Lun Cai Zhiliang Yuan Beijing Academy of Quantum Information Sciences Beijing 100193 China Department of Electronic Engineering Tsinghua University Beijing 100084 China State Key Laboratory of Optoelectronic Materials and Technologies School of Electronics and Information Technology Sun Yat-Sen University Guangzhou 510275 China

Photonic integration in quantum communication holds significant potential for miniaturization and enabling commercial applications. Among various platforms, thin-film lithium niobate (TFLN) stands out due to its exceptional combination of high electro-optical efficiency, low propagation loss, and compact footprint. Here, we demonstrate a 2.5 GHz chip-to-chip fully integrated quantum key distribution (QKD) system based on a TFLN platform, which incorporates high-speed dual-polarization time-bin phase encoding and decoding functionalities. We achieve an extremely low quantum bit error rate of 0.53% and a secret key rate exceeding 10 Mbps over 25 km fiber spools. The design of cascaded Mach–Zehnder modulators effectively suppresses the patterning effect in high speed QKD. Notably, the TFLN chips used in both the transmitter and receiver share a similar architecture, highlighting the potential for creating a homogeneous transceiver. This work paves the way for high-speed, miniaturized QKD systems based on the lithium niobate integrated platform.

关键词： field programmable gate arrays Integrated photonics Lithium niobate Phase modulation Quantum key distribution Semiconductor lasers

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