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FQsun: A Configurable Wave Function-Based Quantum Emulator for Power-Efficient Quantum Simulations

IEEE Access 2025年 13卷 93271-93286页

作者： Tuan Hai Vu Vu Trung Duong Le Hoai Luan Pham Quoc Chuong Nguyen Yasuhiko Nakashima Nara Institute of Science and Technology Ikoma Nara Japan Department of Mathematics University at Buffalo Buffalo NY USA

Quantum computers are promising powerful computers for solving complex problems, but access to real quantum hardware remains limited due to high costs. Although software simulators like Qiskit, ProjectQ, and Pennylane offer flexibility and support for many qubits, they struggle with high power consumption and limited processing speed, particularly as qubit counts increase. Accordingly, quantum emulators implemented on dedicated hardware, such as FPGAs and analog circuits, offer a promising path for addressing energy efficiency concerns. However, existing studies on hardware-based emulators still face challenges in terms of limited flexibility and lack of fidelity evaluation. To overcome these gaps, we propose FQsun, a wave function-based quantum emulator that enhances performance by integrating four key innovations: efficient memory organization, a configurable Quantum gate Unit (QGU), optimized scheduling, and five number precisions implemented on the Xilinx ZCU102. Experimental results demonstrate high fidelity, low mean square error, and high normalized gate speed, particularly with 32-bit versions. Benchmarking on Random Quantum Circuits, Quantum Fourier Transform, and Parameter-Shift Rule reveals that FQsun achieves a superior power-delay product and precisely, outperforms software simulators on CPUs in the processing speed range.

关键词： Logic gates Quantum computing Hardware Qubit Software Quantum circuit field programmable gate arrays Computers Vectors Energy efficiency

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Tools for Analyzing Signature-Based Hardware Solutions for Cyber Security Systems

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Journal of Cyber Security and Mobility 2025年第3期12卷 339-366页

作者： Serhii Ya. Hilgurt Anatolii M. Davydenko Tetyana V. Matovka Mykhailo P. Prygara Department of Mathematical and Econometric Modelling G.E. Pukhov Institute for Modelling in Energy Engineering of the National Academy of Sciences of Ukraine Ukraine Department of Finance and Banking Uzhhorod National University Ukraine Department of Machine Industry Technology Uzhhorod National University Ukraine

When creating signature-based cybersecurity systems for network intrusion detection (NIDS), spam filtering, protection against viruses, worms, etc., developers have to use hardware devices such as field programmable gate arrays (FPGA), since software solutions can no longer support the necessary speeds. There are many different approaches to build hardware circuits for pattern matching (where patterns are the parts of signatures). Choosing the optimal technical solution for certain conditions is not a trivial task. Developers of such hardware tend to act intuitively, heuristically. In this arti-cle, we provide tools to help them intelligently build cybersecurity systems using FPGAs. For the qualitative analysis of FPGA-based matching schemes, the classification of efficiency criteria and related indicators is considered. This classification was compiled by studying a large number of practical developments of FPGA-based cybersecurity systems, primarily NIDS. A method of rapid calculating numerical characteristics of the FPGA-based signature system components is proposed as a quantitative assessment tool. This method based on the use of so-called estimation functions allows avoiding the time-consuming execution of the digital circuit synthesis procedure. A number of experiments were carried out with the most promising matching schemes, allowing evaluating the abovementioned tools. The rapid quan-tification method allows developers of hardware-accelerated cybersecurity systems to even apply it at each iteration within the optimization procedure cycle.

关键词： Statistical analysis Network intrusion detection Logic gates Hardware Software Computer crime Protection field programmable gate arrays Pattern matching Optimization

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On the Negative Effects of Trend Noise and Its Applications in Side-Channel Cryptanalysis

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Chinese Journal of Electronics 2025年第2期23卷 366-370页

作者： Yuchen Cao Yongbin Zhou Zhenmei Yu State Key Laboratory of Information Security Institute of Information Engineering Chinese Academy of Sciences Beijing China School of Information Technology Shandong Women's University Jinan China

Most existing noise reduction methods in side-channel cryptanalysis treat all noises as a whole, instead of identifying and dealing with each of them individually. Motivated by this, this paper investigates the feasibility and implications of identifying trend noise from any other noises in side-channel acquisitions and then dealing with it accordingly. We discuss the effectiveness of applying least square method to remove inherent trend noise in side-channel leakages, and also clarify the limited capability of existing noise reduction methods in dealing with trend noise. We performed a series of correlation power analysis attacks against real power traces publicly available in DPA contest v2 from an unprotected FPGA implementation of Advanced encryption standard (AES) encryption. The experimental results firmly confirmed the soundness and validity of our analysis and observations.

关键词： Correlation Noise Noise reduction Market research Encryption Standards field programmable gate arrays Least mean squares methods

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Digital multi-wavelength optical absolute ranging

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Optics Letters 2025年第11期50卷 3764-3767页

作者： Shawn McSorley Benjamin P Dix-MatthewsAndrew M LanceDavid R Gozzard Sascha W Schediwy International Centre for Radio Astronomy Research The University of Western Australia Crawley WA 6009 Australia

Optical metrology underpins sensing applications that require extreme precision and accuracy. Optical metrology with a continuous-wave source is constrained by the near-ambiguous range of one optical wavelength, limiting the realization of full interferometric sensitivity. We present a digitally tunable, multi-wavelength continuous-wave optical phase measurement scheme, which can be used for absolute laser ranging. This system was demonstrated over a free-space link on an optical bench, with a distance uncertainty of, at best, 0.2 μm—sufficient to resolve the continuous-wave optical fringe. This design is flexible and can be applied to both coherent optical ranging and optical time and frequency transfer.

关键词： field programmable gate arrays Fringes Measurement and metrology Phase measurement Phase noise Polarization maintaining fibers

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Ph.D. Project: Floorplan Quality Prediction for HLS Design Exploration on Multi-Die FPGA

Ph.D. Project: Floorplan Quality Prediction for HLS Design E...

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Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Haoran Xue Teng Wang Chao Wang School of Computer Science and Technology University of Science and Technology of China Suzhou Institute for Advanced Research University of Science and Technology of China

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

High-level synthesis (HLS) and multi-die FPGAs are widely used for large-scale accelerators. To address the cross multi-die boundary delays and local congestion issues in HLS designs on multi-die FPGAs, a coarse-grained floorplan and pipeline method was proposed to improve frequency performance. However, achieving better frequency performance requires iterative implementation in Vitis to adjust the parameters, leading to significant time overhead. To accelerate this tuning process, this paper proposes a floorplan quality predictor based on a graph neural network for each slot on FPGA, achieving accuracy rates of 88.63% and 89.68% in high-level congestion and critical resource, respectively. Compared with the traditional tuning process, we reduce the time overhead from 7 hours to millisecond-level and achieve a 25 % improvement in WNS performance in the tuning case.

关键词： Time-frequency analysis Accuracy Pipelines Graph neural networks Delays Iterative methods field programmable gate arrays Tuning

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Fall Detection Using Sound with FPGA Signal Analysis and Machine Learning Integration

Fall Detection Using Sound with FPGA Signal Analysis and Mac...

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Machine Learning and Autonomous Systems (ICMLAS), International Conference on

作者： Mariano Viegas Andre Ahmet Turan Özdemir Erhan Kavuncuoglu Department of Electric and Electronic Engineering Erciyes University Kayseri Turkey Department of Computer Tecnology Gemerek Vocational School: Cumhuriyet University Sivas Turkey

ISBN: (数字)9798331505745

ISBN: (纸本)9798331505752

Falls represent a considerable risk to the well-being of geriatric populations, frequently resulting in injuries or mortality. In response to this pressing concern, we introduce an innovative fall detection apparatus employing acoustic sensors and FPGA (field programmable gate Array) technology to effectively alleviate these hazards. Our system capitalizes on acoustic phenomena, particularly those associated with footstep sounds and falls, which are gathered through routine activities and video documentation to develop a comprehensive model adept at differentiating between fall incidents and non-fall occurrences. The primary attributes encompass the derivation of Mel-frequency cepstral coefficients (MFCC) from the processed auditory signals. To enhance operational efficacy, an FPGA is utilized to execute all data processing functions, inclusive of Fourier transformations and a threshold-based predictive algorithm. This methodology diminishes dependence on conventional computational systems while preserving elevated processing efficiency. The derived features are subsequently employed to formulate a data classification model utilizing a Convolutional Neural Network (CNN) and Random Forest Tree (RFT), which proficiently discriminates between sounds indicative of falls and those not related to falls.

关键词： Signal processing algorithms Mortality Pressing Prediction algorithms Convolutional neural networks Fall detection Signal analysis field programmable gate arrays Random forests Sensor arrays

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Multi-Sensor Data Fusion for Enhanced Detection of Laser Fault Injection Attacks in Cryptographic Hardware: Practical Results

Multi-Sensor Data Fusion for Enhanced Detection of Laser Fau...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Mohammad Ebrahimabadi Raphael Viera Sylvain Guilley Jean-Luc Danger Jean-Max Dutertre Naghmeh Karimi University of Maryland Baltimore County United States Mines de Saint-Étienne CEA Leti Centre CMP Gardanne France Secure-IC S.A.S. France ENS Information Security Group Paris France Telecom Paris Institut Polytechnique de Paris France

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Though considered secure the cryptographic hardware can be compromised by fault injection attack, especially laser illumination due to its precision in targeting specific areas and its fine temporal control. To address this threat, this paper presents a low-cost detection scheme that utilizes Time-to-Digital Converters (TDCs) to sense the IR drops induced by laser illumination. To achieve a high detection rate while minimizing false alarms, the proposed approach incorporates multiple sensors, with as few as two sensors demonstrated in the study. The effectiveness of the scheme is validated using a real laser setup to illuminate a targeted AES module implemented on an AMD/Xilinx Artix-7 FPGA.

关键词： Semiconductor lasers Lighting Europe Data integration Hardware Sensors Cryptography Laser fusion field programmable gate arrays

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A new architecture of field programmable analog arrays for reconfigurable instantiation of continuous-time filters

A new architecture of field programmable analog arrays for r...

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3rd International Conference on field-programmable Technology

作者： Becker, J Manoli, Y Univ Freiburg Chair Microelect IMTEK D-79110 Freiburg Germany

ISBN: (纸本)0780386515

A new methodology of field programmable analog arrays (FPAAs) is presented, which is particulary designed as hardware platform for the instantiation of continuous-time (CT) adaptable filters. The array topology consists of 17 digitally configurable analog blocks (CABs) connected through a hexagonal interconnect network. Each CAB is built of tunable G(m)-C integrators, which provide both routing and shaping of the analog signal and are the building blocks for high-speed continuous-time filters. Intelligent IO-buffers provide reconfiguration of the array with minimal disturbance of the continuous analog signal. The architecture is introduced and reviewed as hardware platform for any circuit that consists of the given number of G(m)-C cells and an exemplary instantiation of a 4(th) order biquad Butterworth filter is shown.

关键词： field programmable gate arrays

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Efficient and Distributed Computation of Electron Repulsion Integrals on AMD AI Engines

Efficient and Distributed Computation of Electron Repulsion ...

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Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Johannes Menzel Christian Plessl Department of Computer Science Paderborn Center for Parallel Computing Paderborn University Paderborn Germany

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

Computing electron repulsion integrals (ERIs) is the major computational bottleneck of many quantum mechanical simulation methods, requiring trillions of ERI evaluations per time step. While the computation of independent ERIs is embarrassingly parallel, the efficient computation of individual ERIs on modern processor cores is difficult due to both an insufficient cache size for intermediates of the computation and irregular memory access patterns that are difficult to vectorize. In this paper, we present how our implementation on the AI Engine (AIE) architecture addresses both of these problems. First, we have defined a flexible graph structure, which we call an ERI-Engine, that can be implemented for all 231 canonical ERI quartets from {ss|ss} to {hh| hh} by distributing the computation over 2–14 AIEs. Second, for the larger quartets, we have devised a novel vectorization scheme that leverages the advanced floating-point unit of the AIEs, while also supporting vectorization of independent ERIs for the smaller quartets. Finally, ERI-Engines are horizontally and vertically stackable to fill the entire AIE array, and in particular, the vertically stacked ERI-Engines form a column that uses one or more time-shared channels to stream the results out of the AIE array, almost completely hiding the computational phases of individual ERI-Engines. In terms of absolute performance, we are competitive with recent high-performance implementations of ERI algorithms on FPGAs (SERI) and GPUs (LibintX), as well as well-established highly optimized CPU libraries (Libint, Libcint), while being the unequivocal leader in terms of energy efficiency.

关键词： Phased arrays Quantum computing Memory management Quantum mechanics Libraries Computational efficiency Artificial intelligence Engines field programmable gate arrays Electrons

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A moving least-square approach for current slope estimation in an inverter fed IPMSM using field programmable gateway arrays

A moving least-square approach for current slope estimation ...

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24th International Conference on Electrical Machines (ICEM)

作者： Degel, J. P. Haehnlein, S. Kloeffer, C. Doppelbauer, M. Karlsruhe Inst Technol KIT Chair Elect Tech Inst ETI Karlsruhe Germany Hsch Offenburg Fac Elect Engn Med Technol & Comp Sci EMI Offenburg Germany

ISBN: (纸本)9781728199450

In this work a method for the estimation of current slopes induced by inverters operating interior permanent magnet synchronous machines is presented. After the derivation of the estimation algorithm, the requirements for a suitable sensor setup in terms of accuracy, dynamic and electromagnetic interference are discussed. The boundary conditions for the estimation algorithm are presented with respect to application within high power traction systems. The estimation algorithm is implemented on a field programmable gateway array. This moving least-square algorithm offers the advantage that it is not dependent on vectors and therefore not every measured value has to be stored. The summation of all measured values leads to a significant reduction of the required storage units and thus decreases the hardware requirements. The algorithm is designed to be calculated within the dead time of the inverter. Appropriate countermeasures for disturbances and hardware restrictions are implemented. The results are discussed afterwards.

关键词： AC machines Current control Current measurement Estimation field programmable gate arrays Measurement Monitoring Parameter estimation Predictive models

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