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检索条件"主题词=Field Programmable Gate Arrays"

共 41626 条记录，以下是521-530 订阅

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RealProbe: An Automated and Lightweight Performance Profiler for In-FPGA Execution of High-Level Synthesis Designs

RealProbe: An Automated and Lightweight Performance Profiler...

引用

Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Jiho Kim Cong Hao School of Electrical and Computer Engineering Georgia Institute of Technology

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

High-level synthesis (HLS) accelerates FPGA design by rapidly generating diverse implementations using optimization directives. However, even with cycle-accurate C/RTL co-simulation, the reported clock cycles often differ significantly from actual FPGA performance. This discrepancy hampers accurate bottleneck identification, leading to suboptimal design choices. Existing in-FPGA profiling tools, such as the Integrated Logic Analyzer (ILA), require tedious inspection of HLS-generated RTL and manual signal monitoring, reducing productivity. To address these challenges, we introduce RealProbe, the first fully automated, lightweight in-FPGA profiling tool for HLS designs. With a single directive-#pragma HLS RealProbe-the tool automatically generates all necessary code to profile cycle counts across the full function hierarchy, including submodules and loops. RealProbe extracts, records, and visualizes cycle counts with high precision, providing actionable insights into on-board performance. RealProbe is non-intrusive, implemented as independent logic to ensure minimal impact on kernel functionality or timing. It also supports automated design space exploration (DSE), optimizing resource allocation based on FPGA constraints and module complexity. By leveraging incremental synthesis and implementation, DSE runs independently of the original HLS kernel. Evaluated across 28 diverse test cases, including a large-scale design, RealProbe achieves 100% accuracy in capturing cycle counts with minimal logic overhead-just 16.98% LUTs,43.15% FFs, and 0% BRAM usage. The tool, with full documentation and examples, is available on GitHub 1 1 https://***/sharc-lab/RealProbe.

关键词： Visualization Accuracy Random access memory Bandwidth Timing Space exploration Logic Kernel Usability field programmable gate arrays

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RapidPnR: Accelerating the Physical Design for FPGAs via Design-Level Parallelism

RapidPnR: Accelerating the Physical Design for FPGAs via Des...

引用

Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Wanzheng Weng Pingqiang Zhou School of Information Science and Technology ShanghaiTech University Shanghai China

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

The runtime of physical design has become a critical issue for FPGA development as the scale and complexity of circuit designs surge with the increasing logic capacity of FPGA devices. The time-consuming process of physical design significantly extends the cycle of design iteration, which heavily impacts the efficiency of debugging and architecture optimization. To address this issue, this work proposes a generic, fully-automated and split-and-parallel physical design flow to accelerate the deployment of large-scale circuits on FPGAs. Specifically, our flow automatically partitions the synthesized netlist into multiple smaller pieces, performs parallel physical design of each piece, and then merges them into the complete design. Evaluated on a set of real circuit benchmarks, our flow reduces the runtime by more than 50% and ensures nearly the same design frequency compared to the physical design flow provided by the commercial tool Vivado.

关键词： Runtime Debugging Computer architecture Parallel processing Routing Logic Surges field programmable gate arrays Optimization Physical design

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Demonstration of a Clock Distribution Method using Switching Matrices and a Two-Phase Clock Signal on an FPGA

Demonstration of a Clock Distribution Method using Switching...

引用

IEEE International Conference on Consumer Electronics (ICCE)

作者： Ayumu Ogura Minoru Watanabe Nobuya Watanabe Information Technology Track Information Technology Electrical Engineering and Mathematical and Data Sciences Program Faculty of Engineering Okayama University Okayama Japan

ISBN: (数字)9798331521165

ISBN: (纸本)9798331521172

Very large-scale Integrations (VLSIs) are vulnerable to radiation, and VLSIs used in high radiation environments such as space environment and nuclear power plants have a short lifetime. Therefore, we are developing radiation-hardened optically reconfigurable gate arrays. Conventional optically reconfigurable gate array VLSIs have a weak point in clock distribution. This problem can be solved by a new clock distribution exploiting reconfigurable switching matrices. However, in this case, the clock skew increases. Therefore, to solve this problem, this paper proposes a new clock distribution method using a two-phase clock signal and switching matrices on an optically reconfigurable gate array VLSI. The proposed clock distribution method has been demonstrated on a Cyclone V FPGA by using a 4-bit counter circuit. This paper presents the demonstration results.

关键词： Integrated optics Optical switches Radiation detectors Logic gates Very large scale integration Adaptive optics field programmable gate arrays Power generation Clocks Optical arrays

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Design of an FPGA-Based Neutral Atom Rearrangement Accelerator for Quantum Computing

Design of an FPGA-Based Neutral Atom Rearrangement Accelerat...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Xiaorang Guo Jonas Winklmann Dirk Stober Amr Elsharkawy Martin Schulz Chair of Computer Architecture and Parallel Systems Technical University of Munich Garching Germany

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Neutral atoms have emerged as a promising technology for implementing quantum computers due to their scalability and long coherence times. However, the execution frequency of neutral atom quantum computers is constrained by image processing procedures, particularly the assembly of defect-free atom arrays, which is a crucial step in preparing qubits (atoms) for execution. To optimize this assembly process, we propose a novel quadrant-based rearrangement algorithm that employs a divide-and-conquer strategy and also enables the simultaneous movement of multiple atoms, even across different columns and rows. We implement the algorithm on field programmable gate arrays (FPGAs) to handle each quadrant independently (hardware-level optimization) while maximizing parallelization. To the best of our knowledge, this is the first hardware acceleration work for atom rearrangement, and it significantly reduces the processing time. This achievement also contributes to the ongoing efforts of tightly integrating quantum accelerators into High-Performance Computing (HPC) systems. Tested on a Zynq RFSoC FPGA at 250 MHz, our hardware implementation is able to complete the rearrangement process of a 30 × 30 compact target array, derived from a 50 × 50 initial loaded array, in approximately 1.0 μs. Compared to a comparable CPU implementation and to state-of-the-art FPGA work, we achieved about 54 x and 300 x speedups in the rearrangement analysis time, respectively. Additionally, the FPGA-based acceleration demonstrates good scalability, allowing for seamless adaptation to varying sizes of the atom array, which makes this algorithm a promising solution for large-scale quantum systems.

关键词： Computers Schedules Quantum system Quantum computing Scalability Qubit Atoms Central Processing Unit field programmable gate arrays Assembly

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ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis

ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Sy...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Hongyang Pan Keren Zhu Fan Yang Zhufei Chu Xuan Zeng State Key Lab of Integrated Circuits and Systems School of Microelectronics Fudan University Shanghai China Faculty of Electrical Engineering and Computer Science Ningbo University Ningbo China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Mapping to $k$ -input lookup tables ( $k$ -LUTs) is a critical process in field-programmable gate array (FPGA) synthesis. However, the structure of the subject graph can introduce structural bias, which refers to the dependency of mapping results on the inherent graph structure, often leading to suboptimal results. To address this, we present ELMap, an area-driven LUT mapping framework. It incorporates structural choice during the collapsing phase. This enables dynamic decomposition, maximizing local-to-global optimization transfer. To ensure seamless integration between the optimization and mapping processes, ELMap leverages exact $k$ -LUT synthesis to generate area-optimal sub-LUT networks. Experiments on the EPFL benchmark suite demonstrate that ELMap significantly outperforms state-of-the-art methods. Specifically, in 6-LUT mapping, ELMap reduces the average LUT area by 8.5% and improves the area-depth-product (ADP) by 5.8%. In 4-LUT remapping, it reduces the average LUT area by 17.6% and improves the ADP by 2.4%.

关键词： Europe Benchmark testing Table lookup Logic Optimization field programmable gate arrays

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Upgate: Low-Power and Secure Over-the-Air Hardware Reconfiguration for Deployed FPGAs

UpGate: Low-Power and Secure Over-the-Air Hardware Reconfigu...

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International Conference on Intelligence in Next Generation Networks (ICIN)

作者： Alexandre Abadie Alfonso Cortes-Neira Thomas Watteyne Filip Maksimovic Inria France

ISBN: (数字)9798331542399

ISBN: (纸本)9798331542405

Attaching field-programmable gate arrays to microcontrollers deployed in the field can increase their potential applications. Making these systems reconfigurable post-deployment effectively makes them future-proof, allowing maintenance and updating of firmware in distributed computing applications. This paper presents Upgate, an embedded software that can securely perform an over-the-air update of an FPGA's function with minimal communication overhead, enabling complete flexibility of the device's functionality. Several benchmarks are performed using simple to complex hardware designs for in-depth analysis of memory footprint, timing, and power consumption. The results show that regular lossless compression techniques, such as GZip and LZ4, with 80% compression rate in the worst case, are reducing the global binary update duration by at least 4 times. This represents 15 times less 128 B packets transmitted, and approximately 40 s to transfer a RISC-V core bitstream of 579 kB. Surprisingly, what takes the most time and energy is writing to flash.

关键词： Performance evaluation Technological innovation Power demand Microcontrollers Wireless networks Writing Hardware Timing field programmable gate arrays Microprogramming

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Digital Self-Interference Cancellation in Wideband Star Radio Using an Auxiliary Receiver

Digital Self-Interference Cancellation in Wideband Star Radi...

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IEEE Annual Conference on Wireless and Microwave Technology (WAMICON)

作者： Kefayet Ullah Satheesh Bojja Venkatakrishnan John L. Volakis Department of Electrical and Computer Engineering Florida International University Radio-Frequency Communications & Terahertz Laboratory (RFCOM) Miami USA

ISBN: (数字)9798331509606

ISBN: (纸本)9798331509613

This paper presents a novel digital self-interference cancellation (DSIC) technique in full-duplex radios supporting simultaneous transmission and reception (STAR). Key to the design approach is the development of a behavioral model of the full-duplex radio front-end at the digital baseband. An auxiliary receiver (RX) chain is deployed to capture the transmitter (TX) chain and the leakage channel response. The leaked signal is digitally reconstructed and analog cancellation is performed at the low-noise amplifier (LNA) input to prevent desensitization. The cancellation algorithm is developed on a $16-\text{nm}$ AMDXilinx radio frequency system-on-chip (RFSoC) incorporating gigasample speed data converters and field programmable gate array (FPGA) on the same chip. The architecture is directly implemented on the programmable logic (PL) and the model coefficients are calculated offline in the ARM processor of the SoC. The hardware demonstration employs a reduced number of off-the-shelf analog components that provide an impressive digital cancellation of 20 dB for a maximum modulation bandwidth of 400 MHz.

关键词： Wireless communication Interference cancellation Auxiliary transmitters Radio transmitters Stars Modulation Receivers Full-duplex system Wideband field programmable gate arrays

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Review of Lightweight Cryptographic Algorithm: NIST Requirement and Practical Implementation

Review of Lightweight Cryptographic Algorithm: NIST Requirem...

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Artificial Intelligence and Data Engineering (AIDE), International Conference on

作者： Suhan Rai K Sushma Reshma S Karthik Mahantesh Herur Kiran Kumar V G Prakash K Shetty Department of Electronics and Communication A J Institute of Engineering and Technology Kottara Mangaluru India

ISBN: (数字)9798331527518

ISBN: (纸本)9798331527525

The technological development has increased the requirement for robust security measures to protect the information. Many new security concerns arise as a result of the transition from high-end devices, like desktop computers, servers, and laptops, to smaller devices with limited resources. A number of these devices, such as smart cards, RFID tags, and wireless sensors, require secure ways of storing, accessing, and transmitting vital data. The primary objective of lightweight cryptography is to provide cryptographic algorithms that are tailored for these kinds of limited environments. This paper discusses the principles of lightweight cryptography, the requirements set forth by NIST for these algorithms, and their practical implementations on platforms like FPGAs.

关键词： Wireless communication Wireless sensor networks Smart cards Portable computers Reviews NIST Cryptography Servers RFID tags field programmable gate arrays

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FPGA-Based Real-Time Data Acquisition and Transmission Using Ethernet UDP: Application of MCSA for Induction Motor Diagnosis

FPGA-Based Real-Time Data Acquisition and Transmission Using...

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iNnovative Informatics of Biskra (ISNIB), International Symposium on

作者： Salim Hamouda Samir Hamdani Hamid Khelfi Electrical Engineering Department University of Science and Technology Houari Boumediene Algiers Algerer

ISBN: (数字)9798331509576

ISBN: (纸本)9798331509583

In industrial applications, using Ethernet for data communication has become increasingly important due to its high speed, reliability, and ability to handle large volumes of data. This paper presents the development of a real-time data acquisition and transmission system utilizing FPGA technology and Ethernet UDP protocol, designed explicitly for Motor Current Signature Analysis (MCSA) in induction motor diagnosis. The system incorporates an external ADC (AD7606) for high-precision data acquisition controlled by an FPGA architecture. The acquired data is then transmitted to a PC via an Ethernet module (W5500) using the UDP protocol. A user-friendly graphical user interface (GUI) is developed to display the results, facilitating real-time monitoring and analysis. This implementation provides an efficient and reliable solution for real-time motor current signature analysis, enabling accurate diagnosis of various induction motor faults through MCSA. Experimental results validate the system's effectiveness in accurately diagnosing induction motor faults.

关键词： Induction motors Protocols Data acquisition Ethernet Real-time systems Reliability Data communication Informatics field programmable gate arrays Graphical user interfaces

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HBMex: An Attachment for Nonbursting Accelerators to Enhance HBM Performance

HBMex: An Attachment for Nonbursting Accelerators to Enhance...

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Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Canberk Sönmez Mohamed Shahawy Paolo Ienne École Polytechnique Fédérale de Lausanne Lausanne Switzerland

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

Modern FPGAs integrate High Bandwidth Memory (HBM), offering up to 12× the DDR bandwidth distributed across multiple memory interfaces. To utilize the most of HBM's theoretical bandwidth, accelerators typically issue long bursts and exploit data locality. However, some applications like sparse matrix-vector multiplication (SpMV) and graph analytics often exhibit irregular, nonbursting memory access patterns, which hinder performance. Additionally, the HBM interconnect, essential for accessing multiple interfaces, may stall requests under certain conditions. This work introduces HBMex, a novel module designed to enhance HBM throughput for accelerators with irregular access patterns. Positioned between the accelerator and the HBM, HBMex improves parallelism by distributing memory requests across interfaces and mitigates stalls caused by the interconnect. We evaluate HBMex using memory access microbenchmarks and an SpMV accelerator, demonstrating throughput gains of up to 37% across real-world workloads compared to vendor-provided solutions. HBMex is distributed as a highly-configurable and open-source RTL generator.

关键词： Bandwidth Parallel processing Benchmark testing Throughput Generators Sparse matrices field programmable gate arrays Clocks

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