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检索条件"主题词=Field Programmable Gate Arrays"

共 41642 条记录，以下是531-540 订阅

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Ph.D. Project: Floorplan Quality Prediction for HLS Design Exploration on Multi-Die FPGA

Ph.D. Project: Floorplan Quality Prediction for HLS Design E...

引用

Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Haoran Xue Teng Wang Chao Wang School of Computer Science and Technology University of Science and Technology of China Suzhou Institute for Advanced Research University of Science and Technology of China

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

High-level synthesis (HLS) and multi-die FPGAs are widely used for large-scale accelerators. To address the cross multi-die boundary delays and local congestion issues in HLS designs on multi-die FPGAs, a coarse-grained floorplan and pipeline method was proposed to improve frequency performance. However, achieving better frequency performance requires iterative implementation in Vitis to adjust the parameters, leading to significant time overhead. To accelerate this tuning process, this paper proposes a floorplan quality predictor based on a graph neural network for each slot on FPGA, achieving accuracy rates of 88.63% and 89.68% in high-level congestion and critical resource, respectively. Compared with the traditional tuning process, we reduce the time overhead from 7 hours to millisecond-level and achieve a 25 % improvement in WNS performance in the tuning case.

关键词： Time-frequency analysis Accuracy Pipelines Graph neural networks Delays Iterative methods field programmable gate arrays Tuning

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Fall Detection Using Sound with FPGA Signal Analysis and Machine Learning Integration

Fall Detection Using Sound with FPGA Signal Analysis and Mac...

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Machine Learning and Autonomous Systems (ICMLAS), International Conference on

作者： Mariano Viegas Andre Ahmet Turan Özdemir Erhan Kavuncuoglu Department of Electric and Electronic Engineering Erciyes University Kayseri Turkey Department of Computer Tecnology Gemerek Vocational School: Cumhuriyet University Sivas Turkey

ISBN: (数字)9798331505745

ISBN: (纸本)9798331505752

Falls represent a considerable risk to the well-being of geriatric populations, frequently resulting in injuries or mortality. In response to this pressing concern, we introduce an innovative fall detection apparatus employing acoustic sensors and FPGA (field programmable gate Array) technology to effectively alleviate these hazards. Our system capitalizes on acoustic phenomena, particularly those associated with footstep sounds and falls, which are gathered through routine activities and video documentation to develop a comprehensive model adept at differentiating between fall incidents and non-fall occurrences. The primary attributes encompass the derivation of Mel-frequency cepstral coefficients (MFCC) from the processed auditory signals. To enhance operational efficacy, an FPGA is utilized to execute all data processing functions, inclusive of Fourier transformations and a threshold-based predictive algorithm. This methodology diminishes dependence on conventional computational systems while preserving elevated processing efficiency. The derived features are subsequently employed to formulate a data classification model utilizing a Convolutional Neural Network (CNN) and Random Forest Tree (RFT), which proficiently discriminates between sounds indicative of falls and those not related to falls.

关键词： Signal processing algorithms Mortality Pressing Prediction algorithms Convolutional neural networks Fall detection Signal analysis field programmable gate arrays Random forests Sensor arrays

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Multi-Sensor Data Fusion for Enhanced Detection of Laser Fault Injection Attacks in Cryptographic Hardware: Practical Results

Multi-Sensor Data Fusion for Enhanced Detection of Laser Fau...

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Mohammad Ebrahimabadi Raphael Viera Sylvain Guilley Jean-Luc Danger Jean-Max Dutertre Naghmeh Karimi University of Maryland Baltimore County United States Mines de Saint-Étienne CEA Leti Centre CMP Gardanne France Secure-IC S.A.S. France ENS Information Security Group Paris France Telecom Paris Institut Polytechnique de Paris France

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Though considered secure the cryptographic hardware can be compromised by fault injection attack, especially laser illumination due to its precision in targeting specific areas and its fine temporal control. To address this threat, this paper presents a low-cost detection scheme that utilizes Time-to-Digital Converters (TDCs) to sense the IR drops induced by laser illumination. To achieve a high detection rate while minimizing false alarms, the proposed approach incorporates multiple sensors, with as few as two sensors demonstrated in the study. The effectiveness of the scheme is validated using a real laser setup to illuminate a targeted AES module implemented on an AMD/Xilinx Artix-7 FPGA.

关键词： Semiconductor lasers Lighting Europe Data integration Hardware Sensors Cryptography Laser fusion field programmable gate arrays

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A new architecture of field programmable analog arrays for reconfigurable instantiation of continuous-time filters

A new architecture of field programmable analog arrays for r...

引用

3rd International Conference on field-programmable Technology

作者： Becker, J Manoli, Y Univ Freiburg Chair Microelect IMTEK D-79110 Freiburg Germany

ISBN: (纸本)0780386515

A new methodology of field programmable analog arrays (FPAAs) is presented, which is particulary designed as hardware platform for the instantiation of continuous-time (CT) adaptable filters. The array topology consists of 17 digitally configurable analog blocks (CABs) connected through a hexagonal interconnect network. Each CAB is built of tunable G(m)-C integrators, which provide both routing and shaping of the analog signal and are the building blocks for high-speed continuous-time filters. Intelligent IO-buffers provide reconfiguration of the array with minimal disturbance of the continuous analog signal. The architecture is introduced and reviewed as hardware platform for any circuit that consists of the given number of G(m)-C cells and an exemplary instantiation of a 4(th) order biquad Butterworth filter is shown.

关键词： field programmable gate arrays

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Efficient and Distributed Computation of Electron Repulsion Integrals on AMD AI Engines

Efficient and Distributed Computation of Electron Repulsion ...

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Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Johannes Menzel Christian Plessl Department of Computer Science Paderborn Center for Parallel Computing Paderborn University Paderborn Germany

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

Computing electron repulsion integrals (ERIs) is the major computational bottleneck of many quantum mechanical simulation methods, requiring trillions of ERI evaluations per time step. While the computation of independent ERIs is embarrassingly parallel, the efficient computation of individual ERIs on modern processor cores is difficult due to both an insufficient cache size for intermediates of the computation and irregular memory access patterns that are difficult to vectorize. In this paper, we present how our implementation on the AI Engine (AIE) architecture addresses both of these problems. First, we have defined a flexible graph structure, which we call an ERI-Engine, that can be implemented for all 231 canonical ERI quartets from {ss|ss} to {hh| hh} by distributing the computation over 2–14 AIEs. Second, for the larger quartets, we have devised a novel vectorization scheme that leverages the advanced floating-point unit of the AIEs, while also supporting vectorization of independent ERIs for the smaller quartets. Finally, ERI-Engines are horizontally and vertically stackable to fill the entire AIE array, and in particular, the vertically stacked ERI-Engines form a column that uses one or more time-shared channels to stream the results out of the AIE array, almost completely hiding the computational phases of individual ERI-Engines. In terms of absolute performance, we are competitive with recent high-performance implementations of ERI algorithms on FPGAs (SERI) and GPUs (LibintX), as well as well-established highly optimized CPU libraries (Libint, Libcint), while being the unequivocal leader in terms of energy efficiency.

关键词： Phased arrays Quantum computing Memory management Quantum mechanics Libraries Computational efficiency Artificial intelligence Engines field programmable gate arrays Electrons

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A moving least-square approach for current slope estimation in an inverter fed IPMSM using field programmable gateway arrays

A moving least-square approach for current slope estimation ...

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24th International Conference on Electrical Machines (ICEM)

作者： Degel, J. P. Haehnlein, S. Kloeffer, C. Doppelbauer, M. Karlsruhe Inst Technol KIT Chair Elect Tech Inst ETI Karlsruhe Germany Hsch Offenburg Fac Elect Engn Med Technol & Comp Sci EMI Offenburg Germany

ISBN: (纸本)9781728199450

In this work a method for the estimation of current slopes induced by inverters operating interior permanent magnet synchronous machines is presented. After the derivation of the estimation algorithm, the requirements for a suitable sensor setup in terms of accuracy, dynamic and electromagnetic interference are discussed. The boundary conditions for the estimation algorithm are presented with respect to application within high power traction systems. The estimation algorithm is implemented on a field programmable gateway array. This moving least-square algorithm offers the advantage that it is not dependent on vectors and therefore not every measured value has to be stored. The summation of all measured values leads to a significant reduction of the required storage units and thus decreases the hardware requirements. The algorithm is designed to be calculated within the dead time of the inverter. Appropriate countermeasures for disturbances and hardware restrictions are implemented. The results are discussed afterwards.

关键词： AC machines Current control Current measurement Estimation field programmable gate arrays Measurement Monitoring Parameter estimation Predictive models

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Demonstration of a Clock Distribution Method using Switching Matrices and a Two-Phase Clock Signal on an FPGA

Demonstration of a Clock Distribution Method using Switching...

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IEEE International Conference on Consumer Electronics (ICCE)

作者： Ayumu Ogura Minoru Watanabe Nobuya Watanabe Information Technology Track Information Technology Electrical Engineering and Mathematical and Data Sciences Program Faculty of Engineering Okayama University Okayama Japan

ISBN: (数字)9798331521165

ISBN: (纸本)9798331521172

Very large-scale Integrations (VLSIs) are vulnerable to radiation, and VLSIs used in high radiation environments such as space environment and nuclear power plants have a short lifetime. Therefore, we are developing radiation-hardened optically reconfigurable gate arrays. Conventional optically reconfigurable gate array VLSIs have a weak point in clock distribution. This problem can be solved by a new clock distribution exploiting reconfigurable switching matrices. However, in this case, the clock skew increases. Therefore, to solve this problem, this paper proposes a new clock distribution method using a two-phase clock signal and switching matrices on an optically reconfigurable gate array VLSI. The proposed clock distribution method has been demonstrated on a Cyclone V FPGA by using a 4-bit counter circuit. This paper presents the demonstration results.

关键词： Integrated optics Optical switches Radiation detectors Logic gates Very large scale integration Adaptive optics field programmable gate arrays Power generation Clocks Optical arrays

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RapidPnR: Accelerating the Physical Design for FPGAs via Design-Level Parallelism

RapidPnR: Accelerating the Physical Design for FPGAs via Des...

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Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Wanzheng Weng Pingqiang Zhou School of Information Science and Technology ShanghaiTech University Shanghai China

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

The runtime of physical design has become a critical issue for FPGA development as the scale and complexity of circuit designs surge with the increasing logic capacity of FPGA devices. The time-consuming process of physical design significantly extends the cycle of design iteration, which heavily impacts the efficiency of debugging and architecture optimization. To address this issue, this work proposes a generic, fully-automated and split-and-parallel physical design flow to accelerate the deployment of large-scale circuits on FPGAs. Specifically, our flow automatically partitions the synthesized netlist into multiple smaller pieces, performs parallel physical design of each piece, and then merges them into the complete design. Evaluated on a set of real circuit benchmarks, our flow reduces the runtime by more than 50% and ensures nearly the same design frequency compared to the physical design flow provided by the commercial tool Vivado.

关键词： Runtime Debugging Computer architecture Parallel processing Routing Logic Surges field programmable gate arrays Optimization Physical design

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RealProbe: An Automated and Lightweight Performance Profiler for In-FPGA Execution of High-Level Synthesis Designs

RealProbe: An Automated and Lightweight Performance Profiler...

引用

Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Jiho Kim Cong Hao School of Electrical and Computer Engineering Georgia Institute of Technology

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

High-level synthesis (HLS) accelerates FPGA design by rapidly generating diverse implementations using optimization directives. However, even with cycle-accurate C/RTL co-simulation, the reported clock cycles often differ significantly from actual FPGA performance. This discrepancy hampers accurate bottleneck identification, leading to suboptimal design choices. Existing in-FPGA profiling tools, such as the Integrated Logic Analyzer (ILA), require tedious inspection of HLS-generated RTL and manual signal monitoring, reducing productivity. To address these challenges, we introduce RealProbe, the first fully automated, lightweight in-FPGA profiling tool for HLS designs. With a single directive-#pragma HLS RealProbe-the tool automatically generates all necessary code to profile cycle counts across the full function hierarchy, including submodules and loops. RealProbe extracts, records, and visualizes cycle counts with high precision, providing actionable insights into on-board performance. RealProbe is non-intrusive, implemented as independent logic to ensure minimal impact on kernel functionality or timing. It also supports automated design space exploration (DSE), optimizing resource allocation based on FPGA constraints and module complexity. By leveraging incremental synthesis and implementation, DSE runs independently of the original HLS kernel. Evaluated across 28 diverse test cases, including a large-scale design, RealProbe achieves 100% accuracy in capturing cycle counts with minimal logic overhead-just 16.98% LUTs,43.15% FFs, and 0% BRAM usage. The tool, with full documentation and examples, is available on GitHub 1 1 https://***/sharc-lab/RealProbe.

关键词： Visualization Accuracy Random access memory Bandwidth Timing Space exploration Logic Kernel Usability field programmable gate arrays

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ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis

ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Sy...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Hongyang Pan Keren Zhu Fan Yang Zhufei Chu Xuan Zeng State Key Lab of Integrated Circuits and Systems School of Microelectronics Fudan University Shanghai China Faculty of Electrical Engineering and Computer Science Ningbo University Ningbo China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Mapping to $k$ -input lookup tables ( $k$ -LUTs) is a critical process in field-programmable gate array (FPGA) synthesis. However, the structure of the subject graph can introduce structural bias, which refers to the dependency of mapping results on the inherent graph structure, often leading to suboptimal results. To address this, we present ELMap, an area-driven LUT mapping framework. It incorporates structural choice during the collapsing phase. This enables dynamic decomposition, maximizing local-to-global optimization transfer. To ensure seamless integration between the optimization and mapping processes, ELMap leverages exact $k$ -LUT synthesis to generate area-optimal sub-LUT networks. Experiments on the EPFL benchmark suite demonstrate that ELMap significantly outperforms state-of-the-art methods. Specifically, in 6-LUT mapping, ELMap reduces the average LUT area by 8.5% and improves the area-depth-product (ADP) by 5.8%. In 4-LUT remapping, it reduces the average LUT area by 17.6% and improves the ADP by 2.4%.

关键词： Europe Benchmark testing Table lookup Logic Optimization field programmable gate arrays

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