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检索条件"主题词=Field Programmable Gate Arrays"

共 41626 条记录，以下是531-540 订阅

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Real-Time Detection and Correction of Signal-Based Attacks in Cyber-Physical Systems

Real-Time Detection and Correction of Signal-Based Attacks i...

引用

Innovative Research in Applied Science, Engineering and Technology (IRASET),Conference on

作者： Yassine Khamlich Aziz Oukaira Fathallah Khamlich Ahmed Lakhssassi Jamal Zbitou Department of Computer Science and Engineering Université du Québec en Outaouais Gatineau Canada Department of Electrical Engineering Université de Moncton Moncton Canada Department of Physics Université Hassan II Casablanca Morocco Department of Engineering and Computer Science Université du Québec en Outaouais Gatineau Canada

ISBN: (数字)9798331532970

ISBN: (纸本)9798331532987

Cyber-Physical Systems (CPS) are vital to modern infrastructure but remain vulnerable to signal-based attacks that threaten their reliability and safety. This work proposes a practical security framework combining Verilog simulations and Python-based analysis to detect and correct False Data Injection (FDI) attacks in real time. The system integrates anomaly detection, classification, and, correction using predefined logic and Machine Learning (ML) inference. Experimental results demonstrate a 92.3% detection rate, 5.4% false positive rate, and correction latency under 250 ms. Three simulated attack scenarios confirm the framework’s robustness and ability to sustain CPS performance under adversarial conditions. Future work will explore field-programmable gate Array (FPGA) deployment for hardware validation and Digital Twin (DT) integration for realtime system mirroring and predictive defense.

关键词： Scalability Machine learning Real-time systems Hardware Digital twins Smart grids Security field programmable gate arrays Anomaly detection Testing

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Fault injection emulation for field programmable analog arrays

Fault injection emulation for field programmable analog arra...

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Southwest Symposium on Mixed-Signal Design

作者： Slaughter, T Stroud, C Univ N Carolina Dept Elect & Comp Engn Charlotte NC 28223 USA

ISBN: (纸本)0780377788

We present a practical and economical method for physical fault insertion in analog circuits using field programmable Analog arrays (FPAAs) for use in the development and evaluation of manufacturing and system-level tests for analog and mixed-signal integrated circuits and systems. The method involves the manipulation of configuration bits used to program the FPAA to emulate catastrophic faults (shorts and opens) and parametric faults (component values outside of acceptable ranges) in the FPAA during operation of the analog circuitry.(1).

关键词： Circuit faults Circuit simulation Circuit testing Emulation field programmable analog arrays field programmable gate arrays Manufacturing Prototypes System testing Virtual prototyping

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An approach to the built-in self-test of field programmable analog arrays

An approach to the built-in self-test of field programmable ...

引用

22nd IEEE VLSI Test Symsposium

作者： Balen, T Andrade, A Azaïs, F Lubaszewski, M Renovell, M Univ Fed Rio Grande Sul DELET Porto Alegre RS Brazil

ISBN: (纸本)0769521347

The use of the Oscillation Test Strategy to test Configurable Analog Blocks of field programmable Analog arrays (FPAAs) has been proposed previously, solving the complex problem of test stimuli generation. An improvement to that technique is presented in this paper, using the resources of the FPAA to build an Output Response Analyzer. This new approach offers a full Built-In Self-Test scheme with no area overhead and requiring a low cost Automatic Test Equipment. Experiments show the efficiency of the approach in detecting parametric faults of the tested components.

关键词： field programmable gate arrays

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A Fast Frequency Measurement Circuit With Low Latency Developed Using FPGA

A Fast Frequency Measurement Circuit With Low Latency Develo...

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First International Symposium on Instrumentation, Control, Artificial Intelligence, and Robotics (ICA-SYMP)

作者： Sohoda Sri Sharani Kuan-Ping Hsieh Yun-Chih Lu Jau-Horng Chen Yi-Jan Emery Chen Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan R. O. C. Department of Engineering Science and Ocean Engineering National Taiwan University Taipei Taiwan R. O. C. Graduate Institute of Electronics Engineering and Graduate Institute of Communication Engineering National Taiwan University Taipei Taiwan R. O. C.

ISBN: (数字)9798331505400

ISBN: (纸本)9798331505417

This paper presents the design and challenges of the statistical frequency measurement technique, which can be implemented using a field-programmable gate array (FPGA) board. The frequency measurement range is from 200 MHz to 715 MHz, with errors of less than 500 kHz. The latency of the first measurement result is only 360 ns, and consecutive measurement results of the same frequency signal can be obtained every 20 ns. Higher frequency accuracy can be effectuated by increasing the measurement latency.

关键词： Logic circuits Instruments Logic gates Throughput Frequency measurement Velocity measurement Low latency communication field programmable gate arrays Robots Frequency control

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Layer-Specific Hardware Pooling Designs for CNN Accelerators

Layer-Specific Hardware Pooling Designs for CNN Accelerators

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International Conference on VLSI Design

作者： Vinay Rayapati Mahati Basavaraju Madhav Rao IIIT Bangalore India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

This paper proposes and explores the impact of using Combinatorial Pooling techniques - the combination of widely used Max pooling and SOTA Deviation based pooling techniques such as Absolute Average Deviation (AAD) or Binary Weighted Absolute Deviation (BWAD) or Absolute Maximum Deviation (AMD), across different layers in CNN architectures. The design-space exploration suggests the best possible combination of pooling schemes to be adopted for realizing hardware-efficient CNN accelerators in the future. The proposed Combinatorial pooling schemes offer enhanced model accuracy in AlexNet, UNet, and VGG-16 CNN architectures, besides offering substantial hardware gains, when compared to sole usage of deviation based pooling techniques. The results obtained from FPGA synthesis on Xilinx Zedboard are presented for a single cumulative unit of convolution and pooling operation for Max, AAD, BWAD and AMD methods. ASIC Synthesis results using Cadence 45 nm technology library are showcased for exhaustive combinations when implemented for all convolution and pooling layers in VGG-16 and AlexNet CNN architectures. For AlexNet, the unique sequence “110” with BWAD (BWAD-BWAD-Max), offers footprint savings of 4.27%, 14.77%, 11.87%, and 14.64%, over the regular individual pooling methods of Max, AAD, BWAD and AMD respectively. It also exhibits 6.67% increase in accuracy over the SOTA best.

关键词： Measurement Accuracy Embedded systems Convolution Very large scale integration Hardware Libraries Convolutional neural networks field programmable gate arrays

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Ph.D. Project ARIES: Efficient Mapping and Automated Compilation for AMD Versal Devices

Ph.D. Project ARIES: Efficient Mapping and Automated Compila...

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Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Jinming Zhuang Peipei Zhou Brown University

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

As AI continues to grow, modern applications are becoming more memory and computation intensive, driving the development of specialized AI chips to meet these demands. AMD Versal ACAP devices serve as a promising heterogeneous solution for continuous compute scaling. However, heterogeneity presents challenges not only in achieving high-performance mapping solutions but also in providing a programming abstraction that ensures high productivity. If these challenges are not effectively addressed, they will hinder the widespread adoption of these heterogeneous architectures by experts from other domains beyond hardware expertise. We are among the first to explore efficient mapping solutions for this heterogeneous system. We propose a series of works (FPGA'23 [1], DAC‘23 [2], TRETS‘24 [3], FPGA‘24 [4], TCAD‘24 [5]), which thoroughly investigate the design space for modern transformer-based workloads by mapping different layers to various system components, such as CPUs, FPGAs, and AIEs, while analyzing the trade-offs between latency and throughput. Additionally, to significantly enhance programming productivity on these heterogeneous systems, we are the first to introduce ARIES (FPGA'25 [6] Best Paper Nominee), a multi-level intermediate representation (MLIR)-based compilation framework that proposes a unified intermediate representation (IR) for the end-to-end application deployment on AIE architectures.

关键词： Productivity AI accelerators Computer architecture Programming Transformers Throughput Hardware field programmable gate arrays

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Simplified Implementation of Histogram Equalization Using Approximation Offset

Simplified Implementation of Histogram Equalization Using Ap...

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Cognitive Computing in Engineering, Communications, Sciences and Biomedical Health Informatics (IC3ECSBHI), International Conference on

作者： Chetan Singh Rajput Sandeep Sharma Rajesh Mishra School of Information and Communication Technology Goutam Buddha University Greater Noida India Department of Higher and Technical Education Government of Jharkhand Ranchi India

ISBN: (数字)9798331518523

ISBN: (纸本)9798331518530

This paper presents a simplified implementation of Histogram Equalization by adding offset values to the Histogram bins. The proposed approach helps to simplify the division/multiplication operations in Histogram Equalization calculation using shift operations. This approach is tested on different resolutions of gray images. The image quality comparison of this approach with conventional Histogram equalization shows that the proposed simplified implementation is effective for lower values of approximation offset.

关键词： Image quality Histograms Image resolution Costs Codes Transfer functions Hardware Entropy Cognitive systems field programmable gate arrays

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Simulation of Analog Filter Using Digital Element Base

Simulation of Analog Filter Using Digital Element Base

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Systems of Signals Generating and Processing in the field of on Board Communications

作者： P. S. Martyanov Scientific and Technological Center of Unique instrumentation of the Russia Academy of Sciences (STC UI RAS) Moscow Russia

ISBN: (数字)9798331532635

ISBN: (纸本)9798331532642

It has been suggested to design analog devices using elementary units of the automatic control theory in order to reduce the labor consumption of the design process. The elementary units have been simulated and implemented on the basis of digital elements. It has been shown that the elementary units studied can be configured into specific analog devices. The correctness of the suggested method has been verified for the example of the simulation and design of an analog filter circuit on the basis of digital elements

关键词： Design methodology Printed circuits Process control Digital signal processing Filtering theory Digital filters field programmable gate arrays Testing

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Implementation Research of Tiny ML on RISC-V Platform Using Efinix Platform for Real Time Person Detection

Implementation Research of Tiny ML on RISC-V Platform Using ...

引用

International Colloquium on Signal Processing & Its Applications, CSPA

作者： Yeap Wei Hao Cheong Choon Min Roslee Mohd Sabri Richard Lai Tian Fat Su Hsiao Wei Hazwan Halim Solahuddin Yusuf Fadhlullah School of Engineering INTI international College Penang Bayan Lepas Pulau Penang Malaysia MIMOS Berhad Technology Park Malaysia Bukit Jalil Kuala Lumpur Malaysia

ISBN: (数字)9798331522193

ISBN: (纸本)9798331522209

The rapid advancements in artificial intelligence (AI) and computer vision have revolutionized intelligent security systems, addressing challenges related to cost, efficiency, and scalability. This paper investigates the application of Tiny Machine Learning (TinyML) on the RISC-V platform, utilizing the Efinix Ti60 F225 FPGA for real-time person detection. The study aims to harness the energy efficiency, flexibility, and scalability of the RISC-V architecture to develop a cost-effective and sustainable solution for intelligent security applications. The proposed system combines the YOLO model for person detection with TinyML techniques, enabling real-time processing while maintaining an accuracy of 80% for individuals within a 2-meter range. Hardware components, such as the Raspberry Pi Camera Module V2 and Mini DSI Panel, were employed to capture and display real-time imagery. Comprehensive evaluations demonstrated the system's performance advantages, including reduced latency, low power consumption, and minimal bandwidth usage, emphasizing the benefits of deploying AI at the edge. Although challenges such as environmental variability and memory limitations were encountered, the findings highlighted the potential of integrating TinyML with RISC-V platforms for intelligent security applications. The results contributed to the field of edge computing and open-source hardware, presenting a viable approach to energy-efficient and scalable AI solutions. Future research will focus on overcoming hardware constraints, extending the detection range, and incorporating adaptive learning capabilities to enhance system robustness and functionality further.

关键词： YOLO Reduced instruction set computing Costs Tiny machine learning Scalability Real-time systems Energy efficiency Security Artificial intelligence field programmable gate arrays

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Compute-In-Memory on FPGAs for Deep Learning: A Review

Compute-In-Memory on FPGAs for Deep Learning: A Review

引用

Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Aman Arora Arizona State University

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

field-programmable gate arrays (FPGAs) are increasingly recognized as an efficient platform for accelerating Deep Learning (DL) applications. This is due to their hardware-level configurability, which allows for tailored datapaths and low-precision inference capabilities. As data-intensive applications such as DL continue to grow, there is a renewed interest in Compute-In-Memory (CIM) architectures to address the bottle-neck caused by moving large volumes of data between memory blocks (off-chip or on-chip) and compute units. This paper delves deep into CIM architectures designed for FPGAs, focusing on making FPGAs better accelerators of DL applications. This paper provides an overview of CIM and FPGA architecture, motivating the need to design custom FPGA architectures with CIM capability. Detailed insights into CIM operation on FPGAs and the implementation of CIM on FPGAs are presented, focusing on modifications to the memory blocks on FPGAs. Existing FPGA CIM proposals are categorized and the nuances of architecting CIM blocks for FPGAs are explained. Lastly, it outlines the current challenges that must be addressed to facilitate broader adoption of CIM architectures on FPGAs.

关键词： Deep learning Reviews Focusing Computer architecture In-memory computing Common Information Model (computing) System-on-chip Proposals field programmable gate arrays

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