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检索条件"主题词=Field Programmable Gate Arrays"
41642 条 记 录,以下是531-540 订阅
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Ph.D. Project: Floorplan Quality Prediction for HLS Design Exploration on Multi-Die FPGA
Ph.D. Project: Floorplan Quality Prediction for HLS Design E...
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Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)
作者: Haoran Xue Teng Wang Chao Wang School of Computer Science and Technology University of Science and Technology of China Suzhou Institute for Advanced Research University of Science and Technology of China
High-level synthesis (HLS) and multi-die FPGAs are widely used for large-scale accelerators. To address the cross multi-die boundary delays and local congestion issues in HLS designs on multi-die FPGAs, a coarse-grain... 详细信息
来源: 评论
Fall Detection Using Sound with FPGA Signal Analysis and Machine Learning Integration
Fall Detection Using Sound with FPGA Signal Analysis and Mac...
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Machine Learning and Autonomous Systems (ICMLAS), International Conference on
作者: Mariano Viegas Andre Ahmet Turan Özdemir Erhan Kavuncuoglu Department of Electric and Electronic Engineering Erciyes University Kayseri Turkey Department of Computer Tecnology Gemerek Vocational School: Cumhuriyet University Sivas Turkey
Falls represent a considerable risk to the well-being of geriatric populations, frequently resulting in injuries or mortality. In response to this pressing concern, we introduce an innovative fall detection apparatus ... 详细信息
来源: 评论
Multi-Sensor Data Fusion for Enhanced Detection of Laser Fault Injection Attacks in Cryptographic Hardware: Practical Results
Multi-Sensor Data Fusion for Enhanced Detection of Laser Fau...
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Design, Automation and Test in Europe Conference and Exhibition
作者: Mohammad Ebrahimabadi Raphael Viera Sylvain Guilley Jean-Luc Danger Jean-Max Dutertre Naghmeh Karimi University of Maryland Baltimore County United States Mines de Saint-Étienne CEA Leti Centre CMP Gardanne France Secure-IC S.A.S. France ENS Information Security Group Paris France Telecom Paris Institut Polytechnique de Paris France
Though considered secure the cryptographic hardware can be compromised by fault injection attack, especially laser illumination due to its precision in targeting specific areas and its fine temporal control. To addres... 详细信息
来源: 评论
A new architecture of field programmable analog arrays for reconfigurable instantiation of continuous-time filters
A new architecture of field programmable analog arrays for r...
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3rd International Conference on field-programmable Technology
作者: Becker, J Manoli, Y Univ Freiburg Chair Microelect IMTEK D-79110 Freiburg Germany
A new methodology of field programmable analog arrays (FPAAs) is presented, which is particulary designed as hardware platform for the instantiation of continuous-time (CT) adaptable filters. The array topology consis... 详细信息
来源: 评论
Efficient and Distributed Computation of Electron Repulsion Integrals on AMD AI Engines
Efficient and Distributed Computation of Electron Repulsion ...
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Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)
作者: Johannes Menzel Christian Plessl Department of Computer Science Paderborn Center for Parallel Computing Paderborn University Paderborn Germany
Computing electron repulsion integrals (ERIs) is the major computational bottleneck of many quantum mechanical simulation methods, requiring trillions of ERI evaluations per time step. While the computation of indepen... 详细信息
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A moving least-square approach for current slope estimation in an inverter fed IPMSM using field programmable gateway arrays
A moving least-square approach for current slope estimation ...
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24th International Conference on Electrical Machines (ICEM)
作者: Degel, J. P. Haehnlein, S. Kloeffer, C. Doppelbauer, M. Karlsruhe Inst Technol KIT Chair Elect Tech Inst ETI Karlsruhe Germany Hsch Offenburg Fac Elect Engn Med Technol & Comp Sci EMI Offenburg Germany
In this work a method for the estimation of current slopes induced by inverters operating interior permanent magnet synchronous machines is presented. After the derivation of the estimation algorithm, the requirements... 详细信息
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Demonstration of a Clock Distribution Method using Switching Matrices and a Two-Phase Clock Signal on an FPGA
Demonstration of a Clock Distribution Method using Switching...
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IEEE International Conference on Consumer Electronics (ICCE)
作者: Ayumu Ogura Minoru Watanabe Nobuya Watanabe Information Technology Track Information Technology Electrical Engineering and Mathematical and Data Sciences Program Faculty of Engineering Okayama University Okayama Japan
Very large-scale Integrations (VLSIs) are vulnerable to radiation, and VLSIs used in high radiation environments such as space environment and nuclear power plants have a short lifetime. Therefore, we are developing r... 详细信息
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RapidPnR: Accelerating the Physical Design for FPGAs via Design-Level Parallelism
RapidPnR: Accelerating the Physical Design for FPGAs via Des...
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Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)
作者: Wanzheng Weng Pingqiang Zhou School of Information Science and Technology ShanghaiTech University Shanghai China
The runtime of physical design has become a critical issue for FPGA development as the scale and complexity of circuit designs surge with the increasing logic capacity of FPGA devices. The time-consuming process of ph... 详细信息
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RealProbe: An Automated and Lightweight Performance Profiler for In-FPGA Execution of High-Level Synthesis Designs
RealProbe: An Automated and Lightweight Performance Profiler...
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Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)
作者: Jiho Kim Cong Hao School of Electrical and Computer Engineering Georgia Institute of Technology
High-level synthesis (HLS) accelerates FPGA design by rapidly generating diverse implementations using optimization directives. However, even with cycle-accurate C/RTL co-simulation, the reported clock cycles often di... 详细信息
来源: 评论
ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis
ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Sy...
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Design, Automation and Test in Europe Conference and Exhibition
作者: Hongyang Pan Keren Zhu Fan Yang Zhufei Chu Xuan Zeng State Key Lab of Integrated Circuits and Systems School of Microelectronics Fudan University Shanghai China Faculty of Electrical Engineering and Computer Science Ningbo University Ningbo China
Mapping to $k$ -input lookup tables ( $k$ -LUTs) is a critical process in field-programmable gate array (FPGA) synthesis. However, the structure of the subject graph can introduce structural bias, which refers to the ... 详细信息
来源: 评论