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Dual-comb spectroscopy in the deep ultraviolet

OPTICA 2024年第4期11卷 460-463页

作者： McCauley, John J. Phillips, Mark C. Weeks, Reagan R. D. Zhang, Yu Harilal, Sivanandan S. Jones, R. Jason Univ Arizona James C Wyant Coll Opt Sci Tucson AZ 85721 USA Univ Arizona Dept Phys Tucson AZ 85721 USA Pacific Northwest Natl Lab Richland WA 99354 USA

This Letter reports dual-frequency-comb spectroscopy in the deep ultraviolet used to characterize transient laser -produced plasmas. Dual-comb spectroscopy at these wavelengths enables access to a large number of strong electronic transitions in neutral and ionized atoms and molecules. This broadband dual-frequency-comb system at 265 nm measures multiple transitions in neutral and singly ionized iron atoms in a laser-produced plasma. Analysis of absorption spectra yields time -resolved ion and neutral column densities, excitation temperatures, and electron densities, which are measured down to 10(14) cm(- 3 )levels. The results provide insights into low -temperature plasma properties.

关键词： Absorption spectroscopy Dual comb spectroscopy field programmable gate arrays Fourier transform infrared spectroscopy Mode-locked fiber lasers Ultraviolet spectroscopy

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Enhancing Wireless PHY With Adaptive OFDM and Multiarmed Bandit Learning on Zynq System-on-Chip

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第6期33卷 1651-1664页

作者： Singh, Neelam Darak, Sumit J. IIIT Delhi Algorithms Architecture Lab New Delhi 110020 India IIIT Delhi Dept Elect & Commun New Delhi 110020 India

In this work, we present an intelligent and reconfigurable wireless physical layer (PHY) that dynamically adjusts the transmission parameters for a given radio frequency (RF) environment. The proposed PHY is based on orthogonal frequency division multiplexing (OFDM) and can dynamically augment OFDM with a finite impulse response (FIR) low-pass filter to improve the out-of-band emissions (OOBE). To make these adaptations intelligently, we employ multiarmed bandit (MAB)-based online learning algorithms, specifically upper confidence bound with control variate (UCB-CV). UCB-CV enhances traditional UCB by incorporating additional information such as interference level and transmit power, allowing it to manage interference more effectively. These algorithms are integrated into the PHY of an FPGA-based OFDM transceiver on the Zynq system-on-chip (SoC), facilitating real-time decision-making based on side-channel interference and other parameters. Our comparative analysis highlights the enhanced performance of the UCB-CV algorithm over the traditional UCB in terms of reducing the bit-error rate (BER) and managing interference more effectively. Unlike the traditional UCB, UCB-CV leverages side information through a control variate approach, incorporating the coefficient of variation (CV) into reward estimation to better handle interference. Additionally, we underline the advantages of filtered-OFDM (FOFDM) compared to standard OFDM. Notably, FOFDM significantly reduces OOBE by 20-75 dBW/Hz and improves BER. In environments with high interference, UCB-CV achieves a throughput improvement of 29.54% compared to UCB.

关键词： OFDM Interference Throughput Wireless communication Transceivers Real-time systems Heuristic algorithms Modulation field programmable gate arrays Wireless sensor networks Adaptive physical layer dynamic partial reconfiguration (DPR) filtered-OFDM (FOFDM) FPGA intelligent reconfigurable PHY architecture machine learning multiarmed bandit (MAB) orthogonal frequency division multiplexing (OFDM) upper confidence bound (UCB)-control variate Zynq system-on-chip (SoC)

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Turbo-FHE: Accelerating Fully Homomorphic Encryption With FPGA and HBM Integration

IEEE DESIGN & TEST

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IEEE DESIGN & TEST 2025年第3期42卷 86-93页

作者： Nassar, Hassan Bauer, Lars Henkel, Jorg Karlsruhe Inst Technol Chair Embedded Syst D-76131 Karlsruhe Germany

Editor's notes: Homomorphic encryption offers a solution to escalating privacy and security concerns when the data are processed in the cloud. In this article, the authors propose an accelerator for homomorphic en... 详细信息

关键词： field programmable gate arrays Polynomials Noise Homomorphic encryption arrays Memory management Accuracy Three-dimensional displays Bandwidth Software

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Single-Path High-Resolution Digital PWM Architectures With Cascadability of Delay Lines

IEEE OPEN JOURNAL OF POWER ELECTRONICS

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IEEE OPEN JOURNAL OF POWER ELECTRONICS 2025年 6卷 130-143页

作者： Hajiheidari, Marziyeh Fushekati, Joel Emad, Mohammad Vermulst, Bas J. D. van Duivenbode, Jeroen Huisman, Henk Eindhoven Univ Technol Dept Elect Engn Power Elect Lab PELe NL-5612 AZ Eindhoven Netherlands

This paper introduces two new single-path and cascaded High-Resolution Digital Pulse Width Modulation (HRDPWM) architectures. The proposed single-path architecture uses fewer FPGA resources to achieve the same resolution as conventional dual-path architectures. Moreover, the generated HRDPWM signal is independent of the Place-And-Route (PAR) algorithm applied by the synthesis tool, as well as temperature and voltage variations. The proposed cascaded architecture can be used to increase the DPWM resolution without raising the system clock frequency or, alternatively, to reduce the FPGA system clock frequency (relaxing timing challenges) without lowering the resolution. Both architectures have been implemented and verified using a mid-range Artix-7 FPGA with both triangular and sawtooth carriers. A time resolution of 39 ps has been achieved for the cascaded HRDPWM architecture with a sawtooth carrier and a system clock of 400 MHz. Additionally, a GaN-based synchronous buck converter is designed and implemented to evaluate the performance of the proposed HRDPWM architectures in a real application. It is demonstrated that bothhldead time and duty cycle can be modified with high accuracy and resolution and updated twice per switching cycle.

关键词： Clocks Signal resolution field programmable gate arrays Delay lines Delays Pulse width modulation Propagation delay Power electronics Switching frequency Switches Digital pulse width modulation (DPWM) delay line high resolution (HR) high switching frequency

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Transmitter for Visible Light Communications Based on FPGA's Output Buffers

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IEEE COMMUNICATIONS LETTERS 2024年第9期28卷 2116-2120页

作者： Ricci, Stefano Caputo, Stefano Univ Florence Dept Engn Informat DINFO I-50139 Florence Italy

Among the several new applications that Visible Light Communication (VLC) have made possible in recent years, board-to-board (B2B) communication represents an important field of employment for this technology. Most of the systems that would benefit from VLC-based B2B communication are digital boards that include field programmable gate arrays (FPGAs) or advanced processors. Modern FPGA output buffers have limited power, but switch at hundreds of MHz: a much higher rate compared to that of the typical single MOSFET employed in a ON-Off Key (OOK) transmitter. This letter explores the possibility of exploiting the FGPA buffers for realizing a OOK transmitter suitable for B2B communication. A transmitter circuit, driving a 70 mA LED, is proposed and characterized for 26 different electrical standards and configurations of the FPGA buffer. A 210Mb/s link was demonstrated at a distance of 6cm (120Mb/s at 24cm) with a Bit Error Rate (BER) < 1.5 center dot 10(-6) (95% confidence).

关键词： field programmable gate arrays Standards Light emitting diodes Transmitters Bandwidth Gain MOSFET Visible light communication (VLC) IEEE 802.15.7 board-to-board (B2B) communication field programmable gate array (FPGA) VLC transmitter intra-box communication

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Reliable Methodology to FPGA Design Verification and Noise Analysis for Digital Lock-In Amplifiers

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第3期16卷 307-310页

作者： Galaviz-Aguilar, Jose Alejandro Vargas-Rosales, Cesar Falcone, Francisco Tecnol Monterrey Sch Engn & Sci Monterrey 64649 Mexico Publ Univ Navarre UPNA Inst Smart Cities Dept Elect Elect & Commun Engn Pamplona 31006 Spain Tecnol Monterrey Sch Engn & Sci Monterrey 64700 Mexico

The lock-in amplifier (LIA) instruments are designed to provide signal conditioning for precision measurement systems to extract signals from extremely noisy environments. The digital LIAs design often requires a verification process to ensure hardware performance. Thus, hardware description language (HDL) with functional verification strategies offers a powerful tool to provide an FPGA integrated solution. In this letter, we propose a methodology of design and verification of all-digital LIA and an additive white Gaussian noise (AWGN) module able to measure extremely lower levels of signal-to-noise ratio (SNR) of approximate to 10(-15) or down to -37 dB while a wide reserve of spurious-free dynamic range (SFDR) up to 90 dB on FPGA is ensured. To this end, the designed and implemented FPGA framework for quick, accurate, and comprehensive characterization of a given digital LIA is used to leverage the capabilities of the design under controllable AWGN noise patterns stimulus.

关键词： Clocks field programmable gate arrays Noise Frequency measurement IIR filters Task analysis Phase locked loops Additive white Gaussian noise (AWGN) digital lock-in amplifiers (DLIAs) field-programmable gate array (FPGA) phase sensitive detector (PSD) spurious-free dynamic range (SFDR)

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FPGA-based adaptive rate-reduced visible light Ethernet communication system

OPTICS CONTINUUM

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OPTICS CONTINUUM 2025年第3期4卷 522-534页

作者： Jin, Jianli Shang, Qianlong Zhang, Hailong Lu, Huimin Univ Sci & Technol Beijing Sch Comp & Commun Engn Beijing 100083 Peoples R China Univ Sci & Technol Beijing Shunde Innovat Sch Foshan 528399 Peoples R China

Visible light communication (VLC) integrates with Ethernet technology as a nextgeneration wireless access solution for the "last mile," offering vast potential for short-range indoor communications. This paper designs a field programmable gate array (FPGA) based visible light Ethernet communication system that converts Ethernet signals into visible light signals. The system dynamically reduces the signal rate to maintain network efficiency through functional modules, including network interface design, flow control, rate adaptation with a peak rate of 100 Mbps, and VLC transmission/reception control logic. Simulation and experimental results show that the system can support Ethernet connections at rates below 100 Mbps and effectively adapts to deteriorating optical channel conditions, ensuring stable communication in real-world environments.

关键词： field programmable gate arrays Light sources Optical signals Signal transmission Systems design Visible light communications

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Beam Test of a Baseline Vertex Detector Prototype for CEPC

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2024年第6期71卷 1319-1323页

作者： Li, Shuqi Wu, Tianya Huang, Xinhui Zhou, Jia Yan, Ziyue Wang, Wei Zeng, Hao Jia, Xuewei Hu, Yiming Zhang, Xiaoxu Liang, Zhijun Wei, Wei Zhang, Ying Wei, Xiaomin Zhang, Lei Qi, Ming Hu, Jun Fu, Jinyu Zhang, Hongyu Li, Gang Wu, Linghui Dong, Mingyi Li, Xiaoting Casanova, Raimon Zhang, Liang Dong, Jianing Wang, Jia Zheng, Ran Lu, Weiguo Grinstein, Sebastian da Costa, Joao Guimaraes Chinese Acad Sci Inst High Energy Phys Beijing 100049 Peoples R China Univ Chinese Acad Sci Sch Phys Sci Beijing 100049 Peoples R China Nanchang Univ Sch Informat Engn Nanchang 330031 Peoples R China Univ Chinese Acad Sci Sch Nucl Sci & Technol Beijing 100049 Peoples R China Nanjing Univ Dept Phys Nanjing 210093 Peoples R China Northwestern Polytech Univ Sch Comp Sci Xian 710072 Peoples R China Shandong Univ Inst Frontier & Interdisciplinary Sci Qingdao 266237 Peoples R China Shandong Univ Key Lab Particle Phys & Particle Irradiat Qingdao 266237 Peoples R China Northwestern Polytech Univ Sch Elect & Informat Xian 710072 Peoples R China Inst Fis Altes Energies IFAE Barcelona 08193 Spain Adv Studies ICREA Catalan Inst Res Barcelona 08010 Spain

The circular electron positron collider (CEPC) has been proposed to enable more thorough and precise measurements of the properties of Higgs, W, and Z bosons, as well as to search for new physics. In response to the stringent performance requirements of the vertex detector for the CEPC, a baseline vertex detector prototype was tested and characterized for the first time using a 6-GeV electron beam at DESY II Test Beam Line 21 (TB 21). The baseline vertex detector prototype is designed with a cylindrical barrel structure that contains six double-sided detector modules (ladders). Each side of the ladder includes TaichuPix-3 sensors based on monolithic active pixel sensor (MAPS) technology, a flexible printed circuit (FPC), and a carbon fiber support structure. In addition, the readout electronics and the data acquisition (DAQ) system were also examined during this beam test. The performance of the prototype was evaluated using an electron beam that passed through six ladders in a perpendicular direction. The offline data analysis indicates a spatial resolution of about 5 mu m, with detection efficiency exceeding 99% and an impact parameter resolution of about 5.1 mu m. These promising results from this baseline vertex detector prototype mark a significant step toward realizing the optimal vertex detector for the CEPC.

关键词： Detectors Sensors Prototypes Software field programmable gate arrays Electron beams Data acquisition Circular electron positron collider (CEPC) monolithic active pixel sensor (MAPS) vertex detector

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Unveiling the True Power of the Latched Ring Oscillator for a Unified PUF and TRNG Architecture

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2024年第12期32卷 2403-2407页

作者： Della Sala, Riccardo Bellizia, Davide Scotti, Giuseppe Univ Roma La Sapienza DIET Dept I-00184 Rome Italy Telsy SpA I-00161 Rome Italy

This work presents a novel proposal for utilizing the latched ring oscillator (LRO) as a reconfigurable entropy source, outperforming the existing literature on both physical unclonable functions (PUFs) and true random number generators (TRNGs). The PUF working principle and mathematical model are proposed in this manuscript for the first time as well as its performance measured on FPGA. The proposed LRO-based PUF is 2 $\times$ more compact than state-of-the-art PUFs on FPGA. The LRO TRNG architecture has been revisited, and an xor-tree-based postprocessing technique has been introduced to increase the throughput from 0.76 up to 800 Mbit/s, paving the way for a novel class of high-throughput reconfigurable entropy sources. The results of NIST tests carried out also under supply voltage and temperature variations have demonstrated robust key extraction and secure random number generation for different applications. This comprehensive proposal aims to advance the state of the art in compact and high-throughput entropy sources, catering to the increasing demands of modern cryptographic hardware.

关键词： Computer architecture Entropy Microprocessors Physical unclonable function Latches field programmable gate arrays Color FPGA metastability physical unclonable function (PUF) ring oscillator (RO) true random number generator (TRNG)

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Lightweight Hybrid Entropy Source True Random Number Generator Based on Jitter and Metastability

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第7期71卷 3513-3517页

作者： Yang, Shihao Liang, Huaguo Hu, Rong Yao, Liang Huang, Zhengfeng Yi, Maoxiang Lu, Yingchun Hefei Univ Technol Sch Microelect Hefei 230601 Peoples R China Anhui Univ Coll Integrated Circuits Hefei 230000 Peoples R China

True random number generators (TRNGs) perform an irreplaceable role in securing information systems. In this brief, a lightweight hybrid entropy source TRNG implementation scheme based on jitter and metastability is proposed, which uses the underlying field programmable gate array (FPGA) primitive language to construct a dual cross-coupled XOR gate (DCCX) unit to generate a random output sequence and is deployed by automatic layout and routing with the Xilinx compiler. The experimental results show that the generated random sequence passes the NIST SP800-22 test, the TESTU01 test and the AIS-31 test. The structure has been extensively tested under voltage and temperature variations and shows excellent robustness. It is worth mentioning that the proposed TRNG consumes only 12 LUTs and 10 DFFs, and achieves 150Mbps and 200Mbps throughput on Xilinx Artix-7 and Kintex-7 FPGAs, respectively, which shows a highly efficient resource utilization compared to the previously published TRNGs.

关键词： Jitter Entropy Delays field programmable gate arrays Inverters Wires Logic gates TRNGs FPGA jitter metastability hybrid entropy source

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