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An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA

IEEE EMBEDDED SYSTEMS LETTERS 2024年第2期16卷 158-161页

作者： Yin, Xiaodi Wu, Zhipeng Li, Dejian Shen, Chongfei Liu, Yu Tianjin Univ Sch Microelect Tianjin 300072 Peoples R China Beijing Smart Chip Microelect Technol Co Ltd Beijing 100089 Peoples R China

field-programmable gate array (FPGA) has become an excellent hardware accelerator solution for convolutional neural networks (CNNs). Meanwhile, optimizing methods, such as model compression, have been proposed. As most CNN accelerators focus on dense neural networks, to solve the problem of difficult hardware deployment due to irregular networks, we propose a method for sparse neural networks in our work. The storage and coding format of sparse data obtained by the block pruning method is designed to make it friendly to implement on FPGA. Besides, we also propose an efficient and simple data flow by the planarization of the whole convolution calculation process. The experimental result demonstrates that our implementation can achieve clock frequency of 190 MHz, power consumption of 13.32 W and inferencing speed of 16.37 ms. Compared with some typical Mobilenet implementation schemes, our method has been proven to achieve a better balance between frequency, accuracy, power consumption, and speed.

关键词： Convolution field programmable gate arrays Sparse matrices Kernel Encoding Convolutional neural networks Neural networks Block pruning convolutional neural network (CNN) accelerator CNNs field-programmable gate array (FPGA) sparse CNN

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Enabling Model-Based Design for Real-Time Spike Detection

IEEE OPEN JOURNAL OF ENGINEERING IN MEDICINE AND BIOLOGY

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IEEE OPEN JOURNAL OF ENGINEERING IN MEDICINE AND BIOLOGY 2025年 6卷 312-319页

作者： Di Florio, Mattia Bornat, Yannick Care, Marta Cota, Vinicius Rosa Buccelli, Stefano Chiappalone, Michela Univ Genoa Dept Informat Bioengn Robot Syst Engn DIBRIS I-16145 Genoa Italy Univ Bordeaux Lab Integrat Mat Syst IMS Bordeaux INP CNRS UMR 5218 F-33405 Talence France IRCCS Osped Policlin San Martino I-16132 Genoa Italy Ist Italiano Tecnol Rehab Technol Lab I-16163 Genoa Italy

Goal: This study addresses the inherent difficulties in the creation of neuroengineering devices for real-time neural signal processing, a task typically characterized by intricate and technically demanding processes. Beneath the substantial hardware advancements in neurotechnology, there is often rather complex low-level code that poses challenges in terms of development, documentation, and long-term maintenance. Methods: We adopted an alternative strategy centered on Model-Based Design (MBD) to simplify the creation of neuroengineering systems and reduce the entry barriers. MBD offers distinct advantages by streamlining the design workflow, from modelling to implementation, thus facilitating the development of intricate systems. A spike detection algorithm has been implemented on a commercially available system based on a field-programmable gate Array (FPGA) that combines neural probe electronics with configurable integrated circuit. The entire process of data handling and data processing was performed within the Simulink environment, with subsequent generation of hardware description language (HDL) code tailored to the FPGA hardware. Results: The validation was conducted through in vivo experiments involving six animals and demonstrated the capability of our MBD-based real time processing (latency <= 100.37 s) to achieve the same performances of offline spike detection. Conclusions: This methodology can have a significant impact in the development of neuroengineering systems by speeding up the prototyping of various system architectures. We have made all project code files open source, thereby providing free access to fellow scientists interested in the development of neuroengineering systems.

关键词： Hardware design languages Software packages Codes field programmable gate arrays Computer architecture Hardware Signal processing algorithms Neural engineering Signal processing Computational modeling in vivo experiments HDL coder field-programmable gate Array (FPGA) neuroengineering

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Evaluating NTT/INTT Implementation Styles for Post-Quantum Cryptography

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第4期16卷 485-488页

作者： Imran, Malik Khan, Safiullah Khalid, Ayesha Rafferty, Ciara Shah, Yasir Ali Pagliarini, Samuel Rashid, Muhammad O'Neill, Maire Tallinn Univ Technol Dept Comp Syst EE-19086 Tallinn Estonia Queens Univ Ctr Secure Informat Technol Belfast BT7 1NN North Ireland Manchester Metropolitan Univ Dept Comp & Math Manchester M156BH England Ulster Univ Sch Comp Engn & Intelligent Syst Londonderry BT48 7JL North Ireland Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA Umm Al Qurrah Univ Coll Comp Dept Comp & Network Engn Mecca 24382 Saudi Arabia

Unifying the forward and inverse operations of the number theoretic transform (NTT) into a single hardware module is a common practice when designing polynomial coefficient multiplier accelerators as used in the post-quantum cryptographic algorithms. This letter experimentally evaluates that this design unification is not always advantageous. In this context, we present three NTT hardware architectures: 1) a forward NTT (FNTT) architecture;2) an inverse NTT (INTT) architecture;and 3) a unified NTT (UNTT) architecture for computing the FNTT and INTT computations on a single design. We benchmark our throughput/area and energy/area evaluations on Xilinx Virtex-7 field-programmable gate array (FPGA) and 28-nm application-specific integrated circuit (ASIC) platforms. The standalone FNTT and INTT designs, on average on FPGA, exhibit 4.66x and 3.75x higher throughput/area and energy/area values, respectively, than the UNTT design. Similarly, the individual FNTT and INTT designs, on average on ASIC, achieve 1.25x and 1.09x higher throughput/area and energy/area values, respectively, compared to the UNTT design.

关键词： field programmable gate arrays Computer architecture Hardware Polynomials Routing Registers Clocks Application-specific integrated circuit (ASIC) field-programmable gate array (FPGA) number theoretic transform (NTT) polynomial multiplication post-quantum cryptography

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DSCAM: Latency-Guaranteed and High-Capacity Content-Addressable Memory on FPGAs

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第2期16卷 182-185页

作者： Vakili, Shervin Zarei, Amirhossein INRS Univ Energie Mat Telecommun Res Ctr Montreal PQ H5A 1K6 Canada

This letter introduces an original and highly efficient method to implement high-capacity content-addressable memories on field programmable gate arrays (FPGAs). The method includes a new hardware architecture and an optimization technique to determine crucial design parameters. The memory contents are partially synthesized and implemented on FPGA logic fabrics. The proposed architecture offers high throughput and fixed-latency searches. Experimental results show that the proposed method enables the implementation of an IPv4 forwarding table with over 520 K prefixes on a cost-effective AMD-Xilinx UltraScale + FPGA, providing a lookup latency of less than 28 ns and a minimum throughput of 215 million lookups per second. The source code of this work is available on GitHub.

关键词： Hardware field programmable gate arrays Multiplexing Throughput Random access memory Optimization Table lookup Content-addressable memory (CAM) field programmable gate array (FPGA) IP address lookup

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Design and Evaluation of a 2Mbps SEC Transceiver for Automotive Networks

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第6期71卷 3021-3025页

作者： D'Aniello, Federico Ott, Andreas Baschirotto, Andrea Univ Milano Bicocca Dept Phys G Occhialini I-20126 Milan Italy Melexis GmbH Dev Dept D-99099 Erfurt Germany

In this brief, a Supply Embedded Communication (SEC) transceiver for automotive networks is proposed. In an SEC approach, power supply and communication take place on the same differential bus and thus the number of required cables is drastically reduced, leading to space, raw material consumption, and cost advantages. The proposed transceiver is realized in 180nm SOI CMOS technology and is capable of implementing 2Mbps high-speed networks. In addition to proving nominal transient operation, some critical aspects for an automotive application are analyzed. Electromagnetic compatibility (EMC) is evaluated by conducting emission tests, and finally, the robustness to external disturbances is tested by direct power injection (DPI) tests.

关键词： Transceivers Hysteresis Capacitors Switching circuits field programmable gate arrays Automotive engineering Transmitters Supply embedded communication (sec) automotive networks transceiver communication bus electromagnetic compatibility (EMC) direct power injection (DPI) test

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CollectiveHLS: Ultrafast Knowledge-Based HLS Design Optimization

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第2期16卷 235-238页

作者： Ferikoglou, Aggelos Kakolyris, Andreas Kypriotis, Vasilis Masouros, Dimosthenis Soudris, Dimitrios Xydis, Sotirios Natl Tech Univ Athens Sch Elect & Comp Engn Zografos 15780 Greece

High-level synthesis (HLS) has democratized field programmable gate arrays (FPGAs) by enabling high-level device programmability and rapid microarchitecture customization through the use of directives. Nevertheless, the manual selection of the appropriate directives, i.e., the annotations included in the high-level source code to instruct the synthesis process, is a difficult task for programmers without a hardware background. In this letter, we present CollectiveHLS, an ultrafast knowledge-based HLS design optimization method that automatically extracts the most promising directive configurations and applies them to the original source code. The proposed optimization scheme is a fully data-driven approach for generalized HLS tuning, as it is not based on quality of result models or meta-heuristics. We design, implement, and evaluate our method with more than 100 applications of Machsuite, Rodinia, and GitHub on a ZCU104 FPGA. We achieve an average geometric mean speedup of x14.1 and x10.5 compared to the unoptimized, i.e., without HLS directives and optimized designs, a high design feasibility score, and an average inference latency of 38 ms.

关键词： Source coding Optimization Knowledge based systems field programmable gate arrays Measurement Sociology Pareto optimization Collective data-driven design space exploration (DSE) field programmable gate array (FPGA) high-level synthesis (HLS)

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Ultrafast Ultrasound Imaging System With Beamforming on Single FPGA

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷

作者： Zhang, Xi Qi, Sheng Li, Yifan Xu, Lijun Ma, Jianguo Beihang Univ Sch Instrumentat & Optoelect Engn Beijing 100191 Peoples R China Shandong Jianzhu Univ Sch Sci Jinan 250100 Peoples R China

Ultrafast ultrasound imaging technologies, such as ultrasound localization microscopy (ULM) and functional ultrasound (FUS), are gaining significant attention in the ultrasound field, driving the demand for higher frame rates in open ultrasound systems. However, current open ultrasound systems face the challenge of balancing high imaging frame rates with the complexity of hardware architecture. This work reports the detailed implementation and hardware architecture of a 128-channel ultrafast ultrasound platform based on a single field-programmable gate array (FPGA). This platform connects the ultrasound card to a personal computer (PC) via peripheral component interconnect express (PCIe) 3.0, providing excellent compatibility. The platform uses custom instructions to implement flexible parameter configuration in the FPGA. It can control the transmission and reception of signals, the output of raw or beamformed RF data, and the sampling depth. Additionally, a 64 sub-aperture delay-and-sum (DAS) beamformer within the FPGA is implemented in the platform. This beamformer gives output as a 128x2048 image at 10000 frames/s (fps) using plane wave. The core components of the platform measure only 12x21 cm, achieving a compact design while delivering high-frame-rate (HFR) imaging.

关键词： Ultrasonic imaging field programmable gate arrays Delays Array signal processing Imaging Hardware Computer architecture Software Radio frequency Software algorithms Beamforming field-programmable gate array (FPGA) ultrasound system ultrafast ultrasound

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Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic Injection

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第2期16卷 162-165页

作者： Valente, Giacomo Muttillo, Vittoriano Federici, Fabio Pomante, Luigi Di Mascio, Tania Univ Aquila Dept Informat Engn Comp Sci & Math I-67100 Laquila Italy Univ Teramo Dept Polit Sci I-64100 Teramo Italy Collins Aerosp Appl Res & Technol I-00185 Rome Italy

Modern real-time systems started leveraging runtime reconfigurable architectures to reduce size, weight, and power while ensuring predictability. However, the time to reconfigure a platform (referred to as reconfiguration delay) is non-negligible and subject to fluctuations caused by conflicts in accessing shared components during the reconfiguration process. Different from existing solutions that impact either system resources or system performance, in this letter, we propose an approach, together with its supporting tools, allowing to characterize the reconfiguration delay and to be able to capture and produce evidence of the actual impact of the resource contention. In addition, we report the experiments of the proposed approach in a representative configuration on a Xilinx Zynq Ultrascale+ MPSoC;results show that conflicts can impact the reconfiguration delay at most by 230%.

关键词： Delays field programmable gate arrays Real-time systems Random access memory Interference channels Quality of service Memory management Dynamic reconfiguration field-programmable gate array (FPGA) system-on-chip (SoC)

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Toward Precision-Aware Safe Neural-Controlled Cyber-Physical Systems

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第4期16卷 397-400页

作者： Thevendhriya, Harikishan Ghosh, Sumana Lohar, Debasmita Indian Stat Inst Comp Sci Div Kolkata 700108 India Karlsruhe Inst Technol KASTEL D-76131 Karlsruhe Germany

The safety of neural network (NN) controllers is crucial, specifically in the context of safety-critical Cyber-Physical System (CPS) applications. Current safety verification focuses on the reachability analysis, considering the bounded errors from the noisy environments or inaccurate implementations. However, it assumes real-valued arithmetic and does not account for the fixed-point quantization often used in the embedded systems. Some recent efforts have focused on generating the sound quantized NN implementations in fixed-point, ensuring specific target error bounds, but they assume the safety of NNs is already proven. To bridge this gap, we introduce Nexus, a novel two-phase framework combining reachability analysis with sound NN quantization. Nexus provides an end-to-end solution that ensures CPS safety within bounded errors while generating mixed-precision fixed-point implementations for the NN controllers. Additionally, we optimize these implementations for the automated parallelization on the FPGAs using a commercial HLS compiler, reducing the machine cycles significantly.

关键词： Quantization (signal) Embedded systems Artificial neural networks Cyber-physical systems Hardware Safety Noise measurement Reachability analysis field programmable gate arrays Optimization Cyber-physical system (CPS) quantization reachability analysis

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FPGA Implementation of the Proposed DCNN Model for Detection of Tuberculosis and Pneumonia Using CXR Images

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第4期16卷 445-448页

作者： Guddati, Prabhav Dash, Shaswati Tripathy, Rajesh Kumar BITS Pilani Dept EEE Hyderabad Campus Hyderabad 500078 India

The automated detection of tuberculosis (TB) and pneumonia (PN) from chest X-ray (CXR) images using artificial intelligence (AI) is challenging in clinical studies for rapid diagnosis and initiation of treatment. This letter proposes the field-programmable gate array (FPGA)-based hardware implementation of a novel lightweight deep convolutional neural network (DCNN) model to detect PN and TB ailments using CXR images. Initially, the proposed DCNN (consisting of ten layers) is trained using the Google Cloud central processing unit (CPU) to obtain the model weight and bias parameters. Then, the register transfer logic (RTL) for the trained DCNN model is generated by the VIVADO high-level synthesis (HLS) framework using HLS for machine learning (HLS4ML) with fixed-point representation (8 bit for integer and 12 bit for the fractional part). The hardware implementation of the suggested DCNN model is performed using the PYNQ-Z2 FPGA framework to detect TB and PN diseases automatically. The experimental results demonstrate that the proposed DCNN model has obtained accuracy values of 96.39% and 95.63% on the Google-Cloud CPU and PYNQ-Z2 FPGA frameworks using 422 CXR images in the inference phases. The inference time of the proposed DCNN model on the PYNQ-Z2 FPGA framework is reduced by 85.19% compared to the CPU-based implementation. The suggested DCNN model has only 1831 parameters, less than the transfer learning (TFL) and existing CNN-based models to detect TB and PN using CXR images.

关键词： Diseases field programmable gate arrays Computational modeling Hardware Feature extraction Training Image edge detection Accuracy chest X-ray (CXR) deep convolutional neural network (DCNN) field-programmable gate array (FPGA) high-level synthesis (HLS) pneumonia (PN) PYNQ-Z2 tuberculosis (TB)

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