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检索条件"主题词=Field Programmable Gate Arrays"
41641 条 记 录,以下是541-550 订阅
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Tracking Error Suppression of Maglev Planar Actuator With FPGA-Based MPC
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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷
作者: Zhou, Shun Shi, Yuan Zou, Menglong Xu, Fengqiu Xu, Xianze Wuhan Univ Elect Informat Sch Wuhan 430070 Peoples R China
The precision positioning equipment is essential in many manufacture areas. This article develops a novel noncontact six-degree-of-freedom maglev planar actuator (MLPA) for applications in precision manufacturing area... 详细信息
来源: 评论
A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年 第7期71卷 3318-3322页
作者: Lee, Jaewon Jang, Seoyoung Choi, Yujin Kim, Donggeon Yonar, Serdar Braendli, Matthias Ruffino, Andrea Morf, Thomas Kossel, Marcel Francese, Pier-Andrea Kim, Gain Daegu Gyeongbuk Inst Sci & Technol Dept Elect Engn & Comp Sci Daegu 42988 South Korea IBM Res Hybrid Cloud Res Europe Zurich Lab CH-8803 Ruschlikon Switzerland
This brief presents an RFSoC-based functional verification platform for a 2-lane pulse amplitude modulation (PAM) transceiver (TRX) datapath supporting 4-level PAM (PAM-4) and 8-level PAM (PAM-8). Digital-to-analog co... 详细信息
来源: 评论
Low-Power Subgraph Isomorphism at the Edge Using FPGAs
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IEEE ACCESS 2025年 13卷 67127-67135页
作者: Bosio, Roberto Brignone, Giovanni Urso, Teodoro Lazarescu, Mihai T. Lavagno, Luciano Pasini, Paolo Politecn Torino Dept Elect & Telecommun I-10129 Turin Italy
Subgraph matching is a significant problem in several fields, including like social network analysis, chemical compound search, and fraud detection. While current solutions using CPU, graphics processing units (GPUs),... 详细信息
来源: 评论
Primate: A Framework to Automatically Generate Soft Processors for Network Applications
IEEE COMPUTER ARCHITECTURE LETTERS
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IEEE COMPUTER ARCHITECTURE LETTERS 2024年 第1期23卷 57-60页
作者: Ma, Rui Hsu, Jia-Ching Mansoorshahi, Ali Garvey, Joseph Kinsner, Michael Singh, Deshanand Chiou, Derek Univ Texas Austin Austin TX 78712 USA Mangoboost Bellevue WA 98005 USA Intel Corp Toronto ON M5S 2X9 Canada Microsoft Redmond WA 98052 USA
Overlay processors on FPGAs enable i) software programmability through sequential code calling library functions, ii) high performance by converting the library calls to invocations of corresponding accelerators, and ... 详细信息
来源: 评论
Efficient Error Detection Cryptographic Architectures Benchmarked on FPGAs for Montgomery Ladder
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2024年 第11期32卷 2154-2158页
作者: Ahmadi, Kasra Aghapour, Saeed Kermani, Mehran Mozaffari Azarderakhsh, Reza Univ S Florida Dept Comp Sci & Engn Tampa FL 33620 USA Florida Atlantic Univ Dept Comp & Elect Engn & Comp Sci Boca Raton FL USA
Elliptic curve scalar multiplication (ECSM) is a fundamental element of public key cryptography. The ECSM implementations on deeply embedded architectures and Internet-of-nano-Things have been vulnerable to both perma... 详细信息
来源: 评论
Multistage Multirate Filterbank for FPGA Resource Optimization
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IEEE EMBEDDED SYSTEMS LETTERS 2024年 第3期16卷 259-262页
作者: Arnaldi, L. H. Bariloche Atom Ctr Lab Detecc Particulas & Radiac R8402AGP San Carlos De Bariloche Argentina Natl Commiss Atom Energy Inst Balseiro R8402AGP San Carlos De Bariloche Argentina
In this letter, the problem of optimization of multirate filterbanks is addressed. The factors that define the efficiency of these multirate systems are investigated and the implementations of structures in stages are... 详细信息
来源: 评论
Approximate Row-Merging-Based Multipliers for Neural Network Acceleration on FPGAs
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IEEE EMBEDDED SYSTEMS LETTERS 2024年 第2期16卷 126-129页
作者: Aizaz, Zainab Khare, Kavita Tirmizi, Aizaz Maulana Azad Natl Inst Technol Dept Elect & Commun Engn Bhopal 462003 India IES Coll Technol Dept Elect & Commun Engn Bhopal 462044 India
Multipliers are one of the most power-hungry arithmetic circuits on hardware neural network accelerators on field programmable gate array (FPGA). In this letter, design of hardware-efficient softcore multipliers using... 详细信息
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An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA
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IEEE EMBEDDED SYSTEMS LETTERS 2024年 第2期16卷 158-161页
作者: Yin, Xiaodi Wu, Zhipeng Li, Dejian Shen, Chongfei Liu, Yu Tianjin Univ Sch Microelect Tianjin 300072 Peoples R China Beijing Smart Chip Microelect Technol Co Ltd Beijing 100089 Peoples R China
field-programmable gate array (FPGA) has become an excellent hardware accelerator solution for convolutional neural networks (CNNs). Meanwhile, optimizing methods, such as model compression, have been proposed. As mos... 详细信息
来源: 评论
Enabling Model-Based Design for Real-Time Spike Detection
IEEE OPEN JOURNAL OF ENGINEERING IN MEDICINE AND BIOLOGY
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IEEE OPEN JOURNAL OF ENGINEERING IN MEDICINE AND BIOLOGY 2025年 6卷 312-319页
作者: Di Florio, Mattia Bornat, Yannick Care, Marta Cota, Vinicius Rosa Buccelli, Stefano Chiappalone, Michela Univ Genoa Dept Informat Bioengn Robot Syst Engn DIBRIS I-16145 Genoa Italy Univ Bordeaux Lab Integrat Mat Syst IMS Bordeaux INP CNRS UMR 5218 F-33405 Talence France IRCCS Osped Policlin San Martino I-16132 Genoa Italy Ist Italiano Tecnol Rehab Technol Lab I-16163 Genoa Italy
Goal: This study addresses the inherent difficulties in the creation of neuroengineering devices for real-time neural signal processing, a task typically characterized by intricate and technically demanding processes.... 详细信息
来源: 评论
Evaluating NTT/INTT Implementation Styles for Post-Quantum Cryptography
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IEEE EMBEDDED SYSTEMS LETTERS 2024年 第4期16卷 485-488页
作者: Imran, Malik Khan, Safiullah Khalid, Ayesha Rafferty, Ciara Shah, Yasir Ali Pagliarini, Samuel Rashid, Muhammad O'Neill, Maire Tallinn Univ Technol Dept Comp Syst EE-19086 Tallinn Estonia Queens Univ Ctr Secure Informat Technol Belfast BT7 1NN North Ireland Manchester Metropolitan Univ Dept Comp & Math Manchester M156BH England Ulster Univ Sch Comp Engn & Intelligent Syst Londonderry BT48 7JL North Ireland Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA Umm Al Qurrah Univ Coll Comp Dept Comp & Network Engn Mecca 24382 Saudi Arabia
Unifying the forward and inverse operations of the number theoretic transform (NTT) into a single hardware module is a common practice when designing polynomial coefficient multiplier accelerators as used in the post-... 详细信息
来源: 评论