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Tracking Error Suppression of Maglev Planar Actuator With FPGA-Based MPC

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷

作者： Zhou, Shun Shi, Yuan Zou, Menglong Xu, Fengqiu Xu, Xianze Wuhan Univ Elect Informat Sch Wuhan 430070 Peoples R China

The precision positioning equipment is essential in many manufacture areas. This article develops a novel noncontact six-degree-of-freedom maglev planar actuator (MLPA) for applications in precision manufacturing area. To achieve the tracking and positioning of MLPA, a model predictive control (MPC) algorithm is introduced. However, the high frequency feedback control of maglev system up to kilohertz level poses the challenges in the online optimization of MPC. We argue that the field-programmable gate array (FPGA), a high throughput and low latency processor, accelerates the computation of MPC, and the high-level synthesis (HLS) tool simplifies the implementation of the optimization algorithm, which is the most complex module in MPC. In this work, the dual-gradient projection method is introduced to realize the online optimization with its characteristics of parallelism. Benefiting from the parallel architecture of FPGA, the dual-gradient projection method successfully runs in the millisecond level with the acceleration performance highlighted by comparing with active set and interior point methods (IPMs). Furthermore, the FPGA-based MPC is deployed for MLPA to inhibit the trajectory tracking error and improve the step response speed. The synthesis of the proposed FPGA-based MPC scheme indicates the prediction horizon of MPC is able to theoretically reach about 20, and the experiments undertaken on the real-time system shows that tracking performance of MLPA is improved with the prediction horizon expanding.

关键词： Photonic crystals Magnetic materials Optimization field programmable gate arrays Actuators Real-time systems Magnetic levitation Computational efficiency Trajectory tracking Signal processing algorithms field-programmable gate array (FPGA) maglev planar actuator (MLPA) precision positioning real-time system

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A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第7期71卷 3318-3322页

作者： Lee, Jaewon Jang, Seoyoung Choi, Yujin Kim, Donggeon Yonar, Serdar Braendli, Matthias Ruffino, Andrea Morf, Thomas Kossel, Marcel Francese, Pier-Andrea Kim, Gain Daegu Gyeongbuk Inst Sci & Technol Dept Elect Engn & Comp Sci Daegu 42988 South Korea IBM Res Hybrid Cloud Res Europe Zurich Lab CH-8803 Ruschlikon Switzerland

This brief presents an RFSoC-based functional verification platform for a 2-lane pulse amplitude modulation (PAM) transceiver (TRX) datapath supporting 4-level PAM (PAM-4) and 8-level PAM (PAM-8). Digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) existing on the ZU28DR RFSoC are used as digital front-ends of the transmitter (TX) and the receiver (RX), respectively. All digital equalization circuits and adaptation engines required for the modern > 112Gb/s DAC/ADC-DSP-based TRX datapath (excluding clock recovery) are implemented on the programmable logic (PL) running at 50 MHz, enabling real-time functional verification of the DAC/ADC-DSP-based serializer-deserializer (SerDes) operation. The register-transfer-level (RTL) design of the DSP can be directly used for the TRX silicon tape-out once the design is verified with the proposed RFSoC-based platform. The proposed system demonstrates a complete real-time functional verification of the TRX datapath, including the bit-error-rate (BER) test with the BER lower than 10(-9) at 6.4Gb/s and 9.6Gb/s for PAM-4/8 symbols, respectively, with a channel loss of 18 dB at 1.6 GHz.

关键词： Clocks field programmable gate arrays Transceivers Protocols Decision feedback equalizers Connectors Table lookup Serial link DAC/ADC-based serial link wireline transceiver pulse amplitude modulation PAM equalization field-programmable gate array FPGA RFSoC

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Low-Power Subgraph Isomorphism at the Edge Using FPGAs

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IEEE ACCESS 2025年 13卷 67127-67135页

作者： Bosio, Roberto Brignone, Giovanni Urso, Teodoro Lazarescu, Mihai T. Lavagno, Luciano Pasini, Paolo Politecn Torino Dept Elect & Telecommun I-10129 Turin Italy

Subgraph matching is a significant problem in several fields, including like social network analysis, chemical compound search, and fraud detection. While current solutions using CPU, graphics processing units (GPUs), and data center field-programmable gate arrays (FPGAs) deliver high performance, they consume significant power, making them unsuitable for resource-constrained edge environments. This article introduces a novel low-power FPGA accelerator that enables efficient subgraph matching using a small FPGA-based accelerator through three main innovations: a flexible two-level hash table architecture that minimizes memory accesses, a caching mechanism that reduces on-chip memory requirements, and a dynamic first-in first-out (FIFO) queue that efficiently buffers partial results. Experimental results on five real-world graphs show that the accelerator reduces energy consumption by an average of ${75 \,\, \times }$ compared to state-of-the-art CPU solutions, and ${107 \,\, \times }$ compared to GPU solutions, demonstrating that complex graph operations can be performed efficiently using even a small accelerator implemented on a reconfigurable platform.

关键词： field programmable gate arrays Graphics processing units Matched filters Hash functions Central Processing Unit System-on-chip Parallel processing Memory management Throughput Space exploration Graph theory FPGA high-level synthesis cache query

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Primate: A Framework to Automatically Generate Soft Processors for Network Applications

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2024年第1期23卷 57-60页

作者： Ma, Rui Hsu, Jia-Ching Mansoorshahi, Ali Garvey, Joseph Kinsner, Michael Singh, Deshanand Chiou, Derek Univ Texas Austin Austin TX 78712 USA Mangoboost Bellevue WA 98005 USA Intel Corp Toronto ON M5S 2X9 Canada Microsoft Redmond WA 98052 USA

Overlay processors on FPGAs enable i) software programmability through sequential code calling library functions, ii) high performance by converting the library calls to invocations of corresponding accelerators, and iii) faster deployment than reprogramming the FPGA. Traditionally, overlays have been hand-written in RTL and programmed through handwritten assembly. We present the Primate framework, which automatically generates overlays from applications written in annotated C++. We evaluated Primate on Whippersnapper (Dang et al. 2017) P4 benchmarks. Primate Overlay latencies are 0.06x - 0.15x compared to PISCES (Shahbaz et al. 2016), a high-performance CPU solution, and 0.25x - 2.3x compared to solutions generated by P4FPGA (Wang et al. 2017), a P4 HLS compiler on FPGA.

关键词： Registers Codes VLIW Software field programmable gate arrays Throughput Libraries Design methodology domain-specific accelerators flexibility programmability

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Efficient Error Detection Cryptographic Architectures Benchmarked on FPGAs for Montgomery Ladder

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2024年第11期32卷 2154-2158页

作者： Ahmadi, Kasra Aghapour, Saeed Kermani, Mehran Mozaffari Azarderakhsh, Reza Univ S Florida Dept Comp Sci & Engn Tampa FL 33620 USA Florida Atlantic Univ Dept Comp & Elect Engn & Comp Sci Boca Raton FL USA

Elliptic curve scalar multiplication (ECSM) is a fundamental element of public key cryptography. The ECSM implementations on deeply embedded architectures and Internet-of-nano-Things have been vulnerable to both permanent and transient errors, as well as fault attacks. Consequently, error detection is crucial. In this work, we present a novel algorithm-level error detection scheme on Montgomery Ladder often used for a number of elliptic curves featuring highly efficient point arithmetic, known as Montgomery curves. Our error detection simulations achieve high error coverage on loop abort and scalar bit flipping fault model using binary tree data structure. Assuming $n$ is the size of the private key, the overhead of our error detection scheme is $O(n)$ . Finally, we conduct a benchmark of our proposed error detection scheme on both ARMv8 and field-programmable gate array (FPGA) platforms to illustrate the implementation and resource utilization. Deployed on Cortex-A72 processors, our proposed error detection scheme maintains a clock cycle overhead of less than 5.2%. In addition, integrating our error detection approach into FPGAs, including AMD/Xilinx Zynq Ultrascale + and Artix Ultrascale + , results in a comparable throughput and less than 2% increase in area compared with the original hardware implementation. We note that we envision using adoptions of the proposed architectures in the postquantum cryptography (PQC) based on elliptic curves.

关键词： Binary trees field programmable gate arrays Elliptic curves Hardware Cryptography Clocks Software ARM processor fault detection field-programmable gate array (FPGA) Montgomery Ladder reliability

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Multistage Multirate Filterbank for FPGA Resource Optimization

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第3期16卷 259-262页

作者： Arnaldi, L. H. Bariloche Atom Ctr Lab Detecc Particulas & Radiac R8402AGP San Carlos De Bariloche Argentina Natl Commiss Atom Energy Inst Balseiro R8402AGP San Carlos De Bariloche Argentina

In this letter, the problem of optimization of multirate filterbanks is addressed. The factors that define the efficiency of these multirate systems are investigated and the implementations of structures in stages are analyzed. The latter, together with the polyphase implementations of the filters, allows obtaining optimal filterbanks in the use of resources for the FPGAs.

关键词： Passband Finite impulse response filters Filtering theory Filter banks field programmable gate arrays Filtering algorithms Cost function Filterbank multirate multistage optimization

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Approximate Row-Merging-Based Multipliers for Neural Network Acceleration on FPGAs

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第2期16卷 126-129页

作者： Aizaz, Zainab Khare, Kavita Tirmizi, Aizaz Maulana Azad Natl Inst Technol Dept Elect & Commun Engn Bhopal 462003 India IES Coll Technol Dept Elect & Commun Engn Bhopal 462044 India

Multipliers are one of the most power-hungry arithmetic circuits on hardware neural network accelerators on field programmable gate array (FPGA). In this letter, design of hardware-efficient softcore multipliers using adaptive logic modules (ALM) is presented. Two partial products (PP) are added using a Karnaugh map (Kmap) to fit on one Intel FPGA ALM in such a way that two consecutive rows of Booth PP matrix are merged. 29.26% energy savings are observed by AR-44 compared to the exact multiplier with a drop of 0.63% accuracy on VGG16 convolutional neural network.

关键词： field programmable gate arrays Application specific integrated circuits Hardware Table lookup Fabrics Energy efficiency Convolutional neural networks field programmable gate array (FPGA) machine learning softcore multiplier

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An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第2期16卷 158-161页

作者： Yin, Xiaodi Wu, Zhipeng Li, Dejian Shen, Chongfei Liu, Yu Tianjin Univ Sch Microelect Tianjin 300072 Peoples R China Beijing Smart Chip Microelect Technol Co Ltd Beijing 100089 Peoples R China

field-programmable gate array (FPGA) has become an excellent hardware accelerator solution for convolutional neural networks (CNNs). Meanwhile, optimizing methods, such as model compression, have been proposed. As most CNN accelerators focus on dense neural networks, to solve the problem of difficult hardware deployment due to irregular networks, we propose a method for sparse neural networks in our work. The storage and coding format of sparse data obtained by the block pruning method is designed to make it friendly to implement on FPGA. Besides, we also propose an efficient and simple data flow by the planarization of the whole convolution calculation process. The experimental result demonstrates that our implementation can achieve clock frequency of 190 MHz, power consumption of 13.32 W and inferencing speed of 16.37 ms. Compared with some typical Mobilenet implementation schemes, our method has been proven to achieve a better balance between frequency, accuracy, power consumption, and speed.

关键词： Convolution field programmable gate arrays Sparse matrices Kernel Encoding Convolutional neural networks Neural networks Block pruning convolutional neural network (CNN) accelerator CNNs field-programmable gate array (FPGA) sparse CNN

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Enabling Model-Based Design for Real-Time Spike Detection

IEEE OPEN JOURNAL OF ENGINEERING IN MEDICINE AND BIOLOGY

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IEEE OPEN JOURNAL OF ENGINEERING IN MEDICINE AND BIOLOGY 2025年 6卷 312-319页

作者： Di Florio, Mattia Bornat, Yannick Care, Marta Cota, Vinicius Rosa Buccelli, Stefano Chiappalone, Michela Univ Genoa Dept Informat Bioengn Robot Syst Engn DIBRIS I-16145 Genoa Italy Univ Bordeaux Lab Integrat Mat Syst IMS Bordeaux INP CNRS UMR 5218 F-33405 Talence France IRCCS Osped Policlin San Martino I-16132 Genoa Italy Ist Italiano Tecnol Rehab Technol Lab I-16163 Genoa Italy

Goal: This study addresses the inherent difficulties in the creation of neuroengineering devices for real-time neural signal processing, a task typically characterized by intricate and technically demanding processes. Beneath the substantial hardware advancements in neurotechnology, there is often rather complex low-level code that poses challenges in terms of development, documentation, and long-term maintenance. Methods: We adopted an alternative strategy centered on Model-Based Design (MBD) to simplify the creation of neuroengineering systems and reduce the entry barriers. MBD offers distinct advantages by streamlining the design workflow, from modelling to implementation, thus facilitating the development of intricate systems. A spike detection algorithm has been implemented on a commercially available system based on a field-programmable gate Array (FPGA) that combines neural probe electronics with configurable integrated circuit. The entire process of data handling and data processing was performed within the Simulink environment, with subsequent generation of hardware description language (HDL) code tailored to the FPGA hardware. Results: The validation was conducted through in vivo experiments involving six animals and demonstrated the capability of our MBD-based real time processing (latency <= 100.37 s) to achieve the same performances of offline spike detection. Conclusions: This methodology can have a significant impact in the development of neuroengineering systems by speeding up the prototyping of various system architectures. We have made all project code files open source, thereby providing free access to fellow scientists interested in the development of neuroengineering systems.

关键词： Hardware design languages Software packages Codes field programmable gate arrays Computer architecture Hardware Signal processing algorithms Neural engineering Signal processing Computational modeling in vivo experiments HDL coder field-programmable gate Array (FPGA) neuroengineering

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Evaluating NTT/INTT Implementation Styles for Post-Quantum Cryptography

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第4期16卷 485-488页

作者： Imran, Malik Khan, Safiullah Khalid, Ayesha Rafferty, Ciara Shah, Yasir Ali Pagliarini, Samuel Rashid, Muhammad O'Neill, Maire Tallinn Univ Technol Dept Comp Syst EE-19086 Tallinn Estonia Queens Univ Ctr Secure Informat Technol Belfast BT7 1NN North Ireland Manchester Metropolitan Univ Dept Comp & Math Manchester M156BH England Ulster Univ Sch Comp Engn & Intelligent Syst Londonderry BT48 7JL North Ireland Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA Umm Al Qurrah Univ Coll Comp Dept Comp & Network Engn Mecca 24382 Saudi Arabia

Unifying the forward and inverse operations of the number theoretic transform (NTT) into a single hardware module is a common practice when designing polynomial coefficient multiplier accelerators as used in the post-quantum cryptographic algorithms. This letter experimentally evaluates that this design unification is not always advantageous. In this context, we present three NTT hardware architectures: 1) a forward NTT (FNTT) architecture;2) an inverse NTT (INTT) architecture;and 3) a unified NTT (UNTT) architecture for computing the FNTT and INTT computations on a single design. We benchmark our throughput/area and energy/area evaluations on Xilinx Virtex-7 field-programmable gate array (FPGA) and 28-nm application-specific integrated circuit (ASIC) platforms. The standalone FNTT and INTT designs, on average on FPGA, exhibit 4.66x and 3.75x higher throughput/area and energy/area values, respectively, than the UNTT design. Similarly, the individual FNTT and INTT designs, on average on ASIC, achieve 1.25x and 1.09x higher throughput/area and energy/area values, respectively, compared to the UNTT design.

关键词： field programmable gate arrays Computer architecture Hardware Polynomials Routing Registers Clocks Application-specific integrated circuit (ASIC) field-programmable gate array (FPGA) number theoretic transform (NTT) polynomial multiplication post-quantum cryptography

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