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检索条件"主题词=Field Programmable Gate Arrays"

共 41626 条记录，以下是541-550 订阅

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FPGA Implementation of Transposed FIR Filter for De-Noising ECG Signals

FPGA Implementation of Transposed FIR Filter for De-Noising ...

引用

Devices for Integrated Circuit (DevIC)

作者： Ramesh Kumar Aytha Kiran Kumar Vasam Pavan Devandla Dept. of Electronics and Communication Engineering VNR Vignana Jyothi Institute of Engineering and Technology Hyderabad India

ISBN: (数字)9798350391107

ISBN: (纸本)9798350391114

An Electrocardiogram (ECG) is a bioelectrical signal that represents the heart's condition by capturing its potential changes. It is a commonly used technique for the early detection and assessment of cardiovascular disease (CVD). However, various types of noise can interfere with the ECG signal during recording, potentially leading to an inaccurate diagnosis. This paper describes the design of an effective ECG denoising method implemented in an FPGA. The design is realized with a transposed FIR filter based on a Vedic multiplier and a Carry Select Adder (CSA) and implemented on an FPGA. FPGAs are reconfigurable and reprogrammable in nature and hence are the best choice for such applications. The transposed FIR filter is chosen for its linear phase response and design flexibility, making it highly suitable for high-performance applications with minimal resource utilization. The proposed design incorporates a high-speed multiplier-accumulator unit and utilizes on-chip memory for rapid access to filter coefficients, significantly enhancing computational efficiency. Simulations and synthesis were performed using MATLAB and Vivado 2022.2. The results demonstrate a substantial improvement in the signal-to-noise ratio (SNR) and a significant reduction in artifacts, leading to clearer and more accurate ECG signal interpretation. The proposed filter achieves lower power consumption, reduced latency, and improved operational efficiency, making it ideal for real-time ECG monitoring.

关键词： Finite impulse response filters Noise reduction Electrocardiography Real-time systems System-on-chip Recording Resource management field programmable gate arrays Adders Signal to noise ratio

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Voltage and Current Universal High-Speed Train Speed Acquisition and Processing Circuit

Voltage and Current Universal High-Speed Train Speed Acquisi...

引用

Advances in Electrical, Electronics and Computing Technology (EECT), International Conference on

作者： Zichen Zhu Qingwen Luan Meiyan Zhang Ping Wang Chenghao Yang CRRC Qingdao Sifang Rolling Stock Research Institute Co. Ltd Qingdao China CRRC Technology Innovation (Beijing) Co. Ltd. Beijing China

ISBN: (数字)9798331541545

ISBN: (纸本)9798331541552

To address the demands for enhancing the safety and efficiency of high-speed railway train operations, this paper designs and implements a universal amplification and filtering circuit suitable for signals from both current-type and voltage-type speed sensors. This circuit not only effectively processes the speed signals transmitted by the speed sensors, converting them into standardized square wave signals recognizable by an FPGA, but also, through advanced algorithms integrated within the FPGA, achieves precise measurement of the frequency of speed pulses, thereby accurately obtaining the actual operating speed of the train. Additionally, this design introduces a line detection mechanism capable of monitoring and reporting line faults in real-time during the speed pulse acquisition process, significantly enhancing the stability and reliability of the system. Experimental results demonstrate that this circuit improves data accuracy while effectively reducing the false alarm rate, providing robust technical support for the safe operation of high-speed train.

关键词： Pulse measurements Reliability engineering Real-time systems Rail transportation Sensors Frequency measurement Safety Integrated circuit reliability field programmable gate arrays Monitoring

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FAAR: A router for field-programmable analog arrays

FAAR: A router for field-programmable analog arrays

引用

12th International Conference on VLSI Design

作者： Ganesan, S Vemuri, R Univ Cincinnati Dept ECECS Lab Digital Design Environm Cincinnati OH 45221 USA

ISBN: (纸本)0769500137

In this paper;we address the routability and analog per performance issues involved in routing for array-based FPAAs that hate single-segment horizontal and vertical muting resources. We then present FAAR (field-programmable Analog Array Router) and describe a routing algorithm developed for the target array-based FPAA architecture. Sequential muting technique is used for routing multi-terminal nets as well as multiple nets. Multi-terminal nets are broken into two-terminal pairs and muted. We use the notion of resource demand as a measure of the effect of a net-route on the muting of the other nets, while the number of programmable switches and the net-crossings are used as the metrics of interconnect parasitics. We present experiments to study the effect of various parameters such as the number of nets, terminals, CABs and IO cells on the renting as well as the performance degradation. FAAR routes with high efficiency while keeping performance degradation small, and has considerably: short execution times.

关键词： field programmable gate arrays

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Power Optimization Of FPGAs Used In Autonomous Vehicles

Power Optimization Of FPGAs Used In Autonomous Vehicles

引用

Advancements in Electrical, Electronics, Communication, Computing and Automation (ICAECA), International Conference on

作者： A Kalaiselvi M. Varshini K. Swasthika R. G. Vijay Prakash Electronics and Communication Engineering Kumaraguru College of Technology Coimbatore India

ISBN: (数字)9798331525439

ISBN: (纸本)9798331525446

Autonomous vehicles represent the forefront of modern technology, integrating robotics, machine learning, and advanced hardware systems for tasks such as object detection and real-time decision-making. This research focuses on enhancing the power efficiency of field programmable gate arrays (FPGAs), a key hardware choice due to their flexibility and parallel processing capabilities. By leveraging Dynamic Voltage and Frequency Scaling (DVFS) alongside a Self-Feedback Convolutional Neural Network (CNN), the proposed system achieves a significant reduction in energy consumption while maintaining performance. The system, implemented on a Xilinx Virtex7 FPGA and tested with the KITTI dataset, demonstrates a power reduction of 65.9% without compromising detection accuracy. This scalable solution provides a foundation for energy-efficient operations in autonomous vehicles.

关键词： Voltage Object detection Parallel processing Logic gates Real-time systems Convolutional neural networks Vehicle dynamics field programmable gate arrays Autonomous vehicles Optimization

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Unified Architecture for High-Performance SDR Platforms

Unified Architecture for High-Performance SDR Platforms

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Digital Signal Processing and its Applications (DSPA), International Conference on

作者： Krutin Denis Ivan Melnik Ivan Varakin Artem Aksenov Institute of Information Technology and Electronics Vladimir State University Vladimir Russia

ISBN: (数字)9798331518752

ISBN: (纸本)9798331518769

The research presents a unified architecture for high-performance software-defined radio (SDR) platforms. The proposed architecture provides flexibility, reconfigurability, and modularity, making it ideal for adapting to the increasing demands of modern communication standards. Utilizing system-on-chip (SoC) and field-programmable gate arrays (FPGAs), this solution streamlines the development and prototyping of specialized radio devices. The results are substantiated by the implementation of next-generation modem prototypes and radio monitoring systems, demonstrating the significant potential of the proposed approach.

关键词： Computer architecture Digital signal processing Modems Mathematical models Libraries field programmable gate arrays Next generation networking Monitoring Software radio Communication standards

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16 Bit Memory and Power Efficient Truncated Booth Multiplier For High Speed Applications/Operations

16 Bit Memory and Power Efficient Truncated Booth Multiplier...

引用

Mobile Computing and Sustainable Informatics (ICMCSI), International Conference on

作者： Yashu Swami T. Senthil Vadivel Department of ECE MRIIRS Faridabad Haryana India Civil Engineering Department MRIIRS Faridabad Haryana India

ISBN: (数字)9798331522667

ISBN: (纸本)9798331522674

We now know that multipliers are a necessary component of all basic circuits. These days, multipliers are the cornerstone of any ALU system. High Radix Booth encoding reduces unfinished product during multiplication, but multipliers also introduce delay and power due to hard multiples. The approximate radix-256 Booth encoding is recommended in order to prevent hard multiples. By shifting and complimenting, a partial encoding method is used to construct partial product pairings. Precise encoding values are determined by adding up matching partial products. For performance testing, a 16x16 bit multiplier with the recommended radix-256 Booth encoding was built. Implementation of a 16-bit Truncated Booth Multiplier on the Nexys 4 DDR FPGA board. and contrast with additional multipliers.

关键词： Memory management Circuits Encoding Delays Logic Informatics Mobile computing field programmable gate arrays Testing Arithmetic

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Power and Area-Efficient ECC Processor with Sequential Recursive Polynomial Multiplier Implementation

Power and Area-Efficient ECC Processor with Sequential Recur...

引用

IEEE International Symposium on Quality Electronic Design

作者： Pruthvi Parate Alwin Shaju Vasanthi D R Madhav Rao IIIT Bangalore

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Elliptic curve cryptography (ECC) is a unique and efficient public-key cryptography method where polynomial multiplication is the primary operation. Thus, ECC efficiency depends largely on effective polynomial multiplier implementation. This work presents a hardware-efficient ECC processor with a clocked data-path using an M-term Hybrid Karatsuba multiplier for GF(2 233 ) Montgomery multiplication. The proposed design was implemented on a Kintex UltraScale FPGA and synthesized with a 45 nm library using Cadence Genus, with the sequential multiplier data path integrated into the ECC processor. The M-Term Non-Homogeneous Overlap-Free Karat-sub a Multiplier (MNHOKA) and Composite M-Term Overlap-Free Karatsuba-like Multiplier (CMOKA) multipliers, integrated into ECC processors, achieved top hardware efficiency on FPGA and silicon, surpassing all other variants and SOTA multipliers. The clocked MNHOKA-adopted ECC processor achieved LUT savings of 56.11% and a Figure-of-Merit (FoM) improvement of 74.73% in FPGA over the best SOTA design. On silicon, the sequential design of Overlap-Free Karatsuba Multiplier (OKA) incorporated ECC processor exhibited maximum footprint savings of 45.70% and clocked MNHOKA incorporated ECC processor exhibited maximum power saving of 73.00% over the best SOTA design. The innovative and hardware-efficient ECC accelerator design files are made freely available for further usage to the designers and engineering community.

关键词： Performance evaluation Memory Elliptic curve cryptography Polynomials Silicon Libraries Table lookup Resource management Internet of Things field programmable gate arrays

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A Design of Fault-Tolerant System for Safety-Critical Systems

A Design of Fault-Tolerant System for Safety-Critical System...

引用

International Conference on Autonomous Robots and Agents, ICARA

作者： Kai Yoshizawa Nobuyuki Yamasaki Graduate School of Science and Technology Keio University Yokohama Japan

ISBN: (数字)9798331509231

ISBN: (纸本)9798331509248

In safety-critical systems where failures or faults can lead to accidents, especially in special and harsh environments like those encountered in spacecraft, it is well known that multiple levels of errors can significantly increase the likelihood of system failure. For instance, system-level errors may occur due to cable breaks caused by severe vibrations, while gate-level errors can arise from radiation effects on System-on-Chip (SoC) semiconductors. Furthermore, in such specialized environments, human repair is often not feasible, necessitating that the system continue to operate even when a fault occurs in a part of it. Therefore, this research discusses the design, implementation, and evaluation of a redundant system that combines multi-level redundancy mechanisms to tolerate multiple errors and maintain operation. The implementation was carried out on the Space I/O Core (SIOC), a System-on-Chip equipped with processors and I/O for distributed real-time systems. Additionally, bitstreams were created from the implemented logic, and the performance of the fault-tolerant system was evaluated using an actual FPGA.

关键词： Vibrations Space vehicles Redundancy Fault tolerant systems Termination of employment Switches Logic gates System-on-chip field programmable gate arrays Robots

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An Efficient Reconfigurable Parameterized Convolutional Neural Network Accelerator on FPGA Platform

An Efficient Reconfigurable Parameterized Convolutional Neur...

引用

IEEE International Conference on Consumer Electronics (ICCE)

作者： Yeong-Kang Lai Chien-Hung Lin Department of the Electrical Engineering Master Program in Semiconductor and Green Technology National Chung Hsing University Taichung Taiwan R.O.C

ISBN: (数字)9798331521165

ISBN: (纸本)9798331521172

This paper presents an efficient reconfigurable parameterized convolutional neural network (CNN) accelerator designed for FPGA platforms. The core of the accelerator allows flexible adjustments of input channel parallelism (Pc) and convolution filter parallelism (Pn) to meet the needs of various CNN models, optimizing both resource utilization and computational efficiency. The architecture is applied specifically to infrared (IR) and visible light (VI) image fusion, enabling real-time processing on an FPGA with significantly reduced latency. Experimental results demonstrate that the accelerator reduces latency to 192 ms while maintaining high image quality, achieving efficient image fusion on the FPGA platform.

关键词： Image quality Convolution Computer architecture Parallel processing Real-time systems Convolutional neural networks Resource management Image fusion field programmable gate arrays Hardware acceleration

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Multi-vendor encoder position sensing interface using programmable IP based solution

Multi-vendor encoder position sensing interface using progra...

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Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)

作者： Rajul Bhambay Dhaval Khandla Pratheesh Gangadhar Thomas Leyrer Achala Ram Manoj Koppolu Archit Dev Embedded Processors Texas Instruments Inc. Bengaluru India Embedded Processors Texas Instruments Inc. Munich Germany

ISBN: (数字)9798331516116

ISBN: (纸本)9798331516123

The aim of this work is to look at a software programmable solution for multi-vendor encoders protocol in which TI utilizes "Three Channel Peripheral Interface (3CPI)" or general purpose inputs (GPIs)/general purpose outputs (GPOs) in programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS) on Texas Instruments AM24x/AM26x micro-controllers (MCUs) and AM64x processors [10] –[12]. Existing solutions are FPGA based which come with a few challenges like high power consumption, high cost, and latency in operating control loop. This approach cuts down huge amount of cost by not implementing with FPGA, but using programmable IP and offloading MCUs or processors CPU load via PRU-ICSS. It also has the capability to optimize control loop, by moving the position data after validation and post processing to the tightly coupled memory of CPU running control loop. This makes TI’s solution cost effective and low latency in terms of running control loop, highly flexible and scalable in terms of implementing multiple vendor encoder interfaces.

关键词： Costs Program processors Protocols Industrial communication Process control Real-time systems Software System-on-chip Sensors field programmable gate arrays

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