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DSCAM: Latency-Guaranteed and High-Capacity Content-Addressable Memory on FPGAs

IEEE EMBEDDED SYSTEMS LETTERS 2024年第2期16卷 182-185页

作者： Vakili, Shervin Zarei, Amirhossein INRS Univ Energie Mat Telecommun Res Ctr Montreal PQ H5A 1K6 Canada

This letter introduces an original and highly efficient method to implement high-capacity content-addressable memories on field programmable gate arrays (FPGAs). The method includes a new hardware architecture and an optimization technique to determine crucial design parameters. The memory contents are partially synthesized and implemented on FPGA logic fabrics. The proposed architecture offers high throughput and fixed-latency searches. Experimental results show that the proposed method enables the implementation of an IPv4 forwarding table with over 520 K prefixes on a cost-effective AMD-Xilinx UltraScale + FPGA, providing a lookup latency of less than 28 ns and a minimum throughput of 215 million lookups per second. The source code of this work is available on GitHub.

关键词： Hardware field programmable gate arrays Multiplexing Throughput Random access memory Optimization Table lookup Content-addressable memory (CAM) field programmable gate array (FPGA) IP address lookup

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CollectiveHLS: Ultrafast Knowledge-Based HLS Design Optimization

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第2期16卷 235-238页

作者： Ferikoglou, Aggelos Kakolyris, Andreas Kypriotis, Vasilis Masouros, Dimosthenis Soudris, Dimitrios Xydis, Sotirios Natl Tech Univ Athens Sch Elect & Comp Engn Zografos 15780 Greece

High-level synthesis (HLS) has democratized field programmable gate arrays (FPGAs) by enabling high-level device programmability and rapid microarchitecture customization through the use of directives. Nevertheless, the manual selection of the appropriate directives, i.e., the annotations included in the high-level source code to instruct the synthesis process, is a difficult task for programmers without a hardware background. In this letter, we present CollectiveHLS, an ultrafast knowledge-based HLS design optimization method that automatically extracts the most promising directive configurations and applies them to the original source code. The proposed optimization scheme is a fully data-driven approach for generalized HLS tuning, as it is not based on quality of result models or meta-heuristics. We design, implement, and evaluate our method with more than 100 applications of Machsuite, Rodinia, and GitHub on a ZCU104 FPGA. We achieve an average geometric mean speedup of x14.1 and x10.5 compared to the unoptimized, i.e., without HLS directives and optimized designs, a high design feasibility score, and an average inference latency of 38 ms.

关键词： Source coding Optimization Knowledge based systems field programmable gate arrays Measurement Sociology Pareto optimization Collective data-driven design space exploration (DSE) field programmable gate array (FPGA) high-level synthesis (HLS)

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Design and Evaluation of a 2Mbps SEC Transceiver for Automotive Networks

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2024年第6期71卷 3021-3025页

作者： D'Aniello, Federico Ott, Andreas Baschirotto, Andrea Univ Milano Bicocca Dept Phys G Occhialini I-20126 Milan Italy Melexis GmbH Dev Dept D-99099 Erfurt Germany

In this brief, a Supply Embedded Communication (SEC) transceiver for automotive networks is proposed. In an SEC approach, power supply and communication take place on the same differential bus and thus the number of required cables is drastically reduced, leading to space, raw material consumption, and cost advantages. The proposed transceiver is realized in 180nm SOI CMOS technology and is capable of implementing 2Mbps high-speed networks. In addition to proving nominal transient operation, some critical aspects for an automotive application are analyzed. Electromagnetic compatibility (EMC) is evaluated by conducting emission tests, and finally, the robustness to external disturbances is tested by direct power injection (DPI) tests.

关键词： Transceivers Hysteresis Capacitors Switching circuits field programmable gate arrays Automotive engineering Transmitters Supply embedded communication (sec) automotive networks transceiver communication bus electromagnetic compatibility (EMC) direct power injection (DPI) test

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A Study in Specification and Hardware Runtime Verification of Critical Embedded Software

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IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING 2025年第3期22卷 2258-2269页

作者： Solet, Dimitry Bechennec, Jean-Luc Briday, Mikael Faucou, Sebastien Pillement, Sebastien ESEO F-49100 Angers France Nantes Univ Ecole Cent Nantes CNRS LS2N F-44000 Nantes France Nantes Univ IETR UMR 6164 F-44300 Nantes France

We evaluate HARVEST (Hardware Accelerated Runtime Verification for Embedded SofTware), a runtime error detection mechanism for embedded software running on standard SoPC architectures, i.e., one (or more) processor(s) and an FPGA on a single chip. The program under monitoring runs on the processor(s), while a trace analysis module running on the FPGA detects errors in its execution. The hardware implementation of trace analysis minimizes the performanceimpact and achieves a very low error reporting latency (a few processor cycles). In this article, we evaluate the suitability of using HARVEST to detect errors resulting from transient physical faults. We explain how HARVEST is used to monitor a complex software component (Trampoline RTOS) on a commercially available hardware platform (Microchip SmartFusion2). We measure the overhead of the resulting instrumentation on system resources. We then evaluate its performance in detecting silent data corruptions, based on a systematic simulation of bit flips at the instruction set architecture level. We report a detection rate of up to 90.2% for a fairly low system resource overhead, suggesting an interesting trade-off for designers of highly constrained critical systems.

关键词： Monitoring Runtime Hardware field programmable gate arrays Computer architecture Kernel Embedded software Registers Real-time systems Logic Computers and information processing error analysis fault tolerance fault tolerant computing industrial electronics reliability software software safety systems system testing testing

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Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic Injection

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第2期16卷 162-165页

作者： Valente, Giacomo Muttillo, Vittoriano Federici, Fabio Pomante, Luigi Di Mascio, Tania Univ Aquila Dept Informat Engn Comp Sci & Math I-67100 Laquila Italy Univ Teramo Dept Polit Sci I-64100 Teramo Italy Collins Aerosp Appl Res & Technol I-00185 Rome Italy

Modern real-time systems started leveraging runtime reconfigurable architectures to reduce size, weight, and power while ensuring predictability. However, the time to reconfigure a platform (referred to as reconfiguration delay) is non-negligible and subject to fluctuations caused by conflicts in accessing shared components during the reconfiguration process. Different from existing solutions that impact either system resources or system performance, in this letter, we propose an approach, together with its supporting tools, allowing to characterize the reconfiguration delay and to be able to capture and produce evidence of the actual impact of the resource contention. In addition, we report the experiments of the proposed approach in a representative configuration on a Xilinx Zynq Ultrascale+ MPSoC;results show that conflicts can impact the reconfiguration delay at most by 230%.

关键词： Delays field programmable gate arrays Real-time systems Random access memory Interference channels Quality of service Memory management Dynamic reconfiguration field-programmable gate array (FPGA) system-on-chip (SoC)

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Toward Precision-Aware Safe Neural-Controlled Cyber-Physical Systems

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第4期16卷 397-400页

作者： Thevendhriya, Harikishan Ghosh, Sumana Lohar, Debasmita Indian Stat Inst Comp Sci Div Kolkata 700108 India Karlsruhe Inst Technol KASTEL D-76131 Karlsruhe Germany

The safety of neural network (NN) controllers is crucial, specifically in the context of safety-critical Cyber-Physical System (CPS) applications. Current safety verification focuses on the reachability analysis, considering the bounded errors from the noisy environments or inaccurate implementations. However, it assumes real-valued arithmetic and does not account for the fixed-point quantization often used in the embedded systems. Some recent efforts have focused on generating the sound quantized NN implementations in fixed-point, ensuring specific target error bounds, but they assume the safety of NNs is already proven. To bridge this gap, we introduce Nexus, a novel two-phase framework combining reachability analysis with sound NN quantization. Nexus provides an end-to-end solution that ensures CPS safety within bounded errors while generating mixed-precision fixed-point implementations for the NN controllers. Additionally, we optimize these implementations for the automated parallelization on the FPGAs using a commercial HLS compiler, reducing the machine cycles significantly.

关键词： Quantization (signal) Embedded systems Artificial neural networks Cyber-physical systems Hardware Safety Noise measurement Reachability analysis field programmable gate arrays Optimization Cyber-physical system (CPS) quantization reachability analysis

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FPGA Implementation of the Proposed DCNN Model for Detection of Tuberculosis and Pneumonia Using CXR Images

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第4期16卷 445-448页

作者： Guddati, Prabhav Dash, Shaswati Tripathy, Rajesh Kumar BITS Pilani Dept EEE Hyderabad Campus Hyderabad 500078 India

The automated detection of tuberculosis (TB) and pneumonia (PN) from chest X-ray (CXR) images using artificial intelligence (AI) is challenging in clinical studies for rapid diagnosis and initiation of treatment. This letter proposes the field-programmable gate array (FPGA)-based hardware implementation of a novel lightweight deep convolutional neural network (DCNN) model to detect PN and TB ailments using CXR images. Initially, the proposed DCNN (consisting of ten layers) is trained using the Google Cloud central processing unit (CPU) to obtain the model weight and bias parameters. Then, the register transfer logic (RTL) for the trained DCNN model is generated by the VIVADO high-level synthesis (HLS) framework using HLS for machine learning (HLS4ML) with fixed-point representation (8 bit for integer and 12 bit for the fractional part). The hardware implementation of the suggested DCNN model is performed using the PYNQ-Z2 FPGA framework to detect TB and PN diseases automatically. The experimental results demonstrate that the proposed DCNN model has obtained accuracy values of 96.39% and 95.63% on the Google-Cloud CPU and PYNQ-Z2 FPGA frameworks using 422 CXR images in the inference phases. The inference time of the proposed DCNN model on the PYNQ-Z2 FPGA framework is reduced by 85.19% compared to the CPU-based implementation. The suggested DCNN model has only 1831 parameters, less than the transfer learning (TFL) and existing CNN-based models to detect TB and PN using CXR images.

关键词： Diseases field programmable gate arrays Computational modeling Hardware Feature extraction Training Image edge detection Accuracy chest X-ray (CXR) deep convolutional neural network (DCNN) field-programmable gate array (FPGA) high-level synthesis (HLS) pneumonia (PN) PYNQ-Z2 tuberculosis (TB)

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Experimental Investigation of Side-Channel Attacks on Neuromorphic Spiking Neural Networks

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第2期16卷 231-234页

作者： Goswami, Bhanprakash Das, Tamoghno Suri, Manan Indian Inst Technol Delhi Dept Elect Engn New Delhi 110016 India

This study investigates the reliability of commonly utilized digital spiking neurons and the potential side-channel vulnerabilities in neuromorphic systems that employ them. Through our experiments, we have successfully decoded the parametric information of Izhikevich and leaky integrate-and-fire (LIF) neuron-based spiking neural networks (SNNs) using differential power analysis. Furthermore, we have demonstrated the practical application of extracted information from the 92% accurate pretrained standard spiking convolution neural network classifier on the FashionMNIST dataset. These findings highlight the potential dangers of utilizing internal information for side-channel and denial-of-service attacks, even when using the usual input as the attack vector.

关键词： Neurons Power distribution field programmable gate arrays Firing Threshold voltage Power demand Convolution Neuromorphic hardware side-channel attack

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Real-time fully digital control scheme for pulse coherent beam combining

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OPTICS LETTERS 2024年第21期49卷 6333-6336页

作者： Wu, Yong Wang, Xinyu Pu, Guoqing Zhang, Xuguang Liu, Chenxu Dong, Kegong Hu, Weisheng Yi, Lilin Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn State Key Lab Adv Commun Syst & Networks Shanghai 200240 Peoples R China Chinese Acad Engn & Phys Laser Fus Res Ctr Mianyang 621900 Peoples R China

A fully digital control scheme for non-polarizationcombining (CBC) is proposed, where digital locking of optical coherence by single-detector electronic-frequency tagging (LOCSET) for active phase control and stochastic parallel gradient descent (SPGD) for active polarization control is proposed. The fully digital control scheme is integrated on a real-time field-programmable gate array (FPGA) empowered hardware platform and then experimentally validated in a four-channel all-fiber non-fully polarization-maintaining nanosecond pulse CBC system. Consequently, the system can be fully locked in 9.5 ms, and the polarization extinction ratio (PER) of the combined beam is 21.5 dB with a CBC efficiency of 95.3%. are reserved.

关键词： Extinction ratios field programmable gate arrays Nanosecond pulses Nonlinear frequency conversion Phase noise Polarization control

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Highly secure OFDM scheme based on multi-level masking and performance-enhanced key accompanying transmission

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OPTICS LETTERS 2024年第24期49卷 6936-6939页

作者： Yin, Mengtong Liu, Bo Ren, Jianxin Mao, Yaya Chen, Shuaidong Wu, Xiangyu Li, Ying Zhao, Lilong Zhu, Dongxu Nanjing Univ Informat Sci & Technol Inst Opt & Elect Nanjing 210044 Peoples R China Nanjing Univ Informat Sci & Technol Jiangsu Key Lab Optoelect Detect Atmosphere & Ocea Nanjing 210044 Peoples R China Nanjing Univ Informat Sci & Technol Jiangsu Int Joint Lab Meteorol Photon & Optoelect Nanjing 210044 Peoples R China Beijing Univ Posts & Telecommun Beijing 100876 Peoples R China Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Nanjing Univ Posts & Telecommun Nanjing 210003 Peoples R China

In this Letter, we propose a highly secure OFDM scheme based on multi-level masking and performance-enhanced key-accompanying transmission. Our scheme exploits a fourdimensional hyperchaotic model and uses subcarriers and symbols to scramble the signal, thereby achieving chaotic encryption and enhancing system security. The dual-mode index technique is employed to conceal the key within the encrypted signal, enabling cooperative transmission of both the key and the signal. We conducted experiments that successfully transmitted a 28 Gb/s dual-mode QPSK (DMQPSK) signal and a 42 Gb/s dual-mode 8QAM (DM-8QAM) signal over a 2-km stretch of 7-core fiber. The results demonstrated that our proposed key-accompanying transmission scheme did not compromise the system's transmission performance. Moreover, the key space of this scheme is as large as 10135, effectively ensuring system security. Under the received optical power corresponding to the bit error rate of 3.8 x 10-3, the minimum number of key repetitions in DM-8QAM that makes the key bit error rate zero is less than 9 times. This demonstrates that our proposed scheme effectively enhances the transmission performance of the key, achieving high-quality joint transmission of both the key and the signal. (c) 2024 Optica Publishing Group. All rights, including for text and data mining (TDM), Artificial Intelligence (AI) training, and similar technologies, are reserved.

关键词： Bit error rate field programmable gate arrays Light beams Optical signals Quadrature phase shift keying Signal transmission

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