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检索条件"主题词=Field Programmable Gate Arrays"

共 41642 条记录，以下是551-560 订阅

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Simplified Implementation of Histogram Equalization Using Approximation Offset

Simplified Implementation of Histogram Equalization Using Ap...

引用

Cognitive Computing in Engineering, Communications, Sciences and Biomedical Health Informatics (IC3ECSBHI), International Conference on

作者： Chetan Singh Rajput Sandeep Sharma Rajesh Mishra School of Information and Communication Technology Goutam Buddha University Greater Noida India Department of Higher and Technical Education Government of Jharkhand Ranchi India

ISBN: (数字)9798331518523

ISBN: (纸本)9798331518530

This paper presents a simplified implementation of Histogram Equalization by adding offset values to the Histogram bins. The proposed approach helps to simplify the division/multiplication operations in Histogram Equalization calculation using shift operations. This approach is tested on different resolutions of gray images. The image quality comparison of this approach with conventional Histogram equalization shows that the proposed simplified implementation is effective for lower values of approximation offset.

关键词： Image quality Histograms Image resolution Costs Codes Transfer functions Hardware Entropy Cognitive systems field programmable gate arrays

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Ph.D. Project ARIES: Efficient Mapping and Automated Compilation for AMD Versal Devices

Ph.D. Project ARIES: Efficient Mapping and Automated Compila...

引用

Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Jinming Zhuang Peipei Zhou Brown University

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

As AI continues to grow, modern applications are becoming more memory and computation intensive, driving the development of specialized AI chips to meet these demands. AMD Versal ACAP devices serve as a promising heterogeneous solution for continuous compute scaling. However, heterogeneity presents challenges not only in achieving high-performance mapping solutions but also in providing a programming abstraction that ensures high productivity. If these challenges are not effectively addressed, they will hinder the widespread adoption of these heterogeneous architectures by experts from other domains beyond hardware expertise. We are among the first to explore efficient mapping solutions for this heterogeneous system. We propose a series of works (FPGA'23 [1], DAC‘23 [2], TRETS‘24 [3], FPGA‘24 [4], TCAD‘24 [5]), which thoroughly investigate the design space for modern transformer-based workloads by mapping different layers to various system components, such as CPUs, FPGAs, and AIEs, while analyzing the trade-offs between latency and throughput. Additionally, to significantly enhance programming productivity on these heterogeneous systems, we are the first to introduce ARIES (FPGA'25 [6] Best Paper Nominee), a multi-level intermediate representation (MLIR)-based compilation framework that proposes a unified intermediate representation (IR) for the end-to-end application deployment on AIE architectures.

关键词： Productivity AI accelerators Computer architecture Programming Transformers Throughput Hardware field programmable gate arrays

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Layer-Specific Hardware Pooling Designs for CNN Accelerators

Layer-Specific Hardware Pooling Designs for CNN Accelerators

引用

International Conference on VLSI Design

作者： Vinay Rayapati Mahati Basavaraju Madhav Rao IIIT Bangalore India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

This paper proposes and explores the impact of using Combinatorial Pooling techniques - the combination of widely used Max pooling and SOTA Deviation based pooling techniques such as Absolute Average Deviation (AAD) or Binary Weighted Absolute Deviation (BWAD) or Absolute Maximum Deviation (AMD), across different layers in CNN architectures. The design-space exploration suggests the best possible combination of pooling schemes to be adopted for realizing hardware-efficient CNN accelerators in the future. The proposed Combinatorial pooling schemes offer enhanced model accuracy in AlexNet, UNet, and VGG-16 CNN architectures, besides offering substantial hardware gains, when compared to sole usage of deviation based pooling techniques. The results obtained from FPGA synthesis on Xilinx Zedboard are presented for a single cumulative unit of convolution and pooling operation for Max, AAD, BWAD and AMD methods. ASIC Synthesis results using Cadence 45 nm technology library are showcased for exhaustive combinations when implemented for all convolution and pooling layers in VGG-16 and AlexNet CNN architectures. For AlexNet, the unique sequence “110” with BWAD (BWAD-BWAD-Max), offers footprint savings of 4.27%, 14.77%, 11.87%, and 14.64%, over the regular individual pooling methods of Max, AAD, BWAD and AMD respectively. It also exhibits 6.67% increase in accuracy over the SOTA best.

关键词： Measurement Accuracy Embedded systems Convolution Very large scale integration Hardware Libraries Convolutional neural networks field programmable gate arrays

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Simulation of Analog Filter Using Digital Element Base

Simulation of Analog Filter Using Digital Element Base

引用

Systems of Signals Generating and Processing in the field of on Board Communications

作者： P. S. Martyanov Scientific and Technological Center of Unique instrumentation of the Russia Academy of Sciences (STC UI RAS) Moscow Russia

ISBN: (数字)9798331532635

ISBN: (纸本)9798331532642

It has been suggested to design analog devices using elementary units of the automatic control theory in order to reduce the labor consumption of the design process. The elementary units have been simulated and implemented on the basis of digital elements. It has been shown that the elementary units studied can be configured into specific analog devices. The correctness of the suggested method has been verified for the example of the simulation and design of an analog filter circuit on the basis of digital elements

关键词： Design methodology Printed circuits Process control Digital signal processing Filtering theory Digital filters field programmable gate arrays Testing

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Implementation Research of Tiny ML on RISC-V Platform Using Efinix Platform for Real Time Person Detection

Implementation Research of Tiny ML on RISC-V Platform Using ...

引用

International Colloquium on Signal Processing & Its Applications, CSPA

作者： Yeap Wei Hao Cheong Choon Min Roslee Mohd Sabri Richard Lai Tian Fat Su Hsiao Wei Hazwan Halim Solahuddin Yusuf Fadhlullah School of Engineering INTI international College Penang Bayan Lepas Pulau Penang Malaysia MIMOS Berhad Technology Park Malaysia Bukit Jalil Kuala Lumpur Malaysia

ISBN: (数字)9798331522193

ISBN: (纸本)9798331522209

The rapid advancements in artificial intelligence (AI) and computer vision have revolutionized intelligent security systems, addressing challenges related to cost, efficiency, and scalability. This paper investigates the application of Tiny Machine Learning (TinyML) on the RISC-V platform, utilizing the Efinix Ti60 F225 FPGA for real-time person detection. The study aims to harness the energy efficiency, flexibility, and scalability of the RISC-V architecture to develop a cost-effective and sustainable solution for intelligent security applications. The proposed system combines the YOLO model for person detection with TinyML techniques, enabling real-time processing while maintaining an accuracy of 80% for individuals within a 2-meter range. Hardware components, such as the Raspberry Pi Camera Module V2 and Mini DSI Panel, were employed to capture and display real-time imagery. Comprehensive evaluations demonstrated the system's performance advantages, including reduced latency, low power consumption, and minimal bandwidth usage, emphasizing the benefits of deploying AI at the edge. Although challenges such as environmental variability and memory limitations were encountered, the findings highlighted the potential of integrating TinyML with RISC-V platforms for intelligent security applications. The results contributed to the field of edge computing and open-source hardware, presenting a viable approach to energy-efficient and scalable AI solutions. Future research will focus on overcoming hardware constraints, extending the detection range, and incorporating adaptive learning capabilities to enhance system robustness and functionality further.

关键词： YOLO Reduced instruction set computing Costs Tiny machine learning Scalability Real-time systems Energy efficiency Security Artificial intelligence field programmable gate arrays

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Compute-In-Memory on FPGAs for Deep Learning: A Review

Compute-In-Memory on FPGAs for Deep Learning: A Review

引用

Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Aman Arora Arizona State University

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

field-programmable gate arrays (FPGAs) are increasingly recognized as an efficient platform for accelerating Deep Learning (DL) applications. This is due to their hardware-level configurability, which allows for tailored datapaths and low-precision inference capabilities. As data-intensive applications such as DL continue to grow, there is a renewed interest in Compute-In-Memory (CIM) architectures to address the bottle-neck caused by moving large volumes of data between memory blocks (off-chip or on-chip) and compute units. This paper delves deep into CIM architectures designed for FPGAs, focusing on making FPGAs better accelerators of DL applications. This paper provides an overview of CIM and FPGA architecture, motivating the need to design custom FPGA architectures with CIM capability. Detailed insights into CIM operation on FPGAs and the implementation of CIM on FPGAs are presented, focusing on modifications to the memory blocks on FPGAs. Existing FPGA CIM proposals are categorized and the nuances of architecting CIM blocks for FPGAs are explained. Lastly, it outlines the current challenges that must be addressed to facilitate broader adoption of CIM architectures on FPGAs.

关键词： Deep learning Reviews Focusing Computer architecture In-memory computing Common Information Model (computing) System-on-chip Proposals field programmable gate arrays

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FPGA Implementation of Transposed FIR Filter for De-Noising ECG Signals

FPGA Implementation of Transposed FIR Filter for De-Noising ...

引用

Devices for Integrated Circuit (DevIC)

作者： Ramesh Kumar Aytha Kiran Kumar Vasam Pavan Devandla Dept. of Electronics and Communication Engineering VNR Vignana Jyothi Institute of Engineering and Technology Hyderabad India

ISBN: (数字)9798350391107

ISBN: (纸本)9798350391114

An Electrocardiogram (ECG) is a bioelectrical signal that represents the heart's condition by capturing its potential changes. It is a commonly used technique for the early detection and assessment of cardiovascular disease (CVD). However, various types of noise can interfere with the ECG signal during recording, potentially leading to an inaccurate diagnosis. This paper describes the design of an effective ECG denoising method implemented in an FPGA. The design is realized with a transposed FIR filter based on a Vedic multiplier and a Carry Select Adder (CSA) and implemented on an FPGA. FPGAs are reconfigurable and reprogrammable in nature and hence are the best choice for such applications. The transposed FIR filter is chosen for its linear phase response and design flexibility, making it highly suitable for high-performance applications with minimal resource utilization. The proposed design incorporates a high-speed multiplier-accumulator unit and utilizes on-chip memory for rapid access to filter coefficients, significantly enhancing computational efficiency. Simulations and synthesis were performed using MATLAB and Vivado 2022.2. The results demonstrate a substantial improvement in the signal-to-noise ratio (SNR) and a significant reduction in artifacts, leading to clearer and more accurate ECG signal interpretation. The proposed filter achieves lower power consumption, reduced latency, and improved operational efficiency, making it ideal for real-time ECG monitoring.

关键词： Finite impulse response filters Noise reduction Electrocardiography Real-time systems System-on-chip Recording Resource management field programmable gate arrays Adders Signal to noise ratio

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Voltage and Current Universal High-Speed Train Speed Acquisition and Processing Circuit

Voltage and Current Universal High-Speed Train Speed Acquisi...

引用

Advances in Electrical, Electronics and Computing Technology (EECT), International Conference on

作者： Zichen Zhu Qingwen Luan Meiyan Zhang Ping Wang Chenghao Yang CRRC Qingdao Sifang Rolling Stock Research Institute Co. Ltd Qingdao China CRRC Technology Innovation (Beijing) Co. Ltd. Beijing China

ISBN: (数字)9798331541545

ISBN: (纸本)9798331541552

To address the demands for enhancing the safety and efficiency of high-speed railway train operations, this paper designs and implements a universal amplification and filtering circuit suitable for signals from both current-type and voltage-type speed sensors. This circuit not only effectively processes the speed signals transmitted by the speed sensors, converting them into standardized square wave signals recognizable by an FPGA, but also, through advanced algorithms integrated within the FPGA, achieves precise measurement of the frequency of speed pulses, thereby accurately obtaining the actual operating speed of the train. Additionally, this design introduces a line detection mechanism capable of monitoring and reporting line faults in real-time during the speed pulse acquisition process, significantly enhancing the stability and reliability of the system. Experimental results demonstrate that this circuit improves data accuracy while effectively reducing the false alarm rate, providing robust technical support for the safe operation of high-speed train.

关键词： Pulse measurements Reliability engineering Real-time systems Rail transportation Sensors Frequency measurement Safety Integrated circuit reliability field programmable gate arrays Monitoring

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FAAR: A router for field-programmable analog arrays

FAAR: A router for field-programmable analog arrays

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12th International Conference on VLSI Design

作者： Ganesan, S Vemuri, R Univ Cincinnati Dept ECECS Lab Digital Design Environm Cincinnati OH 45221 USA

ISBN: (纸本)0769500137

In this paper;we address the routability and analog per performance issues involved in routing for array-based FPAAs that hate single-segment horizontal and vertical muting resources. We then present FAAR (field-programmable Analog Array Router) and describe a routing algorithm developed for the target array-based FPAA architecture. Sequential muting technique is used for routing multi-terminal nets as well as multiple nets. Multi-terminal nets are broken into two-terminal pairs and muted. We use the notion of resource demand as a measure of the effect of a net-route on the muting of the other nets, while the number of programmable switches and the net-crossings are used as the metrics of interconnect parasitics. We present experiments to study the effect of various parameters such as the number of nets, terminals, CABs and IO cells on the renting as well as the performance degradation. FAAR routes with high efficiency while keeping performance degradation small, and has considerably: short execution times.

关键词： field programmable gate arrays

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Power Optimization Of FPGAs Used In Autonomous Vehicles

Power Optimization Of FPGAs Used In Autonomous Vehicles

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Advancements in Electrical, Electronics, Communication, Computing and Automation (ICAECA), International Conference on

作者： A Kalaiselvi M. Varshini K. Swasthika R. G. Vijay Prakash Electronics and Communication Engineering Kumaraguru College of Technology Coimbatore India

ISBN: (数字)9798331525439

ISBN: (纸本)9798331525446

Autonomous vehicles represent the forefront of modern technology, integrating robotics, machine learning, and advanced hardware systems for tasks such as object detection and real-time decision-making. This research focuses on enhancing the power efficiency of field programmable gate arrays (FPGAs), a key hardware choice due to their flexibility and parallel processing capabilities. By leveraging Dynamic Voltage and Frequency Scaling (DVFS) alongside a Self-Feedback Convolutional Neural Network (CNN), the proposed system achieves a significant reduction in energy consumption while maintaining performance. The system, implemented on a Xilinx Virtex7 FPGA and tested with the KITTI dataset, demonstrates a power reduction of 65.9% without compromising detection accuracy. This scalable solution provides a foundation for energy-efficient operations in autonomous vehicles.

关键词： Voltage Object detection Parallel processing Logic gates Real-time systems Convolutional neural networks Vehicle dynamics field programmable gate arrays Autonomous vehicles Optimization

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