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Development of Radiation-Tolerant Slow-Control Board Based on Atom Switch-Based FPGA

IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第4期72卷 1525-1530页

作者： Ueno, Kazuki Taniguchi, Nanae Sakamoto, Toshitsugu Miyamura, Makoto Osaka Univ Dept Phys Osaka 5600043 Japan KEK Inst Particle & Nucl Studies Tsukuba 3050801 Japan NanoBridge Semicond Inc Tsukuba 3050047 Japan

The atom switch-based FPGA (AS-FPGA) is a promising candidate for high-radiation environments, such as those encountered in future particle physics experiments using accelerators. To assess its feasibility, we conducted neutron and gamma-ray irradiation tests. No single-event upsets (SEUs) were detected at least up to 1011 and 1012 n/cm(2) with and without applied voltage, respectively. The AS-field-programmable gate array (FPGA) withstood displacement damage dose (DDD) levels at least up to 1014 n/cm2 and exhibited no total ionizing dose (TID) effects at least up to 5 and 10 kGy with and without applied voltage, respectively. These results confirm its suitability for high-radiation environments. To facilitate its practical application, we developed an evaluation board to investigate its functions and performance. A prototype slow-control board incorporating a commercial slow-control sensor was constructed. This prototype was used to implement basic logic for temperature data acquisition and tested under neutron irradiation. The slow-control board operated successfully in a high-radiation environment up to 1011 n/cm2, demonstrating the potential of the AS-FPGA and the slow-control board for future particle physics experiments.

关键词： Radiation effects Neutrons field programmable gate arrays Leakage currents Random access memory Gamma-rays Switches High energy physics Current measurement Particle beams Atom switch (AS) field-programmable gate array (FPGA) radiation tolerance slow control

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Experimental Investigation of Side-Channel Attacks on Neuromorphic Spiking Neural Networks

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第2期16卷 231-234页

作者： Goswami, Bhanprakash Das, Tamoghno Suri, Manan Indian Inst Technol Delhi Dept Elect Engn New Delhi 110016 India

This study investigates the reliability of commonly utilized digital spiking neurons and the potential side-channel vulnerabilities in neuromorphic systems that employ them. Through our experiments, we have successfully decoded the parametric information of Izhikevich and leaky integrate-and-fire (LIF) neuron-based spiking neural networks (SNNs) using differential power analysis. Furthermore, we have demonstrated the practical application of extracted information from the 92% accurate pretrained standard spiking convolution neural network classifier on the FashionMNIST dataset. These findings highlight the potential dangers of utilizing internal information for side-channel and denial-of-service attacks, even when using the usual input as the attack vector.

关键词： Neurons Power distribution field programmable gate arrays Firing Threshold voltage Power demand Convolution Neuromorphic hardware side-channel attack

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Highly secure OFDM scheme based on multi-level masking and performance-enhanced key accompanying transmission

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OPTICS LETTERS 2024年第24期49卷 6936-6939页

作者： Yin, Mengtong Liu, Bo Ren, Jianxin Mao, Yaya Chen, Shuaidong Wu, Xiangyu Li, Ying Zhao, Lilong Zhu, Dongxu Nanjing Univ Informat Sci & Technol Inst Opt & Elect Nanjing 210044 Peoples R China Nanjing Univ Informat Sci & Technol Jiangsu Key Lab Optoelect Detect Atmosphere & Ocea Nanjing 210044 Peoples R China Nanjing Univ Informat Sci & Technol Jiangsu Int Joint Lab Meteorol Photon & Optoelect Nanjing 210044 Peoples R China Beijing Univ Posts & Telecommun Beijing 100876 Peoples R China Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Nanjing Univ Posts & Telecommun Nanjing 210003 Peoples R China

In this Letter, we propose a highly secure OFDM scheme based on multi-level masking and performance-enhanced key-accompanying transmission. Our scheme exploits a fourdimensional hyperchaotic model and uses subcarriers and symbols to scramble the signal, thereby achieving chaotic encryption and enhancing system security. The dual-mode index technique is employed to conceal the key within the encrypted signal, enabling cooperative transmission of both the key and the signal. We conducted experiments that successfully transmitted a 28 Gb/s dual-mode QPSK (DMQPSK) signal and a 42 Gb/s dual-mode 8QAM (DM-8QAM) signal over a 2-km stretch of 7-core fiber. The results demonstrated that our proposed key-accompanying transmission scheme did not compromise the system's transmission performance. Moreover, the key space of this scheme is as large as 10135, effectively ensuring system security. Under the received optical power corresponding to the bit error rate of 3.8 x 10-3, the minimum number of key repetitions in DM-8QAM that makes the key bit error rate zero is less than 9 times. This demonstrates that our proposed scheme effectively enhances the transmission performance of the key, achieving high-quality joint transmission of both the key and the signal. (c) 2024 Optica Publishing Group. All rights, including for text and data mining (TDM), Artificial Intelligence (AI) training, and similar technologies, are reserved.

关键词： Bit error rate field programmable gate arrays Light beams Optical signals Quadrature phase shift keying Signal transmission

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Real-time fully digital control scheme for pulse coherent beam combining

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OPTICS LETTERS 2024年第21期49卷 6333-6336页

作者： Wu, Yong Wang, Xinyu Pu, Guoqing Zhang, Xuguang Liu, Chenxu Dong, Kegong Hu, Weisheng Yi, Lilin Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn State Key Lab Adv Commun Syst & Networks Shanghai 200240 Peoples R China Chinese Acad Engn & Phys Laser Fus Res Ctr Mianyang 621900 Peoples R China

A fully digital control scheme for non-polarizationcombining (CBC) is proposed, where digital locking of optical coherence by single-detector electronic-frequency tagging (LOCSET) for active phase control and stochastic parallel gradient descent (SPGD) for active polarization control is proposed. The fully digital control scheme is integrated on a real-time field-programmable gate array (FPGA) empowered hardware platform and then experimentally validated in a four-channel all-fiber non-fully polarization-maintaining nanosecond pulse CBC system. Consequently, the system can be fully locked in 9.5 ms, and the polarization extinction ratio (PER) of the combined beam is 21.5 dB with a CBC efficiency of 95.3%. are reserved.

关键词： Extinction ratios field programmable gate arrays Nanosecond pulses Nonlinear frequency conversion Phase noise Polarization control

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An FPGA Integrated 2D Graphic Processor for Enhanced Digital Design and Computer Architecture Education

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IEEE REVISTA IBEROAMERICANA DE TECNOLOGIAS DEL APRENDIZAJE-IEEE RITA 2024年 19卷 176-185页

作者： Alves, Gabriel Sa B. Carlos Bittencourt, Joao N. Dias, Anfranserai State Univ Feira de Santana Dept Technol BR-44036900 Feira De Santana Brazil Univ Fed Reconcavo Bahia Ctr Exact & Technol Sci BR-44380000 Cruz Das Almas Brazil

In the rapidly evolving domain of technology education, the integration of digital systems and computer architecture into a unified academic curriculum has become increasingly important. This integration reflects the dynamic nature of the technological landscape and aligns with the growing demands and expectations of students pursuing competencies in both disciplines. Within this context, there is an urgent need for innovative and disruptive pedagogical tools that are in line with current educational trends and effectively address the different learning styles of students. Consequently, the adoption of field programmable gate Array (FPGA) co-design approaches, which integrate hardware and software aspects of systems, represents a significant step forward in meeting the contemporary demands of computer architecture education, offering a practical, engaging and scalable solution. This paper introduces CoLenda, a novel learning tool, through the implementation of an educational FPGA platform based on a 2D graphics processor. The aim of CoLenda is to provide a comprehensive understanding of its architecture, enabling students to experience practical, hands-on learning through the development of graphics-based games. The introduction of this processor enhances the learning process by allowing students to engage in digital design and computer architecture curricula while fostering creativity and practical problem-solving skills. Additionally, making the project open-source for community contributions could significantly expand the potential and scope of this educational tool.

关键词： Computer architecture Games field programmable gate arrays Hardware Software Graphics processing units Hardware design languages Game-based educational tool hands-on learning teaching technology

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Dynamic Reconfiguration for Multi-Magnet Tracking in Myokinetic Prosthetic Interfaces

IEEE TRANSACTIONS ON MEDICAL ROBOTICS AND BIONICS

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IEEE TRANSACTIONS ON MEDICAL ROBOTICS AND BIONICS 2024年第4期6卷 1678-1687页

作者： Mendez, Sergio A. Pertuz Mendes, Davi de Alencar Gherardini, Marta Munoz, Daniel M. Ayala, Helon Vicente Hultmann Cipriani, Christian Tech Univ Dresden Inst Comp Engn D-01062 Dresden Germany Univ Brasilia Dept Mech Engn BR-70910900 Brasilia Brazil Scuola Super Sant Anna BioRobot Inst I-56025 Pontedera Italy Univ Brasilia Dept Mech Engn BR-70910900 Brasilia Brazil Univ Brasilia Elect Engn Undergrad Program BR-70910900 Brasilia Brazil Pontificia Univ Catolica Parana Dept Mech Engn BR-38097 Rio De Janeiro Brazil Pontificia Univ Catolica Parana BR-80215901 Curitiba Brazil

Recently myokinetic interfaces have been proposed to exploit magnet tracking for controlling bionic prostheses. This interface derives information about muscle contractions from permanent magnets implanted into the amputee's forearm muscles. Machine learning models have been mapped on field programmable gate arrays (FPGAs) to track a single magnet, achieving good precision and computational efficiency, but consuming a large area and hardware resources. To track several magnets, here we propose a novel solution based on dynamic partial reconfiguration, switching three prediction models: a linear regressor, a radial basis function neural network, and a multi-layer perceptron neural network. A system with five magnets and 128 magnetic sensor inputs was used and experimental data were collected to train a system with five hardware predictors. To reduce the complexity of the models, we applied principal component analysis, ranking by correlation the number of inputs of each model. This run-time reconfigurable solution allows the circuits to be reconfigured in order to select the most reliable predictor model for each magnet while the rest of the circuit continues to operate extracting the most significant information from the captured signals. Thus, the proposed solution remarkably reduces the hardware occupation and improves the computational efficiency compared to previous solutions.

关键词： Computational modeling Magnetostatics Location awareness Magnetic sensors Hardware field programmable gate arrays Prosthetics Bionic prostheses myokinetic interface machine learning dynamic partial reconfiguration FPGA

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Energy-Efficient and Secure Edge AI

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IEEE NANOTECHNOLOGY MAGAZINE 2025年第2期19卷 5-6页

作者： Yeo, Kiat Seng

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An Optimized Structure for Data Alignment Logic in Parallel CRC Computing Circuits

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IEEE EMBEDDED SYSTEMS LETTERS 2025年第2期17卷 91-94页

作者： Nie, Yuchen Zhong, Sheng Kuang, Nailiang Ji, Yuting Luo, Hangzai Lishan Microelect Co R&D Innovat Ctr Xian 710065 Peoples R China Northwest Univ Sch Informat Sci & Technol Xian 710127 Peoples R China

In bit-level parallel cyclic redundancy check (CRC) computing circuits, it is possible that the input data length may not be evenly divisible by the parallel bit width. Consequently, the incorporation of alignment logic into the circuit is necessary to discard the invalid data. A comprehensive analysis of 256-bits parallel circuits reveals that the data alignment structure introduces an additional delay of 46% to 53.8%. We proposed a prealignment structure as a means of optimizing the data alignment logic. This structure separates the data alignment logic from the loopback structure generated by the parallel computing logic, allowing for pipelining between the data alignment logic and the parallel computing logic. On-board tests on field-programmable gate arrays (FPGAs) show that circuits with a prealignment structure have an increase in maximum clock frequency of about 95% to 175% and a reduction in average energy consumption for computation of about 40.6% to 55% compared to circuits using a shift-alignment structure.

关键词： Circuits Logic Parallel processing field programmable gate arrays Phase change materials Polynomials Registers Delays Pipelines Periodic structures Cyclic redundancy check (CRC) field-programmable gate array (FPGA) hardware acceleration parallel computation

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Optimized Quantum Random Number Generator for Single Photon LiDAR Interference Suppression

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IEEE PHOTONICS TECHNOLOGY LETTERS 2025年第9期37卷 512-515页

作者： Wang, Yicheng Yang, Xing Pan, Hao Guo, Yunhui Zuo, Lei Chen, Yuwei Natl Univ Def Technol State Key Lab Pulsed Power Laser Technol Hefei 230037 Peoples R China Adv Laser Technol Lab Anhui Prov Hefei 230037 Anhui Peoples R China

Single photon light detection and ranging (LiDAR) sensors have been facing serious issues of light interference and optical attacks. Random modulation of transmitted laser can effectively suppress interference and counter attacks. Quantum Random Number Generator (QRNG) based on single photon detection of LiDAR has become an important solution for generating true random numbers. The performance of traditional QRNG based on the parity of counting values of photon events (CntOE-QRNG) is poor under low photon event rate. This letter proposes a novel QRNG method based on parity discrimination of photon event interval (IntOE-QRNG). It is proved that the IntOE-QRNG has more advantages under the condition of low photon event rate. Based on the analysis of the advantages and disadvantages of these two methods, this letter finally proposes an optimized QRNG that combines these two methods to adapt to different photon event rate conditions.

关键词： Photonics Laser radar Single-photon avalanche diodes Detectors Binary sequences Histograms Generators field programmable gate arrays Entropy Training Quantum random number generator LiDAR SPAD anti-interference

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Portable and Cost-Effective Handheld Ultrasound System Utilizing FPGA-Based Synthetic Aperture Imaging

IEEE OPEN JOURNAL OF NANOTECHNOLOGY

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IEEE OPEN JOURNAL OF NANOTECHNOLOGY 2024年 5卷 107-115页

作者： Wang, Wenping Feng, Ziliang Sichuan Univ Natl Key Lab Fundamental Sci Synthet Vis Chengdu 610065 Peoples R China

The handheld ultrasound has been widely applied in various clinical applications due to its high portability and cost-effectiveness advantages. The smaller hardware architecture can expand its range of application scenarios. However, miniaturized ultrasound devices face the challenges in terms of image quality, frame rate, and power consumption. The achievement of high-quality and high-frame-rate imaging depends on numerous channels and higher pulse repetition frequency (PRF) at the cost of power consumption. The proposed work aims to design a field-programmable gate array (FPGA)-based prototype with synthetic aperture method for portable and cost-effective handheld ultrasound system. The prototype supports 8 transmit and receive channels and forms up to 8 synthetic apertures. In addition, to optimize the FPGA resources, the auto delay calculation and segmented apodizations are employed for 4 parallel beamforming lines. To evaluate the performance of our proposed prototype, scan sequences of B-mode, C-mode, and D-mode are implemented for image construction. The results show that the proposed prototype can provide a lateral resolution of 0.30 mm, a contrast-to-noise ratio (CNR) of 7.58 dB, and a frame rate of 22 frames per second (FPS) in dual-mode imaging. Moreover, it is remarkable that the memory and logic resources in the FPGA (EP4CE55) account for 73.7% and 66.2%, respectively, which makes the FPGA's power consumption only about 530 mW. The proposed prototype is suitable for handheld and other miniaturized ultrasound imaging systems.

关键词： Apertures Ultrasonic imaging field programmable gate arrays Delays Array signal processing Power demand Imaging Random access memory Image quality Nanotechnology Handheld ultrasound field-programmable gate array (FPGA) synthetic aperture parallel beamforming power consumption

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