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Simplified Oblique Decision Tree Accelerator

IEEE EMBEDDED SYSTEMS LETTERS 2025年第2期17卷 79-82页

作者： Choudhury, Rituparna Rafi Ahamed, Shaik Guha, Prithwijit SRM Univ AP Dept Elect & Commun Engn Amravati 522502 Andhra Pradesh India Indian Inst Technol Dept Elect & Elect Engn Gauhati 781039 India

In recent years, hardware platforms like field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs) are highly preferred for implementing machine learning algorithms in low-power or high-speed applications. This letter proposes a simplified oblique node decision tree algorithm. The classification is implemented on FPGA and ASIC for activity recognition and Parkinson's tremor detection. A mode number is used to choose the application mode. To provide better classification performance, efficient multiplier-less architectures have been used for power efficiency. This design operates at a maximum frequency of 167 MHz and has the lowest latency as compared to the existing hardware. It is also found to have very low resource consumption as compared to other existing high-speed architectures.

关键词： Vectors Hardware field programmable gate arrays Training Registers Computer architecture Classification algorithms arrays Switches Machine learning algorithms Application specific integrated circuit (ASIC) classification decision tree (DT) field programmable gate array (FPGA) machine learning (ML)

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FPGA-Based Real-Time Road Object Detection System Using mmWave Radar

IEEE SENSORS LETTERS

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IEEE SENSORS LETTERS 2025年第4期9卷

作者： Mohan, Anand Meena, Hemant Kumar Wajid, Mohd Srivastava, Abhishek Malaviya Natl Inst Technol Dept Elect Engn Jaipur 302017 India Aligarh Muslim Univ Dept Elect Engn Aligarh 202002 India Int Inst Informat Technol Hyderabad Ctr VLSI Design Embedded Syst Technol Hyderabad 500032 India

This letter presents the development of a real-time object detection system using frequency modulated continuous wave millimeter-wave (mmWave) radar signals and the python productivity for zynq ultrascale + mpsocs (PYNQ-ZU) field-programmable gate array (FPGA) board, which is widely used in advanced driving assistance system and robotic applications. A hardware FPGA platform serves as a valid embedded architecture for the purpose of validating object detection and recognition applications. We used our experiment's point cloud images to apply different machine learning models to detect these objects. Using a top-view (TV) filter to convert 3-D point cloud images into 2-D representations made object detection more accurate. Following the use of filtration techniques, we extracted features from the filtered 2-D image using the visual geometry group (VGG) 16 model. We then assessed four machine learning models for object detection and found that the support vector machine (SVM) model and logistic regression (LR) had better results, obtaining an accuracy of 97%. Our proposed work uses mmWave radar, TV filter, VGG 16 Model, and LR to highly increase object detection accuracy over existing methods.

关键词： Radar Object detection Radar detection Point cloud compression Millimeter wave radar field programmable gate arrays Accuracy Radar imaging Millimeter wave communication Feature extraction Sensor applications field-programmable gate array (FPGA) board mmWave radar machine learning object detection PYNQ-ZU point cloud images support vector machine (SVM) VGG 16 model

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FOG: Fast Octree Generator for LiDAR Point Clouds

IEEE SENSORS LETTERS

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IEEE SENSORS LETTERS 2025年第1期9卷

作者： Roriz, Ricardo Costa, Diogo Ekpanyapong, Mongkol Gomes, Tiago Univ Minho ALGORITMI Res Ctr LASI P-4800058 Guimaraes Portugal Asian Inst Technol Sch Engn & Technol Pathum Thani 12120 Thailand

As the need for realistic and immersive 3-D representations of the environment continues to increase across various industries, finding efficient ways to represent data has become paramount. A well-known approach to partitioning 3-D space into a structured data format is the use of octrees, primarily due to their efficiency in handling both sparse and dense 3-D data. This method is particularly useful in applications involving automotive light detection and ranging (LiDAR) sensors, which are widely used in autonomous driving systems for their ability to capture detailed spatial information in real-time. This letter introduces the fast octree generator (FOG) algorithm, a novel approach for generating octrees from 3-D LiDAR point clouds that leverages hardware acceleration. FOG achieves a performance improvement of up to 88.8% compared to PCL's octree implementation, enabling real-time octree generation for high-end sensors on embedded platforms.

关键词： Octrees Three-dimensional displays Point cloud compression Sensors Image reconstruction Laser radar Codes Real-time systems PSNR field programmable gate arrays Sensor applications 3-D light detection and ranging (LiDAR) field-programmable gate array (FPGA) octree

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Implementations for Scattering at 1.8 Volt Between Battery-Less Transponder and Mobile Telephones

IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION

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IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION 2024年 8卷 671-676页

作者： Willi, Roman Kamm, Lars Zbinden, Paul Schutz, Matthias OST Eastern Switzerland Univ Appl Sci Inst Microelect & Embedded Syst CH-9000 St Gallen Switzerland Idp Invent Ag CH-4600 Olten Switzerland

This work concerns advanced implementations of a battery-less transponder operated by intentionally generated wireless signals in the 2.4 GHz ISM band. The wireless signals consist of a power supplying data stream and of a quasi-continuous Bluetooth RF (radio frequency) signal, which enables the transponder to back-scatter the RF signal to a receiver. Our setup uses two regular, unmodified mobile telephones, one for transmitting the signals, the other for receiving the scattered signals. The transponder modulates the quasi-continuous RF signal according to a subcarrier and a predetermined 1 Mbit/s bit-stream. The present extended study further compares advanced implementation techniques: Micro Controller Unit (MCU), FPGA (field programmable gate Array), CPLD (Complex programmable Logic Device) and ASIC (Application Specific Integrated Circuit) and implements a CPLD test version. Experimental results suggest that our CPLD is more suitable than MCU or FPGA implementations. The paper further demonstrates the transition from a fully synchronous to a low-power asynchronous CPLD implementation. The measured power consumption for generating the bit-stream is 87 mu W, which results in a 6-fold reduction compared to our previous work. Accordingly, the asynchronous CPLD implementation increases total efficiency by 40% and it is expected that this will significantly extend the wireless operational range of the battery-less transponder. Thus, the CPLD technology enables fast, flexible, and cost-effective implementation, particularly in the field of research and development.

关键词： Transponders Clocks Telephone sets field programmable gate arrays Radiofrequency identification Radio frequency Power demand Back-scattering battery-less harvesting mobile telephone subcarrier MCU DMA FPGA CPLD ASIC

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An Energy-Efficient FPGA Accelerator for Swin Transformer

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第6期33卷 1774-1778页

作者： Wang, Yuefei Mao, Wendong Shi, Huihong Sha, Jin Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210093 Peoples R China Sun Yat Sen Univ Sch Integrated Circuits Guangzhou 510275 Peoples R China

Recently, transformers have shown strong performance in tasks such as computer vision and natural language processing. Notably, Swin Transformer has gained significant attention for its low computational complexity and impressive performance in computer vision tasks, due to its window attention mechanism and hierarchical architecture. However, these features also make hardware deployment more complicated. In this brief, we present an energy-efficient field-programmable gate array (FPGA) accelerator for Swin Transformer to support the hierarchical architecture and execute the window attention. First, we introduce a systolic array with alterable datapath (SAAD) to conduct the window attention. Second, we split the patch merging operation and design a data rearrangement module, which reduces the computing latency induced by the data rearrangement in Swin Transformer. Third, we present a parallelized dual-array dataflow to support different computing operations in Swin Transformer. We implement the accelerator on the Xilinx XCZU19EG platform. The proposed architecture achieves a throughput per digital signal processing (DSP) of 0.630 giga operations per second (GOPS)/DSP, which is 1.94x higher than existing works.

关键词： Transformers Computer architecture field programmable gate arrays Random access memory Merging Systolic arrays Attention mechanisms Windows Optimization Convolution Computer vision deep learning field-programmable gate array (FPGA) hardware accelerator Swin Transformer

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Low Area and Low Power FPGA Implementation of a DBSCAN-Based RF Modulation Classifier

IEEE OPEN JOURNAL OF THE COMPUTER SOCIETY

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IEEE OPEN JOURNAL OF THE COMPUTER SOCIETY 2024年第1期5卷 50-61页

作者： Gavin, Bill Deng, Tiantai Ball, Edward Univ Sheffield Dept Elect & Elect Engn Sheffield S1 3JD England

This paper presents a new low-area and low-power field programmable gate Array (FPGA) implementation of a Radio Frequency (RF) modulation classifier based on the Density-Based Spatial Clustering of Applications with Noise (DBSCAN) algorithm, known as DBCLASS. The proposed architecture demonstrates a novel approach for the efficient hardware realisation of the DBSCAN algorithm by utilising parallelism, a bespoke sorting algorithm, and eliminating memory access. The design achieves 100% classification accuracy with lab-captured RF data above 8 dB signal-to-noise ratio(SNR) whilst exhibiting an improvement of latency in comparison to the next quickest design by a factor of 7.5, a reduction in terms of total FPGA resources used in comparison to the next smallest complete system by a factor of 3.65, and a reduction in power consumption over the next most efficient by a factor of 4.75. The proposed design is well suited for resource-constrained applications, such as mobile cognitive radios and spectrum monitoring systems.

关键词： Modulation field programmable gate arrays Signal to noise ratio Delays Classification algorithms Hardware Convolutional neural networks RF classifier cognitive radio DBSCAN FPGA automatic modulation classification AMC beyond smart radio

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One-Dimensional Binary Convolutional Neural Network Accelerator Design for Bearing Fault Diagnosis

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IEEE SENSORS JOURNAL 2024年第3期24卷 3649-3658页

作者： Syu, Zih-Syuan Lee, Ching-Hung Natl Yang Ming Chiao Tung Univ Inst Elect & Control Engn Hsinchu 30010 Taiwan

In the field of equipment anomaly detection, anomalies in equipment or tooling machines can be detected earlier by analyzing vibration signals. However, hardware platforms, such as graphics processing units (GPUs), tensor processing units (TPUs), and workstations, are commonly used for the applications of artificial intelligence (AI), which limits the practical applications due to high-power consumption and high cost;the corresponding large amount of computation reduces the inference speed in real-time industrial environments. In this study, we propose a binary neural network (BNN) accelerator and implement it in a field-programmable gate array (FPGA) for bearing fault diagnosis. By using a 1-D convolutional neural network (CNN), we extract the features of vibration signals and classify the classes of bearing faults with high accuracy. The model weights are trained with only one bit by using a knowledge distillation and binarization algorithm to reduce the storage space. We adopt the FPGA, a reprogrammable, low-power, low-cost platform for CNN implementation. The original convolutional operation is replaced with a more efficient algorithm and a specialized binary model computation engine is designed to accelerate model inference and reduce ON-chip resource utilization. Experimental results and comparisons are introduced to show the optimized binary model required only 0.42 ms to infer on the hardware platform, which is 150 times faster than a 32-bit floating-point neural network of the same architecture and still maintained a higher testing accuracy of 98.5%.

关键词： Feature extraction Computational modeling Deep learning Hardware Neural networks field programmable gate arrays Convolutional neural networks Bearing fault diagnosis binary neural networks (BNNs) compression field-programmable gate array (FPGA) model acceleration

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A Reduced-Order Digital Twin FPGA-Based Implementation With Self-Awareness Capabilities for Power Electronics Applications

IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION

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IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION 2024年 8卷 493-505页

作者： Nwoke, Justus Milanesi, Marco Viola, Jairo Chen, Yangquan Visioli, Antonio Univ Californiaat Merced Mechatron Embedded Syst & Automat Lab Merced CA 94343 USA Univ Brescia Dept Mech land Ind Engn Brescia Italy

Developing accurate mathematical or data-driven models for effective controller design under dynamic variable conditions becomes increasingly challenging. For this reason, the concept of a digital twin (DT) as a virtual representation of a physical asset has been introduced as a tool for process modelling, design, and control implementation while providing additional knowledge of the system that can be used to enable awareness capabilities on the asset. However, digital twin models used to be complex, requiring expensive computational times depending on the application to provide the most accurate system representation, limiting its application in edge, embedded, and register transfer level computing domains. Therefore, using reduced-order digital twin models is an alternative to get DT closer to the physical asset. Considering these challenges, we propose a reduced-order FPGA-based digital twin implementation that directly sources data from the real system, operates in parallel with the virtual system, and enables awareness mechanisms to improve the system's operation. This setup removes large data transfers, cloud interfaces and expensive computational times deriving into a faster and more efficient DT. To illustrate the capabilities of this embedded digital twin, we present a case study focused on monitoring a power converter. The study involves establishing and enforcing a safe operating area (SOA) for the power converter, implementing error awareness mechanisms, and enabling machine learning models to predict converter load conditions and fault events detection. Thus, we aim to showcase the effectiveness of our proposed FPGA-based digital twin approach in addressing real-time control challenges towards smart control engineering.

关键词： Digital twins Buck converters field programmable gate arrays Read only memory Cloud computing Real-time systems Computational modeling Digital twin flyback converter smart control engineering FPGA embedded digital twin Industry 4.0

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Simple and high-resolution method for displacement sensing using self-mixing interferometry

OPTICS CONTINUUM

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OPTICS CONTINUUM 2024年第11期3卷 2116-2126页

作者： Amin, Saqib Orakzai, Muhammad Sadiq Khan, Zohaib Ahmed Riphah Int Univ Fac Engn & Appl Sci Dept Elect & Comp Engn Islamabad Pakistan

Self-mixing interferometry (SMI) is widely used for vibration, velocity, and displacement measurement applications. Many complex and computationally intensive phase unwrapping algorithms have already been proposed to obtain high-resolution measurements, but there remains a requirement for a high-resolution yet simple method for displacement measurement. In this work, a high-resolution yet simple improved unwrapping method (IUM) is proposed, which addresses the limitations of the previously proposed simple but low-resolution method, consecutive sample-based unwrapping (CSU). IUM shows a remarkable improvement of 49% over CSU. IUM was assessed for a broad range of SMI signals, and results revealed that IUM is capable of processing SMI signals from all three main feedback regimes with an average RMS and peak error of 37.7 nm and 113.3 nm, respectively. Such a high-resolution method with a straightforward processing methodology is a vital step towards real-time independent displacement sensors capable of performing high-resolution measurements. (c) 2024 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement

关键词： field programmable gate arrays Fourier transforms Michelson interferometers Optical components Phase retrieval Phase unwrapping

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High-Performance of Eigenvalue Decomposition on FPGA for the DOA Estimation

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IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY 2023年第5期72卷 5782-5797页

作者： Zhang, Xiao-Wei Yan, Di Zuo, Lei Li, Ming Guo, Jian-Xin Xidian Univ Natl Lab Radar Signal Proc Xian 710126 Peoples R China Xijing Univ Sch Informat Engn Xian 710123 Peoples R China Changan Univ Sch Informat Engn Xian 710064 Peoples R China

For the direction of arrival (DOA) in array signal processing, eigenvalue decomposition (EVD) is one key issue in hardware implementation of the multiple signal classification (MUSIC) algorithm. Therefore, we introduce the look-ahead simplified one-sided Jacobi's method to efficiently decompose those symmetric matrices in this article and prove that the new method has the best orthogonality of eigenvector and locates eigenvectors closest to the true solution in theory. Both the numerical performance and real-time are important in engineering, so we present the novel flexible hardware architecture in single floating point arithmetic for EVD on field-programmable gate arrays (FPGAs). Finally, the simulated and raw data are used to investigate the performance of some different approaches in the context of both the EVD and MUSIC algorithm. The experimental results show that our proposed method has the best performance.

关键词： Matrix decomposition Jacobian matrices field programmable gate arrays Eigenvalues and eigenfunctions Hardware Signal processing algorithms Multiple signal classification Eigenvalue decomposition (EVD) field-programmable gate array (FPGA) MUSIC Jacobi's method matrix inversion partial sorter QR algorithm

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