检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

37,600 篇 会议
3,973 篇 期刊文献
30 册 图书
20 篇 学位论文
19 篇 科技报告

馆藏范围

41,639 篇 电子文献
5 种 纸本馆藏

日期分布

学科分类号

16,100 篇 工学
- 9,293 篇 电气工程
- 7,912 篇 计算机科学与技术...
- 2,243 篇 软件工程
- 2,209 篇 电子科学与技术（可...
- 2,165 篇 信息与通信工程
- 2,041 篇 控制科学与工程
- 1,136 篇 仪器科学与技术
- 776 篇 机械工程
- 415 篇 核科学与技术
- 336 篇 航空宇航科学与技...
- 335 篇 生物医学工程（可授...
- 292 篇 光学工程
- 271 篇 材料科学与工程（可...
- 238 篇 测绘科学与技术
- 144 篇 石油与天然气工程
- 94 篇 动力工程及工程热...
- 91 篇 网络空间安全
- 90 篇 交通运输工程
2,403 篇 理学
- 1,341 篇 物理学
- 691 篇 数学
- 392 篇 系统科学
- 75 篇 化学
- 57 篇 统计学（可授理学、...
- 53 篇 生物学
819 篇 管理学
- 790 篇 管理科学与工程(可...
- 103 篇 工商管理
774 篇 医学
- 518 篇 临床医学
- 163 篇 基础医学(可授医学...
- 89 篇 特种医学
59 篇 文学
- 59 篇 新闻传播学
49 篇 农学
44 篇 军事学
38 篇 经济学
35 篇 教育学
24 篇 法学
22 篇 艺术学

主题

41,642 篇 field programmab...
11,578 篇 hardware
7,428 篇 clocks
5,203 篇 computer archite...
5,136 篇 signal processin...
4,255 篇 ofdm
4,244 篇 estimation
4,148 篇 modulation
3,941 篇 filtration
2,185 篇 table lookup
2,075 篇 random access me...
2,008 篇 algorithm design...
1,992 篇 digital signal p...
1,932 篇 throughput
1,768 篇 routing
1,548 篇 switches
1,492 篇 software
1,419 篇 registers
1,413 篇 costs
1,384 篇 delay

机构

75 篇 department of el...
73 篇 school of comput...
58 篇 department of co...
52 篇 faculty of infor...
44 篇 department of el...
44 篇 department of el...
39 篇 imperial college...
38 篇 department of el...
29 篇 univ chinese aca...
29 篇 xilinx inc. san ...
28 篇 systems and info...
27 篇 natl univ singap...
25 篇 nanyang technol ...
25 篇 school of inform...
23 篇 department of el...
23 篇 department of el...
21 篇 dipartimento di ...
21 篇 department of el...
21 篇 ecole polytech f...
21 篇 georgia inst tec...

作者

155 篇 wayne luk
50 篇 george a. consta...
49 篇 mohamed abid
47 篇 yu wang
44 篇 jason cong
38 篇 paul chow
37 篇 tughrul arslan
35 篇 iouliia skliarov...
34 篇 chao wang
31 篇 f. lombardi
31 篇 fahmy suhaib a.
30 篇 miriam leeser
30 篇 motoki amagasaki
29 篇 j. becker
28 篇 jian wang
27 篇 kenneth b. kent
27 篇 jinmei lai
27 篇 luca sterpone
26 篇 david andrews
26 篇 wei li

语言

41,036 篇 英文
397 篇 中文
197 篇 其他
3 篇 西班牙文
3 篇 日文
1 篇 德文
1 篇 俄文
1 篇 土耳其文

检索条件"主题词=Field Programmable Gate Arrays"

共 41642 条记录，以下是561-570 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Power and Area-Efficient ECC Processor with Sequential Recursive Polynomial Multiplier Implementation

Power and Area-Efficient ECC Processor with Sequential Recur...

引用

IEEE International Symposium on Quality Electronic Design

作者： Pruthvi Parate Alwin Shaju Vasanthi D R Madhav Rao IIIT Bangalore

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Elliptic curve cryptography (ECC) is a unique and efficient public-key cryptography method where polynomial multiplication is the primary operation. Thus, ECC efficiency depends largely on effective polynomial multiplier implementation. This work presents a hardware-efficient ECC processor with a clocked data-path using an M-term Hybrid Karatsuba multiplier for GF(2 233 ) Montgomery multiplication. The proposed design was implemented on a Kintex UltraScale FPGA and synthesized with a 45 nm library using Cadence Genus, with the sequential multiplier data path integrated into the ECC processor. The M-Term Non-Homogeneous Overlap-Free Karat-sub a Multiplier (MNHOKA) and Composite M-Term Overlap-Free Karatsuba-like Multiplier (CMOKA) multipliers, integrated into ECC processors, achieved top hardware efficiency on FPGA and silicon, surpassing all other variants and SOTA multipliers. The clocked MNHOKA-adopted ECC processor achieved LUT savings of 56.11% and a Figure-of-Merit (FoM) improvement of 74.73% in FPGA over the best SOTA design. On silicon, the sequential design of Overlap-Free Karatsuba Multiplier (OKA) incorporated ECC processor exhibited maximum footprint savings of 45.70% and clocked MNHOKA incorporated ECC processor exhibited maximum power saving of 73.00% over the best SOTA design. The innovative and hardware-efficient ECC accelerator design files are made freely available for further usage to the designers and engineering community.

关键词： Performance evaluation Memory Elliptic curve cryptography Polynomials Silicon Libraries Table lookup Resource management Internet of Things field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

16 Bit Memory and Power Efficient Truncated Booth Multiplier For High Speed Applications/Operations

16 Bit Memory and Power Efficient Truncated Booth Multiplier...

引用

Mobile Computing and Sustainable Informatics (ICMCSI), International Conference on

作者： Yashu Swami T. Senthil Vadivel Department of ECE MRIIRS Faridabad Haryana India Civil Engineering Department MRIIRS Faridabad Haryana India

ISBN: (数字)9798331522667

ISBN: (纸本)9798331522674

We now know that multipliers are a necessary component of all basic circuits. These days, multipliers are the cornerstone of any ALU system. High Radix Booth encoding reduces unfinished product during multiplication, but multipliers also introduce delay and power due to hard multiples. The approximate radix-256 Booth encoding is recommended in order to prevent hard multiples. By shifting and complimenting, a partial encoding method is used to construct partial product pairings. Precise encoding values are determined by adding up matching partial products. For performance testing, a 16x16 bit multiplier with the recommended radix-256 Booth encoding was built. Implementation of a 16-bit Truncated Booth Multiplier on the Nexys 4 DDR FPGA board. and contrast with additional multipliers.

关键词： Memory management Circuits Encoding Delays Logic Informatics Mobile computing field programmable gate arrays Testing Arithmetic

来源：评论

学校读者我要写书评

暂无评论

Unified Architecture for High-Performance SDR Platforms

Unified Architecture for High-Performance SDR Platforms

引用

Digital Signal Processing and its Applications (DSPA), International Conference on

作者： Krutin Denis Ivan Melnik Ivan Varakin Artem Aksenov Institute of Information Technology and Electronics Vladimir State University Vladimir Russia

ISBN: (数字)9798331518752

ISBN: (纸本)9798331518769

The research presents a unified architecture for high-performance software-defined radio (SDR) platforms. The proposed architecture provides flexibility, reconfigurability, and modularity, making it ideal for adapting to the increasing demands of modern communication standards. Utilizing system-on-chip (SoC) and field-programmable gate arrays (FPGAs), this solution streamlines the development and prototyping of specialized radio devices. The results are substantiated by the implementation of next-generation modem prototypes and radio monitoring systems, demonstrating the significant potential of the proposed approach.

关键词： Computer architecture Digital signal processing Modems Mathematical models Libraries field programmable gate arrays Next generation networking Monitoring Software radio Communication standards

来源：评论

学校读者我要写书评

暂无评论

A Design of Fault-Tolerant System for Safety-Critical Systems

A Design of Fault-Tolerant System for Safety-Critical System...

引用

International Conference on Autonomous Robots and Agents, ICARA

作者： Kai Yoshizawa Nobuyuki Yamasaki Graduate School of Science and Technology Keio University Yokohama Japan

ISBN: (数字)9798331509231

ISBN: (纸本)9798331509248

In safety-critical systems where failures or faults can lead to accidents, especially in special and harsh environments like those encountered in spacecraft, it is well known that multiple levels of errors can significantly increase the likelihood of system failure. For instance, system-level errors may occur due to cable breaks caused by severe vibrations, while gate-level errors can arise from radiation effects on System-on-Chip (SoC) semiconductors. Furthermore, in such specialized environments, human repair is often not feasible, necessitating that the system continue to operate even when a fault occurs in a part of it. Therefore, this research discusses the design, implementation, and evaluation of a redundant system that combines multi-level redundancy mechanisms to tolerate multiple errors and maintain operation. The implementation was carried out on the Space I/O Core (SIOC), a System-on-Chip equipped with processors and I/O for distributed real-time systems. Additionally, bitstreams were created from the implemented logic, and the performance of the fault-tolerant system was evaluated using an actual FPGA.

关键词： Vibrations Space vehicles Redundancy Fault tolerant systems Termination of employment Switches Logic gates System-on-chip field programmable gate arrays Robots

来源：评论

学校读者我要写书评

暂无评论

An Efficient Reconfigurable Parameterized Convolutional Neural Network Accelerator on FPGA Platform

An Efficient Reconfigurable Parameterized Convolutional Neur...

引用

IEEE International Conference on Consumer Electronics (ICCE)

作者： Yeong-Kang Lai Chien-Hung Lin Department of the Electrical Engineering Master Program in Semiconductor and Green Technology National Chung Hsing University Taichung Taiwan R.O.C

ISBN: (数字)9798331521165

ISBN: (纸本)9798331521172

This paper presents an efficient reconfigurable parameterized convolutional neural network (CNN) accelerator designed for FPGA platforms. The core of the accelerator allows flexible adjustments of input channel parallelism (Pc) and convolution filter parallelism (Pn) to meet the needs of various CNN models, optimizing both resource utilization and computational efficiency. The architecture is applied specifically to infrared (IR) and visible light (VI) image fusion, enabling real-time processing on an FPGA with significantly reduced latency. Experimental results demonstrate that the accelerator reduces latency to 192 ms while maintaining high image quality, achieving efficient image fusion on the FPGA platform.

关键词： Image quality Convolution Computer architecture Parallel processing Real-time systems Convolutional neural networks Resource management Image fusion field programmable gate arrays Hardware acceleration

来源：评论

学校读者我要写书评

暂无评论

Multi-vendor encoder position sensing interface using programmable IP based solution

Multi-vendor encoder position sensing interface using progra...

引用

Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)

作者： Rajul Bhambay Dhaval Khandla Pratheesh Gangadhar Thomas Leyrer Achala Ram Manoj Koppolu Archit Dev Embedded Processors Texas Instruments Inc. Bengaluru India Embedded Processors Texas Instruments Inc. Munich Germany

ISBN: (数字)9798331516116

ISBN: (纸本)9798331516123

The aim of this work is to look at a software programmable solution for multi-vendor encoders protocol in which TI utilizes "Three Channel Peripheral Interface (3CPI)" or general purpose inputs (GPIs)/general purpose outputs (GPOs) in programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS) on Texas Instruments AM24x/AM26x micro-controllers (MCUs) and AM64x processors [10] –[12]. Existing solutions are FPGA based which come with a few challenges like high power consumption, high cost, and latency in operating control loop. This approach cuts down huge amount of cost by not implementing with FPGA, but using programmable IP and offloading MCUs or processors CPU load via PRU-ICSS. It also has the capability to optimize control loop, by moving the position data after validation and post processing to the tightly coupled memory of CPU running control loop. This makes TI’s solution cost effective and low latency in terms of running control loop, highly flexible and scalable in terms of implementing multiple vendor encoder interfaces.

关键词： Costs Program processors Protocols Industrial communication Process control Real-time systems Software System-on-chip Sensors field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

UNIT: A Highly Unified and Memory-Efficient FPGA-Based Accelerator for Torus FHE

UNIT: A Highly Unified and Memory-Efficient FPGA-Based Accel...

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Yuying Zhang Sharad Sinha Jiang Xu Wei Zhang Hong Kong University of Science and Technology Indian Institute of Technology (IIT) Goa

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Fully Homomorphic Encryption (FHE) has emerged as a promising solution for the secure computation on encrypted data without leaking user privacy. Among various FHE schemes, Torus FHE (TFHE) distinguishes itself by its ability to perform exact computations on non-linear functions within the encrypted domain, satisfying the crucial requirement for privacy-preserving AI applications. However, the high computational overhead and strong data dependency in TFHE's bootstrapping process present significant challenges to its practical adoption and efficient hardware implementation. Existing TFHE accelerators on various hardware platforms still face limitations in terms of performance, flexibility, and area efficiency. In this work, we propose UNIT, a novel and highly unified accelerator for programmable Bootstrapping (PBS) in TFHE, featuring carefully designed computation units. We introduce a unified architecture for negacyclic (inverse) number theoretic transform (I)NTT with fused twisting steps, which reduces computing resources by 33% and the memory utilization of pre-stored factors by nearly 66 %. Another key feature of UNIT is the innovative design of the monomial number theoretic transform unit, called OF-MNTT, which leverages on-the-fly twiddle factor generation to eliminate memory traffic and overhead. This memory-efficient and highly parallelizable approach for MNTT is proposed for the first time in TFHE acceleration. Furthermore, UNIT is highly reconfigurable and scalable, supporting various parameter sets and performance-resource requirements. Our proposed accelerator is evaluated on the Xilinx Alveo U250 FPGA platform. Experimental results demonstrate its superior performance compared to the state-of-the-art GPU and FPGA-based implementations with the improvement of 8.3x and 3.63x, respectively. In comparison with the most advanced FPGA implementation, UNIT achieves 30% enhanced area efficiency and 3.2 x reduced power with much better flexibility.

关键词： Graphics processing units Europe Transforms Hardware Computational efficiency Reconfigurable architectures Cryptography Homomorphic encryption field programmable gate arrays Faces

来源：评论

学校读者我要写书评

暂无评论

Optimized Spiking Neural Network for Chaotic System Prediction in FPGA

Optimized Spiking Neural Network for Chaotic System Predicti...

引用

Annual IEEE Systems Conference

作者： Zongyao Liu Lei Zhang Jin Zhang Qixuan Li Faculty of Engineering and Applied Science University of Regina Regina SK Canada AlphawaveSemi Ottawa ON Canada

ISBN: (数字)9798331508180

ISBN: (纸本)9798331508197

The Spike Neural Network (SNN) is a neural network that simulates the transmission of signals in brain cells. It utilizes the low-energy characteristics of neurons transmitting discrete signals, which have attracted widespread attention. This paper proposes an SNN with the threshold voltage drop to optimize the SNN. The model focuses on controlling the threshold voltage to reduce the effect of residual membrane voltage in the Mean Square Error (MSE). Reduced threshold voltage stimulates neurons to fire more spikes. The initialized membrane voltage SNN (I-SNN) is an optimized method that adding an extra membrane voltage in neurons. This paper optimizes the I-SNN to process negative data, introducing a variant called the signed initialized membrane voltage SNN (SI-SNN). The threshold voltage drop SNN and the SI-SNN in different numbers of neurons are compared for MSE in predicting the Lorenz System. The results indicate that the SNN with threshold voltage drop effectively reduces MSE, especially in the model with fewer neurons. After confirming the feasibility of this algorithm, this paper implements the threshold voltage drop method in FPGA. The MSEs of no optimized SNN and threshold voltage drop in FPGA are 0.0015 and 0.0013, respectively. The threshold voltage drop SNN demonstrates satisfactory performance.

关键词： Neurons Membrane potentials Spiking neural networks Mean square error methods Prediction algorithms Threshold voltage Hardware field programmable gate arrays Optimization Biological neural networks

来源：评论

学校读者我要写书评

暂无评论

Improved Subsynchronous Frequency Oscillations Detection in Wind Farms Using AI-based Fourier Transformation and Advanced Metrics

Improved Subsynchronous Frequency Oscillations Detection in ...

引用

IEEE Green Technologies Conference (IEEE-Green)

作者： Shyam Yathirajam Arash Peighambari Nikil Balaji Owen Man Hamed Nademi Sreedevi Gutta Justin Morris Ali Ahmadinia California State University San Marcos CA USA

ISBN: (数字)9798331520182

ISBN: (纸本)9798331520199

Low-Frequency oscillations in wind farms, caused by interactions between power converters and transmission lines, must be addressed quickly to prevent grid instability. While past studies using Convolutional Neural Networks (CNNs) have focused on high-magnitude oscillation detection, these methods often demand substantial data and computational resources, delaying detection and causing substantial damage to the grid. Moreover, the issue of low-frequency oscillations, which can lead to high-frequency resonance and potential power outages, remains underexplored. In this paper, we propose a dual detection system that swiftly identifies high-magnitude oscillations through time-domain analysis and detects low-frequency oscillations using Fast Fourier Transform-based frequency-domain analysis. We employ Hyperdimensional Computing (HDC) along with one-class SVM introducing True Positive Confidence (TPC) and False Positive Confidence (FPC) metrics to enhance reliability. Our findings show HDC surpasses One class SVM model, performing 6x faster on GPU and 16x on FPGA achieving at least 99% confidence in TPC and FPC for the oscillation types of interest in this work. This positions HDC as an optimal solution for real-time wind farm applications, offering significant advantages in speed and accuracy. Most importantly, the proposed solutions can detect oscillations within tens of microseconds, significantly ahead of the critical time window of 500/800 μ $s$ from the onset of the oscillation, ensuring timely and reliable fault detection.

关键词： Support vector machines Measurement Graphics processing units Wind farms Real-time systems Hardware Power system reliability Reliability Oscillators field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

FPGA-Based 3D EM/MPM Simulation Framework for Medical Image Segmentation Applications

FPGA-Based 3D EM/MPM Simulation Framework for Medical Image ...

引用

International Conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： Samit Karmakar Arindam Chakraborty Saptarshi Banerjee Ayantika Mondal Satavisha Dutta Sayak Nandi Electronics & Communication Engineering Dept. Institute of Engineering & Management University of Engineering & Management Kolkata India

ISBN: (数字)9798331520762

ISBN: (纸本)9798331520779

Medical image segmentation is a critical process in identifying disease-infected regions for diagnostic and treatment purposes. This paper introduces an FPGA-based framework for implementing the Expectation Maximization/Markov Random field (E M/MP M) algorithm in 3D medical image segmentation. FPGA platforms offer unparalleled advantages in terms of parallel processing, speed, and energy efficiency, making them a promising choice for real-time medical image analysis. This proposed framework enables rapid segmentation of 3D images, leveraging the FPGA's on-chip memory and custom logic for efficient pixel classification and data processing. The adaptive design also supports the integration of external RAM for larger datasets. Simulated using Verilog HDL and Quartus Prime, this work demonstrates accurate segmentation results through virtual testing, thus showcasing the system's robustness for medical applications.

关键词： Image segmentation Three-dimensional displays Random access memory Medical services Parallel processing Real-time systems Energy efficiency Hardware design languages Medical diagnostic imaging field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共500页 << < 53 54 55 56 57 58 59 60 61 62 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：