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An FPGA Integrated 2D Graphic Processor for Enhanced Digital Design and Computer Architecture Education

IEEE REVISTA IBEROAMERICANA DE TECNOLOGIAS DEL APRENDIZAJE-IEEE RITA 2024年 19卷 176-185页

作者： Alves, Gabriel Sa B. Carlos Bittencourt, Joao N. Dias, Anfranserai State Univ Feira de Santana Dept Technol BR-44036900 Feira De Santana Brazil Univ Fed Reconcavo Bahia Ctr Exact & Technol Sci BR-44380000 Cruz Das Almas Brazil

In the rapidly evolving domain of technology education, the integration of digital systems and computer architecture into a unified academic curriculum has become increasingly important. This integration reflects the dynamic nature of the technological landscape and aligns with the growing demands and expectations of students pursuing competencies in both disciplines. Within this context, there is an urgent need for innovative and disruptive pedagogical tools that are in line with current educational trends and effectively address the different learning styles of students. Consequently, the adoption of field programmable gate Array (FPGA) co-design approaches, which integrate hardware and software aspects of systems, represents a significant step forward in meeting the contemporary demands of computer architecture education, offering a practical, engaging and scalable solution. This paper introduces CoLenda, a novel learning tool, through the implementation of an educational FPGA platform based on a 2D graphics processor. The aim of CoLenda is to provide a comprehensive understanding of its architecture, enabling students to experience practical, hands-on learning through the development of graphics-based games. The introduction of this processor enhances the learning process by allowing students to engage in digital design and computer architecture curricula while fostering creativity and practical problem-solving skills. Additionally, making the project open-source for community contributions could significantly expand the potential and scope of this educational tool.

关键词： Computer architecture Games field programmable gate arrays Hardware Software Graphics processing units Hardware design languages Game-based educational tool hands-on learning teaching technology

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Dynamic Reconfiguration for Multi-Magnet Tracking in Myokinetic Prosthetic Interfaces

IEEE TRANSACTIONS ON MEDICAL ROBOTICS AND BIONICS

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IEEE TRANSACTIONS ON MEDICAL ROBOTICS AND BIONICS 2024年第4期6卷 1678-1687页

作者： Mendez, Sergio A. Pertuz Mendes, Davi de Alencar Gherardini, Marta Munoz, Daniel M. Ayala, Helon Vicente Hultmann Cipriani, Christian Tech Univ Dresden Inst Comp Engn D-01062 Dresden Germany Univ Brasilia Dept Mech Engn BR-70910900 Brasilia Brazil Scuola Super Sant Anna BioRobot Inst I-56025 Pontedera Italy Univ Brasilia Dept Mech Engn BR-70910900 Brasilia Brazil Univ Brasilia Elect Engn Undergrad Program BR-70910900 Brasilia Brazil Pontificia Univ Catolica Parana Dept Mech Engn BR-38097 Rio De Janeiro Brazil Pontificia Univ Catolica Parana BR-80215901 Curitiba Brazil

Recently myokinetic interfaces have been proposed to exploit magnet tracking for controlling bionic prostheses. This interface derives information about muscle contractions from permanent magnets implanted into the amputee's forearm muscles. Machine learning models have been mapped on field programmable gate arrays (FPGAs) to track a single magnet, achieving good precision and computational efficiency, but consuming a large area and hardware resources. To track several magnets, here we propose a novel solution based on dynamic partial reconfiguration, switching three prediction models: a linear regressor, a radial basis function neural network, and a multi-layer perceptron neural network. A system with five magnets and 128 magnetic sensor inputs was used and experimental data were collected to train a system with five hardware predictors. To reduce the complexity of the models, we applied principal component analysis, ranking by correlation the number of inputs of each model. This run-time reconfigurable solution allows the circuits to be reconfigured in order to select the most reliable predictor model for each magnet while the rest of the circuit continues to operate extracting the most significant information from the captured signals. Thus, the proposed solution remarkably reduces the hardware occupation and improves the computational efficiency compared to previous solutions.

关键词： Computational modeling Magnetostatics Location awareness Magnetic sensors Hardware field programmable gate arrays Prosthetics Bionic prostheses myokinetic interface machine learning dynamic partial reconfiguration FPGA

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Energy-Efficient and Secure Edge AI

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IEEE NANOTECHNOLOGY MAGAZINE 2025年第2期19卷 5-6页

作者： Yeo, Kiat Seng

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Portable and Cost-Effective Handheld Ultrasound System Utilizing FPGA-Based Synthetic Aperture Imaging

IEEE OPEN JOURNAL OF NANOTECHNOLOGY

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IEEE OPEN JOURNAL OF NANOTECHNOLOGY 2024年 5卷 107-115页

作者： Wang, Wenping Feng, Ziliang Sichuan Univ Natl Key Lab Fundamental Sci Synthet Vis Chengdu 610065 Peoples R China

The handheld ultrasound has been widely applied in various clinical applications due to its high portability and cost-effectiveness advantages. The smaller hardware architecture can expand its range of application scenarios. However, miniaturized ultrasound devices face the challenges in terms of image quality, frame rate, and power consumption. The achievement of high-quality and high-frame-rate imaging depends on numerous channels and higher pulse repetition frequency (PRF) at the cost of power consumption. The proposed work aims to design a field-programmable gate array (FPGA)-based prototype with synthetic aperture method for portable and cost-effective handheld ultrasound system. The prototype supports 8 transmit and receive channels and forms up to 8 synthetic apertures. In addition, to optimize the FPGA resources, the auto delay calculation and segmented apodizations are employed for 4 parallel beamforming lines. To evaluate the performance of our proposed prototype, scan sequences of B-mode, C-mode, and D-mode are implemented for image construction. The results show that the proposed prototype can provide a lateral resolution of 0.30 mm, a contrast-to-noise ratio (CNR) of 7.58 dB, and a frame rate of 22 frames per second (FPS) in dual-mode imaging. Moreover, it is remarkable that the memory and logic resources in the FPGA (EP4CE55) account for 73.7% and 66.2%, respectively, which makes the FPGA's power consumption only about 530 mW. The proposed prototype is suitable for handheld and other miniaturized ultrasound imaging systems.

关键词： Apertures Ultrasonic imaging field programmable gate arrays Delays Array signal processing Power demand Imaging Random access memory Image quality Nanotechnology Handheld ultrasound field-programmable gate array (FPGA) synthetic aperture parallel beamforming power consumption

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FPGA-Based Real-Time Road Object Detection System Using mmWave Radar

IEEE SENSORS LETTERS

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IEEE SENSORS LETTERS 2025年第4期9卷

作者： Mohan, Anand Meena, Hemant Kumar Wajid, Mohd Srivastava, Abhishek Malaviya Natl Inst Technol Dept Elect Engn Jaipur 302017 India Aligarh Muslim Univ Dept Elect Engn Aligarh 202002 India Int Inst Informat Technol Hyderabad Ctr VLSI Design Embedded Syst Technol Hyderabad 500032 India

This letter presents the development of a real-time object detection system using frequency modulated continuous wave millimeter-wave (mmWave) radar signals and the python productivity for zynq ultrascale + mpsocs (PYNQ-ZU) field-programmable gate array (FPGA) board, which is widely used in advanced driving assistance system and robotic applications. A hardware FPGA platform serves as a valid embedded architecture for the purpose of validating object detection and recognition applications. We used our experiment's point cloud images to apply different machine learning models to detect these objects. Using a top-view (TV) filter to convert 3-D point cloud images into 2-D representations made object detection more accurate. Following the use of filtration techniques, we extracted features from the filtered 2-D image using the visual geometry group (VGG) 16 model. We then assessed four machine learning models for object detection and found that the support vector machine (SVM) model and logistic regression (LR) had better results, obtaining an accuracy of 97%. Our proposed work uses mmWave radar, TV filter, VGG 16 Model, and LR to highly increase object detection accuracy over existing methods.

关键词： Radar Object detection Radar detection Point cloud compression Millimeter wave radar field programmable gate arrays Accuracy Radar imaging Millimeter wave communication Feature extraction Sensor applications field-programmable gate array (FPGA) board mmWave radar machine learning object detection PYNQ-ZU point cloud images support vector machine (SVM) VGG 16 model

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FOG: Fast Octree Generator for LiDAR Point Clouds

IEEE SENSORS LETTERS

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IEEE SENSORS LETTERS 2025年第1期9卷

作者： Roriz, Ricardo Costa, Diogo Ekpanyapong, Mongkol Gomes, Tiago Univ Minho ALGORITMI Res Ctr LASI P-4800058 Guimaraes Portugal Asian Inst Technol Sch Engn & Technol Pathum Thani 12120 Thailand

As the need for realistic and immersive 3-D representations of the environment continues to increase across various industries, finding efficient ways to represent data has become paramount. A well-known approach to partitioning 3-D space into a structured data format is the use of octrees, primarily due to their efficiency in handling both sparse and dense 3-D data. This method is particularly useful in applications involving automotive light detection and ranging (LiDAR) sensors, which are widely used in autonomous driving systems for their ability to capture detailed spatial information in real-time. This letter introduces the fast octree generator (FOG) algorithm, a novel approach for generating octrees from 3-D LiDAR point clouds that leverages hardware acceleration. FOG achieves a performance improvement of up to 88.8% compared to PCL's octree implementation, enabling real-time octree generation for high-end sensors on embedded platforms.

关键词： Octrees Three-dimensional displays Point cloud compression Sensors Image reconstruction Laser radar Codes Real-time systems PSNR field programmable gate arrays Sensor applications 3-D light detection and ranging (LiDAR) field-programmable gate array (FPGA) octree

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Implementations for Scattering at 1.8 Volt Between Battery-Less Transponder and Mobile Telephones

IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION

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IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION 2024年 8卷 671-676页

作者： Willi, Roman Kamm, Lars Zbinden, Paul Schutz, Matthias OST Eastern Switzerland Univ Appl Sci Inst Microelect & Embedded Syst CH-9000 St Gallen Switzerland Idp Invent Ag CH-4600 Olten Switzerland

This work concerns advanced implementations of a battery-less transponder operated by intentionally generated wireless signals in the 2.4 GHz ISM band. The wireless signals consist of a power supplying data stream and of a quasi-continuous Bluetooth RF (radio frequency) signal, which enables the transponder to back-scatter the RF signal to a receiver. Our setup uses two regular, unmodified mobile telephones, one for transmitting the signals, the other for receiving the scattered signals. The transponder modulates the quasi-continuous RF signal according to a subcarrier and a predetermined 1 Mbit/s bit-stream. The present extended study further compares advanced implementation techniques: Micro Controller Unit (MCU), FPGA (field programmable gate Array), CPLD (Complex programmable Logic Device) and ASIC (Application Specific Integrated Circuit) and implements a CPLD test version. Experimental results suggest that our CPLD is more suitable than MCU or FPGA implementations. The paper further demonstrates the transition from a fully synchronous to a low-power asynchronous CPLD implementation. The measured power consumption for generating the bit-stream is 87 mu W, which results in a 6-fold reduction compared to our previous work. Accordingly, the asynchronous CPLD implementation increases total efficiency by 40% and it is expected that this will significantly extend the wireless operational range of the battery-less transponder. Thus, the CPLD technology enables fast, flexible, and cost-effective implementation, particularly in the field of research and development.

关键词： Transponders Clocks Telephone sets field programmable gate arrays Radiofrequency identification Radio frequency Power demand Back-scattering battery-less harvesting mobile telephone subcarrier MCU DMA FPGA CPLD ASIC

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Low Area and Low Power FPGA Implementation of a DBSCAN-Based RF Modulation Classifier

IEEE OPEN JOURNAL OF THE COMPUTER SOCIETY

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IEEE OPEN JOURNAL OF THE COMPUTER SOCIETY 2024年第1期5卷 50-61页

作者： Gavin, Bill Deng, Tiantai Ball, Edward Univ Sheffield Dept Elect & Elect Engn Sheffield S1 3JD England

This paper presents a new low-area and low-power field programmable gate Array (FPGA) implementation of a Radio Frequency (RF) modulation classifier based on the Density-Based Spatial Clustering of Applications with Noise (DBSCAN) algorithm, known as DBCLASS. The proposed architecture demonstrates a novel approach for the efficient hardware realisation of the DBSCAN algorithm by utilising parallelism, a bespoke sorting algorithm, and eliminating memory access. The design achieves 100% classification accuracy with lab-captured RF data above 8 dB signal-to-noise ratio(SNR) whilst exhibiting an improvement of latency in comparison to the next quickest design by a factor of 7.5, a reduction in terms of total FPGA resources used in comparison to the next smallest complete system by a factor of 3.65, and a reduction in power consumption over the next most efficient by a factor of 4.75. The proposed design is well suited for resource-constrained applications, such as mobile cognitive radios and spectrum monitoring systems.

关键词： Modulation field programmable gate arrays Signal to noise ratio Delays Classification algorithms Hardware Convolutional neural networks RF classifier cognitive radio DBSCAN FPGA automatic modulation classification AMC beyond smart radio

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One-Dimensional Binary Convolutional Neural Network Accelerator Design for Bearing Fault Diagnosis

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IEEE SENSORS JOURNAL 2024年第3期24卷 3649-3658页

作者： Syu, Zih-Syuan Lee, Ching-Hung Natl Yang Ming Chiao Tung Univ Inst Elect & Control Engn Hsinchu 30010 Taiwan

In the field of equipment anomaly detection, anomalies in equipment or tooling machines can be detected earlier by analyzing vibration signals. However, hardware platforms, such as graphics processing units (GPUs), tensor processing units (TPUs), and workstations, are commonly used for the applications of artificial intelligence (AI), which limits the practical applications due to high-power consumption and high cost;the corresponding large amount of computation reduces the inference speed in real-time industrial environments. In this study, we propose a binary neural network (BNN) accelerator and implement it in a field-programmable gate array (FPGA) for bearing fault diagnosis. By using a 1-D convolutional neural network (CNN), we extract the features of vibration signals and classify the classes of bearing faults with high accuracy. The model weights are trained with only one bit by using a knowledge distillation and binarization algorithm to reduce the storage space. We adopt the FPGA, a reprogrammable, low-power, low-cost platform for CNN implementation. The original convolutional operation is replaced with a more efficient algorithm and a specialized binary model computation engine is designed to accelerate model inference and reduce ON-chip resource utilization. Experimental results and comparisons are introduced to show the optimized binary model required only 0.42 ms to infer on the hardware platform, which is 150 times faster than a 32-bit floating-point neural network of the same architecture and still maintained a higher testing accuracy of 98.5%.

关键词： Feature extraction Computational modeling Deep learning Hardware Neural networks field programmable gate arrays Convolutional neural networks Bearing fault diagnosis binary neural networks (BNNs) compression field-programmable gate array (FPGA) model acceleration

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A Reduced-Order Digital Twin FPGA-Based Implementation With Self-Awareness Capabilities for Power Electronics Applications

IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION

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IEEE JOURNAL OF RADIO FREQUENCY IDENTIFICATION 2024年 8卷 493-505页

作者： Nwoke, Justus Milanesi, Marco Viola, Jairo Chen, Yangquan Visioli, Antonio Univ Californiaat Merced Mechatron Embedded Syst & Automat Lab Merced CA 94343 USA Univ Brescia Dept Mech land Ind Engn Brescia Italy

Developing accurate mathematical or data-driven models for effective controller design under dynamic variable conditions becomes increasingly challenging. For this reason, the concept of a digital twin (DT) as a virtual representation of a physical asset has been introduced as a tool for process modelling, design, and control implementation while providing additional knowledge of the system that can be used to enable awareness capabilities on the asset. However, digital twin models used to be complex, requiring expensive computational times depending on the application to provide the most accurate system representation, limiting its application in edge, embedded, and register transfer level computing domains. Therefore, using reduced-order digital twin models is an alternative to get DT closer to the physical asset. Considering these challenges, we propose a reduced-order FPGA-based digital twin implementation that directly sources data from the real system, operates in parallel with the virtual system, and enables awareness mechanisms to improve the system's operation. This setup removes large data transfers, cloud interfaces and expensive computational times deriving into a faster and more efficient DT. To illustrate the capabilities of this embedded digital twin, we present a case study focused on monitoring a power converter. The study involves establishing and enforcing a safe operating area (SOA) for the power converter, implementing error awareness mechanisms, and enabling machine learning models to predict converter load conditions and fault events detection. Thus, we aim to showcase the effectiveness of our proposed FPGA-based digital twin approach in addressing real-time control challenges towards smart control engineering.

关键词： Digital twins Buck converters field programmable gate arrays Read only memory Cloud computing Real-time systems Computational modeling Digital twin flyback converter smart control engineering FPGA embedded digital twin Industry 4.0

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