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检索条件"主题词=Field Programmable Gate Arrays"

共 41642 条记录，以下是581-590 订阅

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Design of Measurement and Control System of Suspension Support Device Based on LabView and FPGA

Design of Measurement and Control System of Suspension Suppo...

引用

Electrical Automation and Artificial Intelligence (ICEAAI), International Conference on

作者： Naijian Zhang Han Wu Zhongwei Du North China University of Technology School of Mechanical and Materials Engineering Beijing China Beijing Information Science and Technology University School of Instrument Science and Optoelectronic Engineering Beijing China

ISBN: (数字)9798331506797

ISBN: (纸本)9798331506803

To ensure flight safety of newly developed aircraft model, it is necessary to conduct wind tunnel stability tests of a scaled-down aircraft model under support of a multi-degree-of-freedom suspension support device in a wind tunnel. In this paper, measurement and control system of the suspension support device is designed to adjust aircraft model's attitude and collect information from various sensors of the support device. The measurement and control system was designed based on LabVIEW and FPGA; FPGA control board is responsible for servo motor control, and control and measurement software system was built by using LabVIEW. This system is responsible for signal transmission and reception, data processing, and storage. Following experimental verification, it has been demonstrated that the measurement and control system designed in this paper can meet requirements of parallel processing of multiple data types, large amounts of information, and aircraft model attitude control during the test.

关键词： Attitude control Atmospheric modeling Wind tunnels Electric variables measurement Control systems Stability analysis Data models Software measurement Aircraft field programmable gate arrays

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Dynamic Partial Reconfiguration of FPGAs for Energy-Efficient Machine Learning Inference in IoT Systems

Dynamic Partial Reconfiguration of FPGAs for Energy-Efficien...

引用

IEEE International Symposium on Quality Electronic Design

作者： Ethan Chen Junting Deng Chia Jen Cheng Jiachen Xu John Kan Yuyi Shen Vanessa Chen Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

This work introduces a dynamic partial reconfiguration (PR) approach for field-programmable gate arrays (FPGAs) to enhance the performance, energy efficiency, and adaptability of IoT systems. By enabling run-time reconfiguration, PR allows flexible allocation of resources for machine learning (ML) tasks, minimizing energy consumption and hardware demands. The method replaces fixed-length floating-point arithmetic with variable bit-width representations, reducing memory usage and computational complexity without sacrificing accuracy. Demonstrated on Graph Convolution Network (GCN)-YOLO models, this approach efficiently handles diverse ML layers while achieving significant improvements in resource utilization, latency, and energy savings. These results establish a scalable framework for real-time edge intelligence in IoT applications.

关键词： Adaptation models Scalability Machine learning Dynamic scheduling Energy efficiency Hardware Real-time systems Internet of Things Resource management field programmable gate arrays

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Design and Implementation of Single Master Single Slave Serial Peripheral Interface (SPI) on FPGA

Design and Implementation of Single Master Single Slave Seri...

引用

IEEE Students' Conference on Electrical, Electronics and Computer Science (SCEECS)

作者： Shardul Penurkar Abhishek Kumar Saurabh Srivastava Sangeeta Nakhate Department of Electronics and Communication Engineering Maulana Azad National Institute of Technology Bhopal India

ISBN: (数字)9798331529833

ISBN: (纸本)9798331529840

This paper presents the design and analysis of a Single Master Single Slave Serial Peripheral Interface (SPI) system implemented on an FPGA. SPI is a communication protocol that enables data transfer between devices by designating master and slave roles. Despite its utility, existing peripheral communication protocols have limitations. While parallel communication requires extensive wiring and is prone to noise and crosstalk, serial communication can be slower, consume more power, and result in lower throughput. This study aims to develop an SPI module optimized for single-slave operation. Simulations conducted using AMD Vivado confirmed the module's functionality, and the design was successfully implemented on a Nexys 4 DDR FPGA board. In conclusion, the Single Master Single Slave SPI module was effectively designed and verified.

关键词： Wiring Noise Logic gates Throughput Main-secondary Software Reliability Hardware design languages field programmable gate arrays Testing

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Non-Homogeneous Composite Karatsuba Multipliers Factored Hardware-Efficient ECDSA Generation and Verification Accelerator Units

Non-Homogeneous Composite Karatsuba Multipliers Factored Har...

引用

IEEE International Symposium on Quality Electronic Design

作者： Pruthvi Parate Alwin Shaju Sanampudi Gopala Krishna Reddy Vasanthi D R Madhav Rao IIIT Bangalore

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

The Elliptic Curve Digital Signature Algorithm (ECDSA) is a cryptographic method superior to the existing Digital Signature Algorithm (DSA). ECDSA utilizes an elliptic curve formulation for achieving tighter security and efficiency, making it well-suited for resource-constrained environments. This work presents a study of the ECDSA architecture, including the design and implementation of optimized GF(2 163 ) Karatsuba multipliers for signature generation and verification. The design was synthesized on a Kintex Ultrascale FPGA board and on silicon using the gpdk-45 nm technology library. We investigated the complete signature generation and verification architecture with non-homogeneous and composite Karatsuba multiplier variants and compared them with state-of-the-art (SOTA) multipliers over hardware metrics. Furthermore, we extracted and compared the results for the multiplier implementation alone, showing superior performance over the SOTA. The M-term Non-Homogeneous Karatsuba Multiplier (MNHKA), integrated into the ECDSA architecture, demonstrated the most hardware-efficient design on both FPGA and silicon, achieving substantial LUT savings of 50.42% and 37.50%, latency improvements of 52.29% and 43.86%, and throughput benefits of 16.66% and 43.86% for signature generation and verification accelerator units, respectively. Additionally, footprint gains on silicon were 56.63% for signature generation and 45.99% for verification units compared to SOTA designs. These efficient variants of polynomial multipliers are found to be apt for ECDSA hardware accelerators over other existing forms of designs and is therefore, expected to enhance hardware security, reliability, and performance. All the hardware design files are made freely available for further usage to the designers and researchers community.

关键词： Handwriting recognition Elliptic curves Hardware security Throughput Silicon Polynomials Table lookup field programmable gate arrays Digital signatures Hardware acceleration

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ASIC Design of an Interval Type-2 Fuzzy Logic Engine for Control Application

ASIC Design of an Interval Type-2 Fuzzy Logic Engine for Con...

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Devices for Integrated Circuit (DevIC)

作者： Susmit Sanyal Aditya Bhattacharjee Dipanjan Konar Sayantani Ghosh Sayan Chatterjee Department of Electronics and Telecommunications Engineering Jadavpur University Kolkata India Institute of Radio Physics and Electronics University of Calcutta Kolkata India

ISBN: (数字)9798350391107

ISBN: (纸本)9798350391114

Despite the existence of VLSI engines for inference generation using type-1 fuzzy sets, little is known about (interval) type-2 fuzzy VLSI engines. An ASIC-based type-2 fuzzy inference engine that was created in two stages is presented in this work. A traditional state-machine method is used in the first stage to construct the control logic and dataflow pathways. In order to verify time restrictions and enhance circuit performance, the inference engine is synthesized on an FPGA in the second stage. Synopsys Design Compiler is used to realize the final hardware implementation. When compared to current implementations, the suggested design performs better in terms of processing speed, resource usage, and inference accuracy. Our method overcomes the drawbacks of current type-1 fuzzy hardware and provides a scalable and effective solution for real-time fuzzy inference applications.

关键词： Fuzzy logic Performance evaluation Fuzzy sets Power demand Firing Very large scale integration Hardware Real-time systems Engines field programmable gate arrays

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A Low-Cost Accelerator for License Plate Character Recognition Using Convolutional Neural Networks

A Low-Cost Accelerator for License Plate Character Recogniti...

引用

IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： George B. Nardes Thiago H. Rausch Douglas R. Melo Cesar A. Zeferino LEDS University of Vale do Itajai Itajai Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

Convolutional Neural Networks (CNNs) are widely used for optical character recognition of vehicle license plates in automatic license plate recognition (ALPR) systems. However, their high computational complexity makes meeting specific ALPR applications' time and cost requirements challenging. This work aimed to develop a CNN architecture and select a hardware acceleration technique to create a low-cost optical character recognition (OCR) system capable of real-time vehicle identification. We designed the CNN architecture with accuracy and simplicity in mind, and we chose the hardware acceleration technique based on silicon cost and performance. Our 8-bit quantized CNN achieved an accuracy of 97.11%, and the accelerator resulted in a latency of 4.21 ms and a throughput of 598 FPS. The solution offers accuracy and performance comparable to related work methods, using less than 20% of the hardware resources.

关键词： Accuracy Costs Computer architecture Throughput Real-time systems Convolutional neural networks Character recognition License plate recognition Hardware acceleration field programmable gate arrays

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Subnet Level Anomaly Detection at Time Units Using VAE

Subnet Level Anomaly Detection at Time Units Using VAE

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International Conference on Electronics, Information and Communications (ICEIC)

作者： Tatsuki Nishida Shigeki Aoki Masaya Ohta Takao Miyamoto Graduate School of Informatics Osaka Metropolitan University Osaka Japan

ISBN: (数字)9798331510756

ISBN: (纸本)9798331510763

With the rise in cyberattacks in recent years, research on Intrusion Detection Systems (IDS) has become increasingly active. In this study, we propose a novel IDS that detects anomalies in network traffic and estimates the source subnet of an attack by applying a Variational Autoencoder (VAE). During the training phase, normal traffic data is segmented into time units, and feature vectors are generated for each subnet. These feature vectors are then trained using the VAE. Subsequently, feature vectors are generated from traffic data containing anomalies using the same method as in the training phase. The generated feature vectors are reconstructed using the trained VAE, and subnets with high reconstruction errors are identified as the source sub nets of the attack. This method performs training and reconstruction for each subnet at each time unit, enabling the detection of the source sub net of an attack with low processing cost. In our experiment, we trained on the Monday dataset of CICIDS2017 and detected attacks in the datasets from Tuesday to Friday. Additionally, we implemented the reconstruction process of this method on a field programmable gate Array (FPGA) and evaluated its performance.

关键词： Training Costs Autoencoders Intrusion detection Telecommunication traffic Logic gates Feature extraction Vectors field programmable gate arrays Anomaly detection

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Defending Side-Channel Attacks in Convolutional Neural Networks with Channel-Level Parallelization

Defending Side-Channel Attacks in Convolutional Neural Netwo...

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Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Yankun Zhu Ranxi Lin Pingqiang Zhou ShanghaiTech University Shanghai China

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

Side-channel attacks (SCAs) pose significant threats to the security of neural networks (NNs) deployed on hardware platforms, especially in cloud field-programmable gate Array (FPGA) environments. This paper presents a novel approach to enhance the security of convolutional layers in NNs against SCAs by introducing a channel-level parallel structure. Compared with the original structure and the state-of-the-art masking technique, the channel-level parallel structure significantly reduces the success rate of SCAs (from 97.13% to 5.46% on average) and is able to be optimized for either low resource overhead (83.64% reduction) or good timing performance (83.01% improvement).

关键词： Side-channel attacks Hardware Timing Security Convolutional neural networks field programmable gate arrays

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Area and Power Modeling of FPGA Based Binary-to-Gray Code Converter Circuit for Rotary Encoder

Area and Power Modeling of FPGA Based Binary-to-Gray Code Co...

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Cognitive Computing in Engineering, Communications, Sciences and Biomedical Health Informatics (IC3ECSBHI), International Conference on

作者： Radhika Gupta Priti Kumari Rashi Jaiswal Tukur Gupta Department of Electronics & Communication Engineering Ajay Kumar Garg Engineering College Ghaziabad India

ISBN: (数字)9798331518523

ISBN: (纸本)9798331518530

The rotary encoders are crucial components of many precision control systems and using gray codes in such systems helps ensure accurate positional data. Hence, it is imperative to efficiently convert binary data to gray code in order to reduce tracking errors. Area and power being two main design constraints for digital circuits need to be estimated. Even though the current commercial tools can be used to make these estimates, doing so takes more time because complete design cycles need to be followed. Accurately estimating resource usage and power dissipation early in the design process while working under tight deadline is therefore one of the biggest challenges for designers. None of the existing literature address the modeling of area and power for binary-to-gray converter circuits. This paper proposes area and power estimation models of field programmable gate arrays (FPGA) based binary-to- gray code converter circuits. The converter circuits are described using very high-speed integrated circuit hardware description language (VHDL), and synthesized using Vivado 2014.2 tool targeted to Zynq family FPGAs device (xc7z020clg484-1). The proposed models are developed in MATLAB Curve Fit tool using regression approach of machine learning. Using the proposed models, the FPGA resource utilization and power dissipation of binary-to-gray code converter circuits are predicted and compared with the reports obtained using Vivado tool. The low values of estimation error obtained in all cases demonstrate the high accuracy of proposed area and power models.

关键词： Codes Accuracy Power demand Computational modeling Circuits Predictive models Reflective binary codes Power dissipation Integrated circuit modeling field programmable gate arrays

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Resource and Performance Improvements of Optimized Convolutional Neural Networks for FPGA Implementations of Automatic Modulation Recognition

Resource and Performance Improvements of Optimized Convoluti...

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Annual Conference on Information Sciences and Systems (CISS)

作者： Joshua A Rothe Haya Shajaiah Whiting School of Engineering Johns Hopkins University Baltimore MD United States

ISBN: (数字)9798331513269

ISBN: (纸本)9798331513276

Automatic Modulation Recognition (AMR), commonly found in software defined radios, relies on speed and accuracy to effectively interpret the modulation type of incoming signals. Convolutional Neural Networks (CNNs) are growing in popularity over traditional algorithms due to their excellent performance with classification-type problems – but these are typically resource intensive, and Radio Frequency (RF) receivers are typically part of a larger system that can benefit from less resources being tied to this classification task. field programmable gate Array (FPGA) implementations provide better performance than CPU and GPU implementations in most cases, and the added benefit of these functions being off the processor allows the entire system to perform better. Since resource utilization is such a critical component of effective CNN implementation, and it is often inversely tied to performance, the effectiveness of various hardware optimization techniques as well as their effects on performance should be considered by the designer. This work evaluates the tradeoffs of various model optimizations and how they affect both implementation and performance, synthesizing the models using Xilinx’s quantization-aware FINN library. In this work, a methodology is presented for the generation of I and Q signals for CNN model training and evaluation, and the performance and hardware utilization benchmarks are evaluated to determine both design considerations and effective approaches for optimizing these models for real-world implementation.

关键词： Training Software algorithms Modulation Logic gates Hardware Convolutional neural networks Resource management field programmable gate arrays Optimization Software radio

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