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检索条件"主题词=Field Programmable Gate Arrays"
41670 条 记 录,以下是51-60 订阅
Long term storage reliability of antifuse field programmable gate arrays
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MICROELECTRONICS RELIABILITY 2013年 第12期53卷 2052-2056页
作者: Patil, Nishad Das, Diganta Scanff, Estelle Pecht, Michael Univ Maryland Ctr Adv Life Cycle Engn College Pk MD 20742 USA
field programmable gate arrays (FPGA) with antifuse elements are preferred in aerospace applications due to their non-volatility and demonstrated radiation hardness. Because aerospace applications typically involve lo... 详细信息
来源: 评论
field programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systems
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JOURNAL OF ELECTRONIC IMAGING 2013年 第1期22卷 013009-013009页
作者: Zhai, Xiaojun Bensaali, Faycal Sotudeh, Reza Univ Hertfordshire Sch Engn & Technol Hatfield AL10 9AB Herts England
Number plate (NP) binarization and adjustment are important preprocessing stages in automatic number plate recognition (ANPR) systems and are used to link the number plate localization (NPL) and character segmentation... 详细信息
来源: 评论
Design of Sobel Operator Using field programmable gate arrays
Design of Sobel Operator Using Field Programmable Gate Array...
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International Conference on Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE)
作者: Alghurair, Dina Al-Rawi, Sefwan S. Specialist Trainer in Computer Department Higher Institute for Telecommunication and Navigation PAAET. Kuwait|c|
The last decade has a rapid development in the structure of a programmable processor called field programmable gate Array (FPGA), which is used to implement a hardware circuit to perform the functions for high speed a... 详细信息
来源: 评论
A High-Resolution Calibration Method for Time-to-Digital Converter of Lidar
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Chinese Journal of Electronics 2025年 第1期34卷 222-228页
作者: Ruqing Liu Feng Li Jingguo Zhu Yan Jiang Chenghao Jiang Tao Hu Institute of Microelectronics of the Chinese Academy of Sciences
High-resolution time-to-digital converter(TDC) finds major applications in light detection and ranging(Lidar) systems as one of the high precision time measuring techniques. In this work, a high-resolution TDC is desi... 详细信息
来源: 评论
FLALM: A Flexible Low Area-Latency Montgomery Modular Multiplication on FPGA
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IEEE TRANSACTIONS ON COMPUTERS 2025年 第1期74卷 29-42页
作者: Xie, Yujun Liu, Yuan Zheng, Xin Lan, Bohan Lei, Dengyun Xiang, Dehao Cai, Shuting Xiong, Xiaoming Guangdong Univ Technol Sch Integrated Circuits Guangzhou 510006 Peoples R China Dalian Univ Technol Sch Software Technol Dalian 116024 Peoples R China Sun Yat Sen Univ Sch Elect & Informat Engn Guangzhou 510006 Peoples R China
Montgomery Modular Multiplication (MMM) is widely used in many public key cryptography systems. This paper presents a Flexible Low Area-Latency MMM (FLALM) implementation, which supports Generic Montgomery Modular Mul... 详细信息
来源: 评论
CoaCAD: Correlation-Assisted Computer-Aided Design for Nonvolatile FPGAs
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2025年 第1期44卷 144-156页
作者: Zhao, Mengying Xiong, Yuqing Zhang, Hao Zheng, Huichuan Yu, Dongxiao Shen, Zhaoyan Shandong Univ Sch Comp Sci & technol Jinan 250100 Peoples R China
Nonvolatile field-programmable gate arrays (FPGAs) offer advantages in terms of high logic density and near-zero leakage power when contrasted with conventional static random access memory-based FPGAs. However, they h... 详细信息
来源: 评论
Assessing NI FPGA-Based Platform With MXIe Interface for Use in ITER Hard Real-Time Investment Protection Applications
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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年 第3期72卷 530-537页
作者: Karkinsky, D. Marqueta, A. Barrera, E. Garcia-Siguero, I. Varlec, J. Ruiz, M. Sekoranja, M. Rebollo, P. Kogovsek, T. ITER Org F-13115 St Paul Les Durance France Univ Politecn Madrid Instrumentat & Appl Acoust Res Grp Madrid 28031 Spain Cosylab Ljubljana 1000 Slovenia
The ITER interlock control system (ICS) assumes a crucial role in the tokamak operation to protect the investment against machine protection hazards. Consequently, it must be developed in compliance with the most chal... 详细信息
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Efficient FPGA Implementation of Multi-Channel Pipelined Large FFT Architectures Based on SA-MDF Algorithm
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年 第5期72卷 2189-2201页
作者: Hu, Tang Hao, Chunling Wang, Xier Liu, Zhiwei Ren, Songnan Xu, Zhiwei Zhu, Shiqiang Zhejiang Univ Ocean Coll Zhoushan 316021 Peoples R China Zhejiang Lab Res Ctr Intelligent Chips & Devices Hangzhou 311121 Peoples R China
FPGA implementation of a multi-channel pipelined large FFT architecture is challenging due to its complex inter-channel data scheduling, high-throughput requirement, and resource-constrained hardware. By transforming ... 详细信息
来源: 评论
White Gaussian Noise Generation With a Vacuum State Quantum Entropy Source Chip
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IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS 2025年 第5期31卷
作者: Qiao, Guan-Ru Bai, Bing Weng, Zi-Xuan Wu, Jia-Ying Nie, You-Qi Zhang, Jun Univ Sci & Technol China Microscale & Sch Phys Sci Hefei Natl Res Ctr Phys Sci Hefei 230026 Peoples R China Univ Sci & Technol China CAS Ctr Excellence Quantum Informat & Quantum Phys Hefei 230026 Peoples R China Univ Sci & Technol China Hefei Natl Lab Hefei 230088 Peoples R China
White Gaussian noise (WGN) is widely used in communication system testing, physical modeling, Monte Carlo simulations, and electronic countermeasures. WGN generation relies heavily on random numbers. In this work, we ... 详细信息
来源: 评论
General-Purpose Data Streaming FPGA TDC Synchronized by SerDes-Based Clock Synchronization Technique
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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年 第3期72卷 614-622页
作者: Honda, Ryotaro Ikeno, Masahiro Lin, Che-Sheng Shoji, Masayoshi High Energy Accelerator Res Org Inst Particle & Nucl Studies Tsukuba 3050801 Japan Osaka Univ Res Ctr Nucl Phys Osaka Ibaraki 5670047 Japan
This study proposes a clock synchronization protocol using the functionalities of IDELAYE2 and IOSERDESE2 primitives of an AMD Xilinx field-programmable gate array (FPGA) to serve as a general-purpose data-streaming t... 详细信息
来源: 评论