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Long term storage reliability of antifuse field programmable gate arrays

MICROELECTRONICS RELIABILITY 2013年第12期53卷 2052-2056页

作者： Patil, Nishad Das, Diganta Scanff, Estelle Pecht, Michael Univ Maryland Ctr Adv Life Cycle Engn College Pk MD 20742 USA

field programmable gate arrays (FPGA) with antifuse elements are preferred in aerospace applications due to their non-volatility and demonstrated radiation hardness. Because aerospace applications typically involve long operating life, there is a requirement to store un-programmed antifuse FPGA parts for long periods and program them when necessary to support the system. No study on the long term reliability of un-programmed antifuse FPGAs in the storage environment is reported in literature. In this paper, antifuse structures, programming process, and failure mechanisms of antifuse FPGAs are discussed. A failure modes, mechanisms and effects (FMMEA) analysis was performed for storage conditions and critical failure mechanisms were identified. High temperature storage tests of a select number of antifuse FPGAs were performed to accelerate the identified failure mechanisms. These parts were subsequently programmed and yield data was analyzed to determine the effects of high temperature storage. (C) 2013 Elsevier Ltd. All rights reserved.

关键词： field programmable gate arrays MICROHARDNESS FRACTURE mechanics RELIABILITY (Engineering) HIGH temperatures AEROSPACE engineering

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field programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systems

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JOURNAL OF ELECTRONIC IMAGING 2013年第1期22卷 013009-013009页

作者： Zhai, Xiaojun Bensaali, Faycal Sotudeh, Reza Univ Hertfordshire Sch Engn & Technol Hatfield AL10 9AB Herts England

Number plate (NP) binarization and adjustment are important preprocessing stages in automatic number plate recognition (ANPR) systems and are used to link the number plate localization (NPL) and character segmentation stages. Successfully linking these two stages will improve the performance of the entire ANPR system. We present two optimized low-complexity NP binarization and adjustment algorithms. Efficient area/speed architectures based on the proposed algorithms are also presented and have been successfully implemented and tested using the Mentor Graphics RC240 FPGA development board, which together require only 9% of the available on-chip resources of a Virtex-4 FPGA, run with a maximum frequency of 95.8 MHz and are capable of processing one image in 0.07 to 0.17 ms. (C) 2013 SPIE and IS&T [DOI: 10.1117/***.22.1.013009]

关键词： Algorithms field programmable gate arrays Data storage Computer hardware Clocks

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Design of Sobel Operator Using field programmable gate arrays

Design of Sobel Operator Using Field Programmable Gate Array...

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International Conference on Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE)

作者： Alghurair, Dina Al-Rawi, Sefwan S. Specialist Trainer in Computer Department Higher Institute for Telecommunication and Navigation PAAET. Kuwait|c|

ISBN: (纸本)9781467356138;9781467356121

The last decade has a rapid development in the structure of a programmable processor called field programmable gate Array (FPGA), which is used to implement a hardware circuit to perform the functions for high speed application. Sobel edge detection is a method to find the edge pixels in an image. This method exploits the change in intensity with respect to neighboring pixels. This paper introduces the implementation of Sobel edge detection method in the FPGA processor [1,2]. The implementation is performed based on two FPGA families from Xilinx, Spartan and Virtex. The cost of these implementations using Spartan3 is 41.66%, Spartan6 is 70%, Virtex5 is 3.69% and Virtex6 is 3.61%. The frequency is 169.188 MHz for using Spartan3, 45.7 MHz for Spartan6, 85.060 MHz for Virtex5 and 65.8 MHz for Virtex6.

关键词： edge detection field programmable gate arrays

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A High-Resolution Calibration Method for Time-to-Digital Converter of Lidar

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Chinese Journal of Electronics 2025年第1期34卷 222-228页

作者： Ruqing Liu Feng Li Jingguo Zhu Yan Jiang Chenghao Jiang Tao Hu Institute of Microelectronics of the Chinese Academy of Sciences

High-resolution time-to-digital converter(TDC) finds major applications in light detection and ranging(Lidar) systems as one of the high precision time measuring techniques. In this work, a high-resolution TDC is designed and implemented on a Xilinx field-programmable gate array(FPGA) board. For precision time measurements, the proposed TDC uses an internal tapped delay chain written in Verilog. The TDC circuit measurement errors are examined and calibrated following several principles of error reduction techniques to meet the specific demand for the high-precision Lidar range. Experiments have shown that the suggested calibration TDC has higher performance, achieving sub-35 ps resolution. The design is fully customizable and implemented as a set of separate intellectual property cores. This allows for easy implementation and meets the requirements of the present-day pulse Lidar systems.

关键词： Temperature measurement Laser radar Voltage measurement Systematics Time measurement Distance measurement Delays Calibration field programmable gate arrays Thermal stability

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FLALM: A Flexible Low Area-Latency Montgomery Modular Multiplication on FPGA

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IEEE TRANSACTIONS ON COMPUTERS 2025年第1期74卷 29-42页

作者： Xie, Yujun Liu, Yuan Zheng, Xin Lan, Bohan Lei, Dengyun Xiang, Dehao Cai, Shuting Xiong, Xiaoming Guangdong Univ Technol Sch Integrated Circuits Guangzhou 510006 Peoples R China Dalian Univ Technol Sch Software Technol Dalian 116024 Peoples R China Sun Yat Sen Univ Sch Elect & Informat Engn Guangzhou 510006 Peoples R China

Montgomery Modular Multiplication (MMM) is widely used in many public key cryptography systems. This paper presents a Flexible Low Area-Latency MMM (FLALM) implementation, which supports Generic Montgomery Modular Multiplication (GMM) and Square Montgomery Modular Multiplication (SMM) operations. A new SMM schedule for the Finely Integrated Product Scanning (FIPS) GMM algorithm is proposed to accelerate SMM with tiny additional design. Furthermore, a new FIPS dual-schedule is proposed to solve the data hazards of this algorithm. Finally, we explore the trade-off between area and latency, and present the FLALM to accelerate GMM and SMM. The FLALM is implemented on FPGA (Virtex-7 platform). The results show that the area*latency (AL) value of FLALM (wordsize w=128) is 38.1% and 44.7% better than the previous state-of-art scalable references when performing 1024-bit and 2048-bit GMM, respectively. Moreover, when computing SMM, the advantage of AL value is raised to 73.7% and 86.3% respectively.

关键词： Adders Schedules Hazards field programmable gate arrays Delays Computers Hardware acceleration Cryptography montgomery modular multiplication generic montgomery modular multiplication square montgomery modular multiplication finely integrated product scanning

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CoaCAD: Correlation-Assisted Computer-Aided Design for Nonvolatile FPGAs

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2025年第1期44卷 144-156页

作者： Zhao, Mengying Xiong, Yuqing Zhang, Hao Zheng, Huichuan Yu, Dongxiao Shen, Zhaoyan Shandong Univ Sch Comp Sci & technol Jinan 250100 Peoples R China

Nonvolatile field-programmable gate arrays (FPGAs) offer advantages in terms of high logic density and near-zero leakage power when contrasted with conventional static random access memory-based FPGAs. However, they have a lifetime issue. To deal with this problem, a series of configuration files can be generated with various logical-to-physical mappings. This enables intensive writing to be distributed across different physical regions for wear leveling. Currently, the configuration files are independently generated, which is time consuming. In this article, we propose to investigate correlations and use them to assist the computer-aided design (CAD) flow to speed up the procedure of generating configuration files. First, we develop dynamic probabilities to drive the swapping of placement stage in CAD flow, so as to push components to locate appropriate positions quickly. Second, we design the congestion information inheritance strategy to adjust routing parameters in the routing stage, aiming to reduce the number of routing attempts. Evaluation shows that the proposed schemes can deliver 44.15% decrease in placement and routing runtime, while maintaining comparable performance and lifetime, when compared with existing strategies.

关键词： field programmable gate arrays Routing Design automation Correlation Random access memory Nonvolatile memory Logic Computer-aided design (CAD) field-programmable gate array (FPGA) nonvolatile memory wear leveling

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Assessing NI FPGA-Based Platform With MXIe Interface for Use in ITER Hard Real-Time Investment Protection Applications

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 530-537页

作者： Karkinsky, D. Marqueta, A. Barrera, E. Garcia-Siguero, I. Varlec, J. Ruiz, M. Sekoranja, M. Rebollo, P. Kogovsek, T. ITER Org F-13115 St Paul Les Durance France Univ Politecn Madrid Instrumentat & Appl Acoust Res Grp Madrid 28031 Spain Cosylab Ljubljana 1000 Slovenia

The ITER interlock control system (ICS) assumes a crucial role in the tokamak operation to protect the investment against machine protection hazards. Consequently, it must be developed in compliance with the most challenging requirements. The National Instruments CompactRIO (NI cRIO) technology was chosen by ITER as the field-programmable gate array (FPGA)-based platform to develop the investment protection functions, with strict time constraints. This contribution focuses on the specific requirements for the ITER advanced protection system (APS) where the disruption mitigation control function requires a sequenced release of hydrogen ice pellets with an accuracy of less than 1 ms. These requirements are an evolution of previous protection system designs based on CompactRIO (cRIO) and motivated this feasibility study. The cRIO platform used at ITER is the NI9159, which provides an MXIe interface between a Virtex 5 LX110 FPGA and a host computer running a Linux preemptive kernel. ITER decided to improve two important requirements: 1) the MXIe interface communication latency's jitter by redesigning the ITER National Instruments (NI)-RIO Linux device driver and 2) the ability to timestamp events in the FPGA logic by designing a specific firmware module based on the precision time protocol (PTP) as used in the ITER time communication network (TCN). This contribution reports the design methodology that is followed, the firmware and software elements implemented, and the time-keeping performance obtained from the approach.

关键词： Protection field programmable gate arrays Linux Real-time systems Prevention and mitigation Accuracy Microprogramming Logic Protocols Plasmas CompactRIO (cRIO) hard real time precision time protocol (PTP)

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Efficient FPGA Implementation of Multi-Channel Pipelined Large FFT Architectures Based on SA-MDF Algorithm

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第5期72卷 2189-2201页

作者： Hu, Tang Hao, Chunling Wang, Xier Liu, Zhiwei Ren, Songnan Xu, Zhiwei Zhu, Shiqiang Zhejiang Univ Ocean Coll Zhoushan 316021 Peoples R China Zhejiang Lab Res Ctr Intelligent Chips & Devices Hangzhou 311121 Peoples R China

FPGA implementation of a multi-channel pipelined large FFT architecture is challenging due to its complex inter-channel data scheduling, high-throughput requirement, and resource-constrained hardware. By transforming to 2D-FFT implementation, investigating different binary tree schemes, and exploring various radices, butterflies, as well as data path structures, many hardware architectures have been designed to enhance single-channel large FFT or multi-channel medium-small size FFT performance. These designs fall short in addressing the demands of multi-channel pipelined and large FFT applications. In this article, a self-attention multipath delay feedback (SA-MDF) algorithm is proposed to analyze and identify the most critical bottleneck, then automatically pay attention to improve it, and finally generate the optimal FFT framework by exhaustively exploring the design space. The proposed algorithm alleviates the design difficulties and speeds up the FPGA implementation. Furthermore, an approximate roofline model and a novel binary tree scheme are introduced to further minimize the utilization of on-chip memory. A comprehensive comparison in terms of principles, implementation methods, and optimization effects is conducted when compared with other multi-channel FFT architectures. Experimental results show that the proposed FFT architectures are superior to other FFT implementations in terms of channel count, FFT length, high-throughput data arrangement, and adaptability to diverse hardware platforms.

关键词： Fast Fourier transforms Computer architecture field programmable gate arrays Throughput Binary trees System-on-chip Hardware Discrete Fourier transforms Delays SDRAM Binary tree fast Fourier transform (FFT) FPGA multipath delay feedback (MDF)

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White Gaussian Noise Generation With a Vacuum State Quantum Entropy Source Chip

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IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS 2025年第5期31卷

作者： Qiao, Guan-Ru Bai, Bing Weng, Zi-Xuan Wu, Jia-Ying Nie, You-Qi Zhang, Jun Univ Sci & Technol China Microscale & Sch Phys Sci Hefei Natl Res Ctr Phys Sci Hefei 230026 Peoples R China Univ Sci & Technol China CAS Ctr Excellence Quantum Informat & Quantum Phys Hefei 230026 Peoples R China Univ Sci & Technol China Hefei Natl Lab Hefei 230088 Peoples R China

White Gaussian noise (WGN) is widely used in communication system testing, physical modeling, Monte Carlo simulations, and electronic countermeasures. WGN generation relies heavily on random numbers. In this work, we present an implementation of WGN generation utilizing a quantum entropy source chip for the first time. A photonic integrated chip based on the vacuum state scheme generates quantum random numbers at a real-time output rate of up to 6.4 Gbps. A hardware-based inversion method converts uniform quantum random numbers into Gaussian random numbers using the inverse cumulative distribution function. Subsequently, the WGN signal is generated through a digital-to-analog converter and amplifiers. The WGN generator is characterized by a bandwidth of 230 MHz, a crest factor as high as 6.2, and an adjustable peak-to-peak range of 2.5 V. This work introduces a novel approach to WGN generation with information-theory provable quantum random numbers to enhance system security.

关键词： Elementary particle vacuum Noise field programmable gate arrays Entropy Photonics Gaussian noise Gaussian distribution Fluctuations Generators Transforms White Gaussian noise (WGN) quantum entropy source chip quantum random number generation vacuum state inversion method

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General-Purpose Data Streaming FPGA TDC Synchronized by SerDes-Based Clock Synchronization Technique

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 614-622页

作者： Honda, Ryotaro Ikeno, Masahiro Lin, Che-Sheng Shoji, Masayoshi High Energy Accelerator Res Org Inst Particle & Nucl Studies Tsukuba 3050801 Japan Osaka Univ Res Ctr Nucl Phys Osaka Ibaraki 5670047 Japan

This study proposes a clock synchronization protocol using the functionalities of IDELAYE2 and IOSERDESE2 primitives of an AMD Xilinx field-programmable gate array (FPGA) to serve as a general-purpose data-streaming type time-to-digital converter (TDC) for particle and nuclear physics experiments. A clock synchronization protocol called local area common clock protocol (LACCP) was developed as the upper layer protocol of a proprietary link (MIKUMARI), which was defined prior to this work by a community of users from the experimental physics field in Japan. Clock synchronization is realized using a round-trip time measurement with the system clock period and a fine offset time estimation, which corresponds to the clock signal phase difference between the primary and secondary FPGAs. The fine offset measurement is based on information from the IDELAYE2 and ISERDESE2 primitives utilized as the physical layer of the MIKUMARI link. No extra component is used. The LACCP can be implemented in an FPGA using general IO pin pairs for serial transmission and reception. A streaming high-resolution TDC (Str-HRTDC) was developed based on a tapped-delay-line (TDL) built from CARRY4 primitives in the AMD Xilinx Kintex-7 FPGA. It continuously measures the timing with 19.5-ps intrinsic resolution in sigma and provides unique timestamp information over 2.4 h by introducing the time frame structure defined and synchronized by LACCP. The clock synchronization accuracy and the timing resolution were evaluated by connecting four modules with optical fibers up to 100 m in length. No cable length dependence was confirmed. The obtained synchronization accuracy was approximately 300 ps. The timing resolution between two synchronized modules was 23.1 ps in sigma.

关键词： Clocks Synchronization field programmable gate arrays Protocols Delays Heart beat Data acquisition Logic Signal resolution Nuclear physics Clock synchronization field-programmable gate array (FPGA) serializer-deserializer (SerDes) streaming readout time-to-digital converter (TDC)

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