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Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters

IEEE ACCESS 2023年 11卷 4228-4241页

作者： Bieber, Levi Wang, Liwei Jatskevich, Juri Li, Wei Univ British Columbia Sch Engn Okanagan Campus Kelowna BC V1V 1V7 Canada Univ British Columbia Dept Elect & Comp Engn Vancouver BC V6T 1Z4 Canada OPAL RT Technol Montreal PQ H3K 1G6 Canada

Real-time simulation is important for ensuring the reliable operation of VSC-HVDC converters in power grids, particularly through the use of rapid control prototyping (RCP) and hardware-in-the-loop (HIL) based converter controllers. While real-time simulation is a common practice for modular multilevel converters (MMCs), it has been less frequently applied to the new class of hybrid cascaded multilevel converters (HCMCs). In this study, a universal equivalent model (UEM) is proposed for a range of HCMC topologies that combines accuracy and computational efficiency through the use of both CPUs and field-programmable gate arrays (FPGAs). The proposed UEM is derived using the hybrid five-level converter (H5LC), a compact, efficient, and fault-tolerant VSC within the HCMC family. The UEM relies on CPUs to simulate the main circuits and controls of the main converter, and utilizes FPGAs to calculate the instantaneous voltages of a large number of full-bridge submodules (FBSMs), flying capacitors, and DC-side pole capacitors. In addition, the FBSMs' voltage-balancing and switching algorithms are implemented on the FPGAs. The proposed real-time CPU/FPGA-based H5LC-UEM is compared to an offline CPU-based detailed equivalent model to verify its accuracy.

关键词： HVDC transmission Topology Multilevel converters Real-time systems Computational modeling Voltage control field programmable gate arrays High-voltage techniques FPGA hybrid multilevel converter modular multilevel converter (MMC) rapid control prototyping (RCP) real-time simulation voltage-source converter high voltage direct current (VSC-HVDC)

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Reconfigurable origami hologram based on deep neural networks

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OPTICS LETTERS 2024年第8期49卷 2041-2044页

作者： Wang, Kang Liao, Dashuang Wang, Haogang Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou 310027 Peoples R China Zhejiang Univ Inter Natl Joint Innovat Ctr Haining 314400 Peoples R China

Reconfigurable and multifunctional metasurfaces are becoming indispensable in a variety of applications due to their capability to execute diverse functions across various states. However, many of these metasurfaces incorporate complex active components, thereby escalating structural complexity and bulk volume. In this research, we propose a reconfigurable passive hologram based solely on an origami structure, enabling the successful generation of holograms depicting the 'Z' and 'L' illuminated by a right-hand circular polarization (RHCP) wave in two distinct states: planar and zigzag configuration, respectively. The transformation between the 2D planar metasurface and the 3D zigzag structure with slant angles of 35 is achieved solely through mechanically stretching and compressing the origami metasurface. The phases on the origami metasurface are trained through a deep neural network which operates on the NVIDIA Tesla k80 GPU, with the total training process costing 11.88 s after 100 epochs. The reconfigurable scheme proposed in this research provides flexibility and ease of implementation in the fields of imaging and data processing.

关键词： Circular polarization field programmable gate arrays Metasurfaces Neural networks Optical neural systems Stochastic gradient descent

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Comparative analysis of lithium niobate and barium titanate material platforms for implementing electro-optically tunable general-purpose photonic processors

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OPTICAL MATERIALS EXPRESS 2023年第11期13卷 3217-3231页

作者： Gaur, Tushar Mishra, Pragya Hegde, Gopalkrishna Talabattula, Srinivas Indian Inst Sci Dept Elect Commun Engn Bangalore 560012 Karnataka India Indian Inst Sci Dept Aerosp Engn Bangalore 560012 Karnataka India

The field of general-purpose photonic processors (GPPPs) has been gaining momentum as a promising area for reconfigurable integrated photonic hardware. Among various tuning mechanisms, the electro-optic tuning mechanism can enable the implementation of high-speed GPPPs with faster reconfiguration, larger bandwidth, and reduced dependence on high-performance blocks. Lithium niobate (LN) and barium titanate (BTO) are promising electro-optic platforms that enable electro-optically tunable GPPPs. However, the inherent anisotropy associated with the two materials and polarization domain formation in BTO makes the study and analysis of these effects on device performance essential, as GPPPs involve tunable devices in three different orientations, which must perform similarly. This article explores and comparatively analyzes the potential of using two material platforms to enable the implementation of high-speed GPPPs. Various applications implemented on LN and BTO GPPPs are also discussed and compared. Based on our results, a method to select the optimal device orientation for implementing a high-speed GPPP with all devices performing similarly in the two platforms has been proposed. The results indicate that both platforms have their own pros and cons, and the choice of platform depends on the application.

关键词： field programmable gate arrays Finite element method Lithium niobate Pockels effect Refractive index Thin films

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Towards Globally Optimal Design of Multipliers for FPGAs

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IEEE TRANSACTIONS ON COMPUTERS 2023年第5期72卷 1261-1273页

作者： Bottcher, Andreas Kumm, Martin Fulda Univ Appl Sci Appl Comp Sci Dept D-36037 Fulda Germany

The design of a multiplier typically consists of three steps: (1) partial product generation, (2) compressor tree design and (3) the selection of the final adder. Conventionally, these three steps are performed consecutively. However, when targeting FPGAs, there are many possibilities in all three design steps that heavily influence each other. This proposal presents for the first time a holistic optimization, combining all three optimization steps yielding a minimum amount of look-up-tables (LUTs) while it can also guarantee the minimal number of (pipeline) stages. An ILP-formulation for the determination of a combined, globally optimal solution for the multiplier tiling, compressor tree generation and final adder selection is proposed. With globally optimal we mean that the best solution is found for a given set of sub-multipliers for partial product generation, compressors and final *** allows to improve the quality and evaluate the limitations of existing heuristic 3-step approaches. It is shown experimentally for the example of Xilinx FPGAs, that globally optimal solutions can be obtained for multiplier sizes of practical relevance, leading to significant LUT reductions. Additional packing density experiments show that a significantly larger number of multiplier instances can be mapped to the same device.

关键词： Adders field programmable gate arrays Costs Table lookup Optimization Shape Proposals Compressor tree computer arithmetic FPGA integer linear programming multiplier multiplier tiling

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New Random PWM Method at Constant Switching Frequency and Maximum Harmonic Reduction Created With a Flexible FPGA-Based Test Bench

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IEEE ACCESS 2023年 11卷 19385-19394页

作者： Morales-Leal, Tomas Moreno-Munoz, Antonio Ortiz-Lopez, Manuel Agustin Geninatti, Sergio. R. Quiles-Latorre, Francisco Javier Univ Cordoba Dept Elect Engn & Automat Cordoba 14071 Spain Univ Cordoba Dept Elect & Comp Engn Cordoba 14071 Spain Univ Nacl Rosario Elect Dept RA-2000 Rosario Argentina

It has been shown that the converters that integrate random PWM produce a spread spectrum in their harmonic emission, shortening the emission peaks. On the converter's input side, the reduction minimizes electromagnetic interference EMI. On the output side of the converter, the reduction manages to smooth the voltage and current ripple in the load. We have built a flexible test bench (FTB) developed with FPGA to generate most of the proposed random PWM modes for converters. The conducted harmonic voltage emission of these modes, both on the input side of the converter and on the load side, has been measured and compared in a DC-DC Buck converter. FTB also has the ability to create new random PWM modes. Of the random modes, the ones that produce the greatest peak reductions are those with variable switching frequency. However, variable frequency modes lead to load feedback problems. A new random PWM method has been developed that significantly reduces the amplitude of the emission peaks but keeps the switching frequency constant.

关键词： Pulse width modulation Harmonic analysis Switching frequency Power harmonic filters field programmable gate arrays Switches Frequency modulation FPGA flexible test bench (FTB) random PWM at the constant switching frequency random PWM at a variable switching frequency

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Modular VNF Components Acceleration With FPGA Overlays

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IEEE TRANSACTIONS ON NETWORK AND SERVICE MANAGEMENT 2023年第1期20卷 846-857页

作者： Bachini Lopes, Filipe Schaeffer-Filho, Alberto E. Nazar, Gabriel Luca Univ Fed Rio Grande do Sul Inst Informat BR-91501970 Porto Alegre Brazil

Network Functions Virtualization (NFV) is a novel paradigm that aims to minimize operational and capital expenditures, by decoupling network functions from dedicated hardware and implementing them as Virtualized Network Functions (VNFs) instead. However, to fulfill such expectations, VNFs must be implemented efficiently, offering high performance and energy efficiency, which is not always feasible on General-Purpose Processors (GPPs). Thus, the use of reconfigurable accelerators, typically based on field-programmable gate arrays (FPGAs), has been proposed to offer higher efficiency whilst not forsaking the flexibility that is the core of the NFV paradigm. Not all VNFs or even VNF Components (VNFCs), however, are suitable for FPGA acceleration. This leads to new challenges related to identifying those VNFCs that should be deployed in FPGAs, maximizing the reuse of developed FPGA accelerators, and managing this heterogeneous infrastructure. To address these challenges, in this paper we present an enhanced design of VNFAccel, a platform to manage VNFCs in heterogeneous NFV infrastructures. We evaluate the performance and energy efficiency of the implemented functions in comparison to GPP-based solutions, showing that, when properly used, FPGAs can provide relevant benefits while maintaining the flexibility and reuse potential envisioned for NFV.

关键词： field programmable gate arrays Software Network function virtualization Guidelines Firewalls (computing) Table lookup Performance evaluation FPGA network function virtualization hardware acceleration

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Microring-based programmable coherent optical neural networks

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OPTICS EXPRESS 2023年第12期31卷 18871-18887页

作者： Wang, Jiahui Rodrigues, Sean P. Dede, Ercan M. Fan, Shanhui Stanford Univ Dept Appl Phys Stanford CA 94305 USA Toyota Res Inst North Amer Elect Res Dept 1555 Woodridge Ave Ann Arbor MI 48105 USA Stanford Univ Dept Elect Engn Ginzton Lab Stanford CA 94305 USA

Coherent programmable integrated photonics circuits have shown great potential as specialized hardware accelerators for deep learning tasks, which usually involve the use of linear matrix multiplication and nonlinear activation components. We design, simulate and train an optical neural network fully based on microring resonators, which shows advantages in terms of device footprint and energy efficiency. We use tunable coupled double ring structures as the interferometer components for the linear multiplication layers and modulated microring resonators as the reconfigurable nonlinear activation components. We then develop optimization algorithms to train the direct tuning parameters such as applied voltages based on the transfer matrix method and using automatic differentiation for all optical components. & COPY;2023 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement

关键词： field programmable gate arrays Integrated photonics Optical components Optical directional couplers Optical networks Optical neural systems

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An Efficient Gustavson-Based Sparse Matrix-Matrix Multiplication Accelerator on Embedded FPGAs

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2023年第12期42卷 4671-4680页

作者： Li, Shiqing Huai, Shuo Liu, Weichen Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore

Sparse matrix-matrix multiplication (SpMM) is an important kernel in multiple areas, e.g., data analytics and machine learning. Due to the low on-chip memory requirement, the consistent data format, and the simplified control logic, Gustavson's algorithm is a promising backbone algorithm for SpMM on hardware accelerators. However, the off-chip memory traffic still limits the performance of the algorithm, especially on embedded FPGAs. Previous researchers optimize Gustavson's algorithm targeting high bandwidth memory-based architectures and their solutions cannot be directly applied to embedded FPGAs with traditional DDRs. In this work, we propose an efficient Gustavson-based SpMM accelerator on embedded FPGAs. The proposed design fully considers the feature of off-chip memory access on embedded FPGAs and the dataflow of Gustavson's algorithm. First, we analyze the parallelism of the algorithm and propose to perform the algorithm with element-wise parallelism, which reduces the idle time of processing elements caused by synchronization. Further, we show a counter-intuitive example that the traditional cache leads to worse performance. Then, we propose a novel access pattern-aware cache scheme called SpCache, which provides quick responses to reduce bank conflicts caused by irregular memory accesses and combines streaming and caching to handle requests that access ordered elements of unpredictable length. Moreover, we propose to perform the merge on part of partial results, which removes some redundant merges in the naive implementation and has little postprocessing overhead. Finally, we conduct experiments on the Xilinx Zynq-UltraScale ZCU106 platform with a set of benchmarks from the SuiteSparse matrix collection. The experimental results show that the proposed design achieves an average 1.75x performance speedup compared to the baseline.

关键词： Sparse matrices Indexes field programmable gate arrays Parallel processing Machine learning algorithms System-on-chip Memory management Dataflow FPGA Gustavson sparse matrix-matrix multiplication (SpMM)

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Ultrahigh-density 3D holographic projection by scattering-assisted dynamic holography

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OPTICA 2023年第4期10卷 481-490页

作者： Yu, Panpan Liu, Yifan Wang, Ziqiang Liang, Jinyang Liu, Xingsi Li, Yinmei Qiu, Chengwei Gong, Lei Univ Sci & Technol China Dept Opt & Opt Engn Hefei 230026 Peoples R China Inst Natl Rech Sci Ctr Energie Materiaux Telecommun Lab Appl Computat Imaging Varennes PQ J3X1S2 Canada Natl Univ Singapore Dept Elect & Comp Engn Singapore City Singapore Univ Sci & Technol China Hefei Natl Lab Phys Sci Microscale Hefei 230026 Peoples R China

Computer-generated holography offers a promising route to three-dimensional (3D) video displays. To realize a realistic-looking 3D display, the critical challenge is to create a 3D hologram that enables high-density multi-plane projection with full depth control. However, two long-existing issues in current digital holographic techniques, low axial resolution and high inter-plane crosstalk, prevent fine depth control and therefore limit the ultimate quality. Here, we report 3D scattering-assisted dynamic holography (3D-SDH) that further breaks the depth-control limit of the state-of-the-art method. Our approach achieves orders of magnitude improvement in axial resolution and greatly suppresses crosstalk, enabling ultrahigh-density 3D holographic projection. Moreover, 3D-SDH enables dynamic 3D vectorial projections via phase-only holograms. The concept is validated through both simulations and experiments, where dynamic projections of 3D point-cloud objects onto high-density successive planes are demonstrated. Our work opens perspectives for 3D holographic technology with ultra-fine depth control, dynamic projection, and polarization multiplexing functionalities. (c) 2023 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement

关键词： Electrooptical devices field programmable gate arrays Holographic techniques Light sources Multiple scattering Scattering media

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Fast and Inexpensive High-Level Synthesis Design Space Exploration: Machine Learning to the Rescue

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2023年第11期42卷 3939-3950页

作者： Rashid, Md Imtiaz Schafer, Benjamin Carrion Univ Texas Dallas Dept Elect & Comp Engn Dallas TX 75080 USA

High-level synthesis (HLS) has multiple significant advantages over traditional RT-level design flows. One in particular that we address in this work is the ability to generate multiple functional equivalent design variants with unique tradeoffs, such as area, performance, and power from the same behavioral description. This is typically done by setting synthesis options in the form or pragmas (comments) to mainly control how to synthesize arrays (RAM or registers), loops (unroll, partially unroll, no unroll or pipeline), and functions (inline or not). Setting different pragma combinations lead to these different design implementations. Out of all the pragma combinations the designer is typically only interested in those that lead to the Pareto-optimal designs (PODs). Fortunately, this search can be automated, but unfortunately, the search space to find these pragma combinations grows supra-linearly with the number of pragma settings. Thus, fast and efficient heuristics are needed. These heuristics generate a new pragma combination and then evaluate their effect by synthesizing (HLS) it. The most time-consuming part of this process is having to execute a full synthesis (HLS) on the behavioral description for every new pragma combination. One obvious way to accelerate the exploration is to parallelize the exploration process using a multithreaded heuristic. The theoretical speedup should match the number of parallel threads. The main problem with this approach is that every HLS invokation requires to check out an HLS tool license. This license is not released until the synthesis process has finished. This implies that the maximum number of parallel threads is restricted by the number of available licenses, which in the ASIC case are extremely expensive. On the contrary, FPGA vendors make their HLS tools free. Thus, it is tempting to investigate if FPGA HLS tools can be used to find the PODs in the ASIC case. To address this, in this work we present a dedicated multit

关键词： field programmable gate arrays Behavioral sciences Transfer learning Predictive models Licenses Space exploration Metaheuristics ASIC design space exploration FPGA high-level synthesis (HLS) machine learning

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