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Dynamic Tsetlin Machine Accelerators for On-Chip Training Using FPGAs

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Mao, Gang Rahman, Tousif Maheshwari, Sidharth Pattison, Bob Shao, Zhuang Shafik, Rishad Yakovlev, Alex Newcastle Univ Sch Engn Microsyst Res Grp Newcastle Upon Tyne NE1 7RU England IIT Jammu Jammu 181221 Jammu & Kashmir India

The increased demand for data privacy and security in machine learning (ML) applications has put impetus on effective edge training on Internet-of-Things (IoT) nodes. Edge training aims to leverage speed, energy efficiency and adaptability within the resource constraints of the nodes. Deploying and training Deep Neural Networks (DNNs)-based models at the edge, although accurate, posit significant challenges from the back-propagation algorithm's complexity, bit precision trade-offs, and heterogeneity of DNN layers. This paper presents a Dynamic Tsetlin Machine (DTM) training accelerator as an alternative to DNN implementations. DTM utilizes logic-based on-chip inference with finite-state automata-driven learning within the same field programmable gate Array (FPGA) package. Underpinned on the Vanilla and Coalesced Tsetlin Machine algorithms, the dynamic aspect of the accelerator design allows for a run-time reconfiguration targeting different datasets, model architectures, and model sizes without resynthesis. This makes the DTM suitable for targeting multivariate sensor-based edge tasks. Compared to DNNs, DTM trains with fewer multiply-accumulates, devoid of derivative computation. It is a data-centric ML algorithm that learns by aligning Tsetlin automata with input data to form logical propositions enabling efficient Look-up-Table (LUT) mapping and frugal Block RAM usage in FPGA training implementations. The proposed accelerator offers 2.54x more Giga operations per second per Watt (GOP/s per W) and uses 6x less power than the next-best comparable design.

关键词： Training field programmable gate arrays Inference algorithms Heuristic algorithms Hardware Artificial neural networks Computer architecture Learning automata Computational modeling System-on-chip Edge training coalesced tsetlin machines dynamic tsetlin machines embedded FPGA machine learning accelerator on-chip learning logic-based-learning

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Design and Implementation of a New Wireless Time Synchronization Method Over IEEE 802.11

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IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS 2025年第6期21卷 5011-5021页

作者： Song, Jiahao Sun, Lei Ma, Zhangchao Wang, Jianquan Ying, Yunpeng Li, Jialin Huang, Rong Univ Sci & Technol Beijing Inst Ind Internet Sch Automat & Elect Engn Beijing 100083 Peoples R China China United Network Commun Corp Ltd Beijing 100033 Peoples R China

The demands for industrial ubiquitous communications promote the development of real-time and high-reliability wireless communication techniques. Accurate time synchronization is a critical foundation for deterministic communications. However, many wireless time synchronization methods achieve poor accuracy, while others take the high hardware costs and can not be used in practice. How to design high precision wireless time synchronization method with reasonable hardware costs is still a big challenge. Therefore, without affecting Wi-Fi protocol stack, a new medium access control (MAC) layer-based approach is proposed in this article to implement precision time synchronization with an open-source Wi-Fi design. The software protocol stack only needs to send handshake messages carrying identifiers, and timestamps are inserted and extracted from handshake messages as they pass through the MAC synchronization architecture designed in field programmable gate array. In the single-hop synchronization experiment, the synchronization accuracy is tested with and without network load. Comparing with other methods in several literatures, the results of the proposed solution unequivocally demonstrate the effectiveness and excellent wireless time synchronization precision, with 99% absolute time synchronization errors under 50% and 100% loads within 200 ns and 1 mu s, respectively.

关键词： Synchronization Wireless communication Protocols Clocks Wireless fidelity IEEE 802.11 Standard Hardware Accuracy field programmable gate arrays Media Access Control field programmable gate array (FPGA) IEEE 802.11 openwifi precision time synchronization wireless time synchronization

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A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets

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IEEE MICRO 2023年第2期43卷 110-119页

作者： Xin, Yao Li, Wenjun Xie, Gaogang Xu, Yang Wang, Yi Peng Cheng Lab Shenzhen 518055 Peoples R China Chinese Acad Sci CNIC Beijing 100083 Peoples R China Fudan Univ Shanghai 200433 Peoples R China Southern Univ Sci & Technol Shenzhen 518055 Peoples R China

As a programmable hardware, field-programmable gate array (FPGA) provides more opportunities for algorithmic network packet classification. Despite more than 10 years of research, the most actively investigated pipeline architectures still struggle to support fast rule search and efficient rule update for large-scale rule sets. In this article, we design and implement a novel architecture for multitree-based packet classification on FPGA, where the search and update processes are decoupled. A strategy of multi-processing elements (PEs), parallel search, and serial update is adopted. The parsing of multiple tree search results adopts a modular and hierarchical design, supporting architecture with various tree numbers. In addition, incremental rule updates can be achieved simply by traversing all PEs in one pass, with little and bounded impact on rule searching. Compared with TcbTree, the state-of-the-art updatable classifier, the experimental results on FPGA show that the classification performance of our design improves 3.4x on average for various 100k-scale rule sets.

关键词： Computer architecture field programmable gate arrays Classification algorithms Pipelines Throughput Random forests Hardware

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Ultrabroadband two-dimensional electronic spectroscopy in the pump-probe geometry using conventional optics

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OPTICS LETTERS 2024年第8期49卷 2065-2068页

作者： Barclay, Matthew S. Wright, Nicholas D. Cavanaugh, Paul Pensack, Ryan D. Martin, Eric W. Turner, Daniel B. Boise State Univ Micron Sch Mat Sci & Engn Boise ID 83725 USA MONSTR Sense Technol Ann Arbor MI 48108 USA

We report ultrabroadband two-dimensional electronic spectroscopy (2D ES) measurements obtained in the pump-probe geometry using conventional optics. A phasestabilized Michelson interferometer provides the pumppulse delay interval, tau 1 , necessary to obtain the excitationfrequency dimension. Spectral resolution of the probe beam provides the detection -frequency dimension, omega 3 . The interferometer incorporates active phase stabilization via a piezo stage and feedback from interference of a continuous -wave reference laser detected in quadrature. To demonstrate the method, we measured a well -characterized laser dye sample and obtained the known peak structure. The vibronic peaks are modulated as a function of the waiting time, tau 2 , by vibrational wave packets. The interferometer simplifies ultrabroadband 2D ES measurements and analysis. (c) 2024 Optica Publishing Group

关键词： Beam splitters field programmable gate arrays Laser beams Laser dyes Michelson interferometers Resolution

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EC-Crypto: Highly Efficient Area-Delay Optimized Elliptic Curve Cryptography Processor

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IEEE ACCESS 2023年 11卷 56649-56662页

作者： Javeed, Khalid El-Moursy, Ali Gregg, David Univ Sharjah Coll Comp & Informat Dept Comp Engn Sharjah U Arab Emirates Univ Dublin Trinity Coll Dublin Sch Comp Sci Dublin D02 PN40 Ireland

Elliptic Curve Cryptography (ECC) based security protocols require much shorter key space which makes ECC the most suitable option for resource-limited devices as compared to the other public key cryptography (PKC) schemes. This paper presents a highly efficient area-delay optimized ECC crypto processor over the general prime field ( F-p). It is structured on a new novel finite field multiplier (FFM) where several optimization techniques have been incorporated to shorten the latency and hardware resource consumption. The proposed FFM architecture is embedded with a finite field adder/subtractor (FFAS) unit which is utilized to perform FFAS operations instead of deploying a dedicated unit. The Common Z (Co-Z) coordinates with the Montgomery ladder method are used to compute point multiplication, a core operation in all ECC-based crypto protocols. The work also proposes an efficient scheduling strategy to execute low-level finite field arithmetic primitives with minimum latency on the employed finite field arithmetic units. Due to these techniques, the proposed ECC processor is optimized for hardware resources, latency, and throughput. It is captured in Verilog-HDL, synthesized, and implemented on Virtex-7, Kintex-7, and Virtex-6 FPGA platforms using Xilinx Vivado and ISE Design Suite tools. On the Virtex-7 FPGA platform, it computes a single 256-bit scalar multiplication primitive in 0.7ms, consumes just 6.2K slices, and delivers a throughput of 1428 operations per second. The implementation results show that it is a highly efficient design outperforming the state-of-the-art by providing a better area-delay product and higher efficiency. Therefore, it has the potential to be deployed in many applications where both latency and resource requirements are critical.

关键词： Galois fields Elliptic curve cryptography field programmable gate arrays Computer architecture Arithmetic Hardware acceleration Throughput Elliptic curve cryptography (ECC) finite field multiplication field programmable gate array (FPGA) hardware acceleration finite field arithmetic

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CocoSketch: High-Performance Sketch-Based Measurement Over Arbitrary Partial Key Query

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IEEE-ACM TRANSACTIONS ON NETWORKING 2023年第6期31卷 2653-2668页

作者： Miao, Ruijie Zhang, Yinda Zheng, Zihao Wang, Ruixin Zhang, Ruwen Yang, Tong Liu, Zaoxing Jiang, Junchen Peking Univ Sch Comp Sci Natl Key Lab Multimedia Informat Proc Beijing 100871 Peoples R China Univ Penn Dept Comp & Informat Sci Philadelphia PA 19104 USA Peng Cheng Lab Shenzhen 518055 Peoples R China Boston Univ Elect & Comp Engn Dept Boston MA 02215 USA Boston Univ Dept Comp Sci Boston MA 02215 USA Univ Chicago Dept Comp Sci Chicago IL 60637 USA

Sketch-based measurement has emerged as a promising solutions due to its high accuracy and resource efficiency. Prior sketches focus on measuring single flow keys and cannot support measurement on multiple keys. This work takes a significant step towards supporting arbitrary partial key queries, which aims to provide information for any key in the predefined range of possible flow keys. The designed system, casts arbitrary partial key queries to the subset sum estimation problem and makes the theoretical tools for subset sum estimation practical. utilizes two techniques: (1) stochastic variance minimization to significantly reduce per-packet update delay, and (2) removing circular dependencies in the per-packet update logic to make the implementation hardware-friendly. This paper extends the conference version by discussing how adapts to new measurement requirements, including: (1) collecting the exact information of specified flow keys, and (2) distributed measurement. is implemented on five popular platforms (CPU, Open vSwitch, Redis, P4, and FPGA). Experiment results show that compared to baselines that use traditional single-key sketches, improves average packet processing throughput by $27.2\times$ and accuracy by $10.4\times$ when measuring six flow keys.

关键词： Throughput Software measurement Hardware Task analysis Software Minimization field programmable gate arrays Sketch arbitrary partial key query P4 FPGA

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A Design Strategy to Improve Machine Learning Resiliency for Ring Oscillator Physically Unclonable Function

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IEEE ACCESS 2023年 11卷 34104-34118页

作者： Jiang, Yuqiu Hu, Yangpingqing Wang, Weizhong Univ Wisconsin Milwaukee Dept Elect Engn & Comp Sci Milwaukee WI 53211 USA

Physically unclonable functions (PUFs) are hardware security primitives that utilize non-reproducible manufacturing variations to provide device-specific challenge-response pairs (CRPs). Such primitives are desirable for applications such as communication and intellectual property protection. PUFs have been gaining considerable interest from both the academic and industrial communities because of their simplicity and stability. However, many recent studies have exposed PUFs to machine-learning (ML) modeling attacks. To improve the resilience of a system to general ML attacks instead of a specific ML technique, a common solution is to improve the complexity of the system. Structures, such as XOR-PUFs, can significantly increase the nonlinearity of PUFs to provide resilience against ML attacks. However, an increase in complexity often results in an increase in area and/or a decrease in reliability. This study proposes a lightweight ring oscillator (RO)-based PUFs using an additional modulus process to improve ML resiliency. The idea was to increase the complexity of the RO-PUF without significant hardware overhead by applying a modulus process to the outcomes from the RO frequency counter. We also present a thorough investigation of the design space to balance ML resiliency and other performance metrics such as reliability, uniqueness, and uniformity.

关键词： field programmable gate arrays Hardware Security Machine learning Modeling Authentication field programmable gate array hardware security identification and authentications machine learning modeling physical unclonable function

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A Survey on Adaptive Computing in Robotics: Modelling, Methods and Applications

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IEEE ACCESS 2023年 11卷 53830-53849页

作者： Podlubne, Ariel Goehringer, Diana Tech Univ Dresden TUD Chair Adapt Dynam Syst Ctr Tactile Internet Human Loop CeTI D-01062 Dresden Germany

Modern robots are complex heterogeneous systems composed of different Processing Elements (PEs) with multiple sensors and actuators. This implies that different experts are needed to build such systems. Traditionally, robots included Central Processing Units (CPUs) as their PE. However, this has been changing over the last decade as different PEs, namely Graphics Processing Units (GPUs) and field programmable gate arrays (FPGAs), have drawn the attention of roboticists. The research community focused on various techniques, methodologies, and applications separately, making integration aspects highly complex. Models, as abstractions, have been proposed to aid in designing complex systems that can also help with integration. Hence, three complementary goals are discussed in this work. The first is which robotic applications benefit from parallelizable and energy-efficient devices such as GPUs and FPGAs. The second one is to understand the contributions of different model-based approaches. Lastly, how these two can complement each other to bring benefits from one field onto the other so hardware developers, as well as roboticists, can improve the design of state-of-the-art robotic platforms.

关键词： Robots field programmable gate arrays Robot sensing systems Computational modeling Sensors Graphics processing units Modeling Model-driven engineering (MDE) robotics field programmable gate arrays (FPGAs) graphics processing units (GPUs)

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Frequency-domain adaptive MIMO filter with fractional oversampling using stochastic gradient descent for long-haul transmission over coupled 4-core fibers

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OPTICS EXPRESS 2023年第8期31卷 13104-13124页

作者： Arikawa, Manabu Hayashi, Kazunori NEC Corp Ltd Adv Network Res Labs 1753 ShimonumabeNakahara Ku Kawasaki 2118666 Japan Kyoto Univ Grad Sch Informat Sakyo Ku Yoshida Honmachi Kyoto 6068501 Japan

We propose a fractionally spaced frequency-domain adaptive multi-input multi-output (MIMO) filter architecture in which the sampling rate of input signals is below 2x oversampling with a non-integer oversampling factor for mode demultiplexing in long-haul transmission over coupled multi-core fibers. The frequency-domain sampling rate conversion to the symbol rate, i.e., 1x sampling, is placed after the fractionally spaced frequency-domain MIMO filter. The filter coefficients are adaptively controlled by stochastic gradient descent and gradient calculation with back propagation through the sampling rate conversion from the output signals on the basis of deep unfolding. We evaluated the proposed filter through a long-haul transmission experiment of 16-channel wavelength-division multiplexed and 4-core space-division multiplexed 32-Gbaud polarization-division-multiplexed quadrature phase shift keying signals over coupled 4-core fibers. The fractional oversampling frequency-domain adaptive 8x8 filter with 9/8x oversampling provided little performance penalty after 6240-km transmission compared to the conventional 2x oversampling frequency-domain adaptive 8x8 filter. The computational complexity in terms of the required number of complex-valued multiplications was reduced by 40.7%.

关键词： field programmable gate arrays Multicore fibers Optical signal to noise ratio Polarization mode dispersion Quadrature phase shift keying Stochastic gradient descent

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Efficient Implementation of Spontaneous Calcium Oscillations in the Central Nervous System on Reconfigurable Digital Boards

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第6期70卷 2478-2486页

作者： Zhang, Guodao Ge, Yisu Xu, Haojie Mayet, Abdulilah Mohammad Lu, Yanjie Ye, Mingtao Nazemi, Ehsan Hangzhou Dianzi Univ Dept Digital Media Technol Hangzhou 310018 Peoples R China Wenzhou Univ Coll Comp Sci & Artificial Intelligence Wenzhou 325100 Peoples R China State Grid Corp China Wencheng Elect Power Supply Co Wenzhou 325100 Peoples R China King Khalid Univ Elect Engn Dept Abha 61411 Saudi Arabia Univ Southampton Fac Engn & Phys Sci Southampton SO17 1BJ England Univ Antwerp Dept Phys Imec Vis Lab B-2610 Antwerp Belgium

Biological systems in case of real-time state and also large-scale simulation approach are interesting and challenge-based due to different aspects of nonlinear mathematical modeling that can describe the interactions of biological blocks. Thus, hardware circuit designing of these basic blocks in the Central Nervous System (CNS) can be an important field in case of achieving high performance neuromorphic system emulator. This paper presents a high-speed, low-cost, and efficient digital circuit for emulating the plausible calcium-dynamic-based model of astrocyte which has spontaneous oscillations. The nonlinear high-cost functions of the complex astrocyte model are reformulated using the power-2 based low-cost terms using optimized exhaustive search algorithm. Subsequently, the proposed model is simulated in case of validating the presented model and new optimized functions. Finally, the proposed model is physically realized in hardware case using Virtex 4 FPGA platform to test and validate final circuits. FPGA implementation results confirmed the ability of the design to emulate biological cell behaviours in detail with high accuracy. The proposed hardware consumes maximum 2% of the all resources of a Virtex 4 board. Additionally, timing analysis and synthesize report represent that the proposed model works in a high frequency of 371.56 MHz. Moreover, to validate the results of implementation, the proposed model is compared with the original model and other similar works in terms of accuracy, speed-up, and maximum number of implemented astrocyte.

关键词： Mathematical models Calcium Biological system modeling Integrated circuit modeling Hardware Oscillators field programmable gate arrays Spontaneous calcium system FPGA digital implementation astrocyte

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