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Resilient Embedded Systems Designs via on the Fly Generation of Adaptive Degenerate Components Using Machine Learning

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IEEE TRANSACTIONS ON COMPUTERS 2023年第5期72卷 1236-1246页

作者： Butts, Corey Jha, Rashmi Messay-Kebede, Temesguen Kapp, David Univ Cincinnati Dept Elect Engn & Comp Sci Cincinnati OH 45221 USA AFRL RYWA Resilient & Agile Avion Branch Dayton OH 45420 USA

Software defined radio (SDR) provides significant advantages over traditional analog radio systems and are becoming increasingly relied on for "mission critical" applications. This along with risk of trojans, single-event upsets and human error creates the necessity for fault tolerant systems. Redundancy has been traditionally used to implement fault tolerance but incurs a substantial area overhead which is undesirable in most applications. Advancements in field-programmable gate array and system on a chip technologies have made implementing machine learning (ML) algorithms within embedded systems feasible. In this paper we explore the use of ML to implement fault tolerance in an SDR. Our approach, which we call adaptive component-level degeneracy (ACD), uses a ML model to learn the functionality of an SDR component. Once trained, the model can detect when the component is compromised and mitigate the issue with its own output. We demonstrate the ability of our model to learn multiple simulated SDR components. We compare the one-dimensional convolutional neural network and bidirectional recurrent neural network architectures at modeling time series components. We also implement ACD within a real-time SDR system using GNU Radio Companion. The results show great potential for the utilization of ML techniques for improving embedded system reliability.

关键词： Embedded systems Integrated circuit reliability Hardware field programmable gate arrays Artificial neural networks Trojan horses Time series analysis Hardware reliability real-time and embedded systems machine learning redundant design signal processing systems

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TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-Based FPGAs

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IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING 2023年第2期11卷 404-419页

作者： Qiao, Weikang Guo, Licheng Fang, Zhenman Chang, Mau-Chung Frank Cong, Jason Univ Calif Los Angeles Dept Elect & Comp Engn Los Angeles CA 90025 USA Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90025 USA Simon Fraser Univ Sch Engn Sci Burnaby V5A 1S6 BC Canada

The emergence of high-bandwidth memory (HBM) brings new opportunities to boost the performance of sorting acceleration on FPGAs, which was conventionally bounded by the available off-chip memory bandwidth. However, it is nontrivial for designers to fully utilize this immense bandwidth. First, the existing sorter designs cannot be directly scaled at the increasing rate of available off-chip bandwidth, as the required on-chip resource usage grows at a much faster rate and would bound the sorting performance in turn. Second, designers need an in-depth understanding of HBM's characteristics to effectively utilize the HBM bandwidth. To tackle these challenges, we present TopSort, a novel two-phase sorting solution optimized for HBM-based FPGAs. In the first phase, 16 merge trees work in parallel to fully utilize 32 HBM channels' bandwidth. In the second phase, TopSort reuses the logic from phase one to form a wider merge tree to merge the partially sorted results from phase one. TopSort also adopts HBM-specific optimizations to reduce resource overhead and improve bandwidth utilization. TopSort can sort up to 4 GB data using all 32 HBM channels, with an overall sorting performance of 15.6 GB/s. TopSort is 6.7x and 2.7x faster than state-of-the-art CPU and FPGA sorters.

关键词： field programmable gate arrays Bandwidth Sorting Hardware Throughput System-on-chip Optimization merge sort hardware acceleration high-bandwidth memory memory-centric design FPGA floorplan

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Efficient Implementation of Spontaneous Calcium Oscillations in the Central Nervous System on Reconfigurable Digital Boards

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第6期70卷 2478-2486页

作者： Zhang, Guodao Ge, Yisu Xu, Haojie Mayet, Abdulilah Mohammad Lu, Yanjie Ye, Mingtao Nazemi, Ehsan Hangzhou Dianzi Univ Dept Digital Media Technol Hangzhou 310018 Peoples R China Wenzhou Univ Coll Comp Sci & Artificial Intelligence Wenzhou 325100 Peoples R China State Grid Corp China Wencheng Elect Power Supply Co Wenzhou 325100 Peoples R China King Khalid Univ Elect Engn Dept Abha 61411 Saudi Arabia Univ Southampton Fac Engn & Phys Sci Southampton SO17 1BJ England Univ Antwerp Dept Phys Imec Vis Lab B-2610 Antwerp Belgium

Biological systems in case of real-time state and also large-scale simulation approach are interesting and challenge-based due to different aspects of nonlinear mathematical modeling that can describe the interactions of biological blocks. Thus, hardware circuit designing of these basic blocks in the Central Nervous System (CNS) can be an important field in case of achieving high performance neuromorphic system emulator. This paper presents a high-speed, low-cost, and efficient digital circuit for emulating the plausible calcium-dynamic-based model of astrocyte which has spontaneous oscillations. The nonlinear high-cost functions of the complex astrocyte model are reformulated using the power-2 based low-cost terms using optimized exhaustive search algorithm. Subsequently, the proposed model is simulated in case of validating the presented model and new optimized functions. Finally, the proposed model is physically realized in hardware case using Virtex 4 FPGA platform to test and validate final circuits. FPGA implementation results confirmed the ability of the design to emulate biological cell behaviours in detail with high accuracy. The proposed hardware consumes maximum 2% of the all resources of a Virtex 4 board. Additionally, timing analysis and synthesize report represent that the proposed model works in a high frequency of 371.56 MHz. Moreover, to validate the results of implementation, the proposed model is compared with the original model and other similar works in terms of accuracy, speed-up, and maximum number of implemented astrocyte.

关键词： Mathematical models Calcium Biological system modeling Integrated circuit modeling Hardware Oscillators field programmable gate arrays Spontaneous calcium system FPGA digital implementation astrocyte

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A Novel programmable Stacked Patch Antenna With the Diversity of Sixteen Linear Polarizations and Four Frequency Bands

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IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION 2023年第1期71卷 1035-1040页

作者： Guo, Pan Zhong, Wenjie Chen, Shu-Lin Chen, Dingzhao Liu, Yanhui Univ Elect Sci & Technol China Sch Elect Sci & Engn Chengdu 611731 Peoples R China Xiamen Univ Inst Electromagnet & Acoust Xiamen 361005 Peoples R China Univ Technol Sydney UTS Global Big Data Technol Ctr GBDTC Ultimo NSW 2007 Australia

A highly multifunctional antenna with multilinear polarizations (MLPs) and multibands (MBs) is proposed, which can operate over four reconfigurable frequency bands, each band having 16 switchable linear polarizations (LPs) at an 11.25(?) interval. The larger number of MLPs is achieved by developing an odd-even switching strategy for the independently controlled p-i-n diodes placed between the inner patch and outer sector patches. The diode control is enabled by a field programmable gate array (FPGA) with an engineered biasing network. Moreover, the reported antenna can switch among four continuous bands for each LP, covering a combined range larger than 35%. It is an attractive feature, yet a challenging task for an antenna with such a large number of MLPs. This is realized by utilizing a double-layer feeding strategy with appropriate sector-patch activation, which is particularly appealed to such a highly multifunctional antenna. Furthermore, the antenna has a rotational symmetry along the azimuthal direction and, hence, all the LPs show almost rotationally invariant pattern shapes and gains. The measured results are consistent with the simulated ones, commonly validating the effectiveness of our design.

关键词： Antennas Substrates Switches Bandwidth PIN photodiodes Pins field programmable gate arrays Multiband (MB) multilinear polarization (MLP) reconfigurable antenna rotationally invariant

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FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology

IEEE DESIGN & TEST

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IEEE DESIGN & TEST 2023年第2期40卷 127-136页

作者： Zhang, Tao Rahman, Fahim Tehranipoor, Mark Farahmandi, Farimah Univ Florida Dept Elect & Comp Engn Gainesville FL USA Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA

Editor 's notes:field-programmable gate array (FPGA) bitstream reverse engineering and counterfeiting is a pertinent challenge in the modern hardware supply chain. To this end, this article proposes a blockchain-based technology to foster authenticity and integrity of the FPGA supply chain for trustworthy traceability. The proposed approach is transformative in being able to detect counterfeit FPGA chips and bitstreams using state-of-the-art blockchain technologies.-Kanad Basu, The University of Texas at Dallas

关键词： field programmable gate arrays Supply chains Blockchains Peer-to-peer computing Security Hardware Databases FPGA security blockchain trustworthy supply chain counterfeit detection

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DeepFire2: A Convolutional Spiking Neural Network Accelerator on FPGAs

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IEEE TRANSACTIONS ON COMPUTERS 2023年第10期72卷 2847-2857页

作者： Aung, Myat Thu Linn Gerlinghoff, Daniel Qu, Chuping Yang, Liwei Huang, Tian Goh, Rick Siow Mong Luo, Tao Wong, Weng-Fai ASTAR Inst High Performance Comp IHPC Singapore 138632 Singapore Natl Univ Singapore Sch Comp Singapore 117417 Singapore

Brain-inspired spiking neural networks (SNNs) replace the multiply-accumulate operations of traditional neural networks by integrate-and-fire neurons, with the goal of achieving greater energy efficiency. Specialized hardware implementations of those neurons clearly have advantages over general-purpose devices in terms of power and performance, but exhibit poor scalability when it comes to accelerating large neural networks. DeepFire2 introduces a hardware architecture which can map large network layers efficiently across multiple super logic regions in a multi-die FPGA. That gives more control over resource allocation and parallelism, benefiting both throughput and energy consumption. Avoiding the use of lookup tables to implement the AND operations of an SNN, prevents the layer size to be limited by logic resources. A deep pipeline does not only lead to an increased clock speed of up to 600 MHz. We double the throughput and power efficiency compared to our previous version of DeepFire, which equates to an almost 10-fold improvement over other previous implementations. Importantly, we are able to deploy a large ImageNet model, while maintaining a throughput of over 1500 frames per second.

关键词： Neurons field programmable gate arrays Hardware Throughput Computer architecture Kernel Biological neural networks field-programmable gate array (FPGA) spiking neural network hardware acceleration layer mapping

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FlowTune: End-to-End Automatic Logic Optimization Exploration via Domain-Specific Multiarmed Bandit

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2023年第6期42卷 1912-1925页

作者： Neto, Walter Lau Li, Yingjie Gaillardon, Pierre-Emmanuel Yu, Cunxi Synopsys Inc Silicon Realizat Grp Sunnyvale CA 94085 USA Univ Utah Dept Elect & Comp Engn Salt Lake City UT 84112 USA

Design flows are the explicit combinations of design transformations, primarily involved in synthesis, placement, and routing processes, to accomplish the design of integrated circuits (ICs) and system-on-chip (SoC). Mostly, the flows are developed based on the knowledge of the experts. However, due to the large search space of design flows and the increasing design complexity, developing intellectual property (IP)-specific synthesis flows providing high quality of result (QoR) is extremely challenging. In recent years, machine learning (ML) has been increasingly used in electronic design automation (EDA), with the goal of reducing manual labor and speeding up the design closure process in current toolflows. Existing techniques, on the other hand, either necessitate a huge amount of labeled data and time-consuming training, or are constrained in terms of practical EDA toolflow integration due to computational overhead. This article presents a generic end-to-end sequential decision making framework FlowTune for synthesis tooflow optimization, with a novel high-performance domain-specific, multistage multiarmed bandit (MAB) approach. This framework addresses a wide range of optimization problems on Boolean optimization problems, such as And-Inv-Graphs (AIGs), conjunction normal form (CNF) minimization (# clauses) for Boolean satisfiability;logic synthesis and technology mapping, and, more importantly, end-to-end post place-and-route (PnR) optimizations. Moreover, we demonstrate the high extensibility and generalizability of the proposed domain-specific MAB approach with end-to-end FPGA design flow, evaluated at post-routing stage, with two different FPGA backend tools (OpenFPGA and VPR) and two different logic synthesis representations [AIGs and Majority-Inv-Graph (MIG)]. FlowTune is fully integrated with ABC (Mishchenko et al., 2010), Yosys (Wolf, 2016), VTR (Luu et al., 2014), LSOracle (Neto et al., 2019), OpenFPGA (Tang et al., 2019), and industrial tools, and is r

关键词： Optimization field programmable gate arrays Upper bound Integrated circuit modeling Delays Tuning Solid modeling Circuit synthesis design automation machine learning

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A Method for Generating True Random Numbers With Multiple Distribution Characteristics

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IEEE ACCESS 2023年 11卷 81753-81762页

作者： Su, Gang Ding, Changchun Li, Sida Liu, Zijian Gao, Zheng Song, Junfeng Guo, Shuxu Tao, Min Jilin Univ Coll Elect Sci & Engn State Key Lab Integrated Optoelect Changchun 130012 Peoples R China Harbin Inst Technol HIT Sch Astronaut Harbin 150006 Peoples R China Peng Cheng Lab Shenzhen 518000 Peoples R China

In this paper, a method of generating true random numbers obeying multiple distribution characteristics is proposed. First, two resistance-capacitance (RC) self-excited oscillation circuits are used to generate two jittered, periodically unstable square wave signals, and then a text high-precision and high-frequency quartz crystal oscillator is used to sample and measure these two jittered signals to obtain their periods. Due to the randomness of the external environment, there is Gaussian white noise in the circuit, so the periods of these two signals are random variables subject to the Gaussian distribution. Finally, we use a text field-programmable gate array (FPGA) to perform secondary processing on these two random signals, which can generate true random number sequences that conform to the distribution characteristics of Gaussian distribution, Poisson distribution, 0-1 distribution, uniform distribution, etc. The random numbers generated by the circuit can be applied to the field of intelligent control related to automatic control and machine learning. This method uses a physical entropy source to generate high-quality true random sequences, which are easy to build, low in circuit cost, and small in size. The experimental results show that the method is low-cost, highly reliable and easy to integrate, providing an effective solution for the generation of true random numbers in electronic systems.

关键词： Generators Oscillators Clocks field programmable gate arrays Jitter Gaussian distribution Capacitors Random number generation Intelligent control True random number RC self-excited oscillation random distribution FPGA intelligent control

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CNN Sensor Analytics With Hybrid-Float6 Quantization on Low-Power Embedded FPGAs

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IEEE ACCESS 2023年 11卷 4852-4868页

作者： Nevarez, Yarib Beering, Andreas Najafi, Amir Najafi, Ardalan Yu, Wanli Chen, Yizhi Krieger, Karl-Ludwig Garcia-Ortiz, Alberto Univ Bremen Inst Electrodynam & Microelect D-28359 Bremen Germany KTH Royal Inst Technol Sch Elect Engn & Comp Sci S-10044 Stockholm Sweden KTH Royal Inst Technol Sch Elect Engn & Comp Sci Dept Elect Engn Div Elect & Embedded Syst Stockholm Sweden IBM Deutschland Dev & Res Boblingen Germany

The use of artificial intelligence (AI) in sensor analytics is entering a new era based on the use of ubiquitous embedded connected devices. This transformation requires the adoption of design techniques that reconcile accurate results with sustainable system architectures. As such, improving the efficiency of AI hardware engines as well as backward compatibility must be considered. In this paper, we present the Hybrid-Float6 (HF6) quantization and its dedicated hardware design. We propose an optimized multiply-accumulate (MAC) hardware by reducing the mantissa multiplication to a multiplexor-adder operation. We exploit the intrinsic error tolerance of neural networks to further reduce the hardware design with approximation. To preserve model accuracy, we present a quantization-aware training (QAT) method, which in some cases improves accuracy. We demonstrate this concept in 2D convolution layers. We present a lightweight tensor processor (TP) implementing a pipelined vector dot-product. For compatibility and portability, the 6-bit floating-point (FP) is wrapped in the standard FP format, which is automatically extracted by the proposed hardware. The hardware/software architecture is compatible with TensorFlow (TF) Lite. We evaluate the applicability of our approach with a CNN-regression model for anomaly localization in a structural health monitoring (SHM) application based on acoustic emission (AE). The embedded hardware/software framework is demonstrated on XC7Z007S as the smallest Zynq-7000 SoC. The proposed implementation achieves a peak power efficiency and run-time acceleration of 5.7 GFLOPS/s/W and 48.3x, respectively.

关键词： Hardware Quantization (signal) field programmable gate arrays Tensors Computational modeling Convolutional neural networks Computer architecture structural health monitoring hardware accelerator TensorFlow Lite embedded systems FPGA custom floating-point

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ROSETTA: A Resource and Energy-Efficient Inference Processor for Recurrent Neural Networks Based on programmable Data Formats and Fine Activation Pruning

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IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING 2023年第3期11卷 650-663页

作者： Kim, Jiho Kim, Tae-Hwan Korea Aerosp Univ Sch Elect & Informat Engn Goyang 10540 Gyeonggi Do South Korea

Recurrent neural networks (RNNs) are extensively employed to perform inference based on the temporal features of the input data. However, their computational workload and power consumption involved in inference are prohibitively high in practice, which may be problematic to achieve a high-speed inference in devices with tight limitations in the available silicon resources and power supply. This paper presents an efficient inference processor for RNNs, named ROSETTA. ROSETTA supports multiple data formats programmable for each vector operand to achieve a wide range or high precision with a limited data size. ROSETTA consistently performs every vector operation based on homogeneous processing units with a high utilization rate. Moreover, ROSETTA skips operations and reduces memory accesses to achieve high energy efficiency by pruning the activation elements in a fine-grained manner. Implemented in a low-cost 28 nm field-programmable gate array, ROSETTA exhibits a resource and energy efficiency as high as 2.51 - 1.14 MOP/s/LUT and 434.01 - 113.29 GOP/s/W, respectively, while producing near-floating-point inference results. The resource and energy efficiency of ROSETTA are higher than those of the previous processor implemented in the same device by up to 206.1% and 304.0%, respectively. The functionality has been verified for several RNN models of various types under a fully-integrated inference system.

关键词： Logic gates field programmable gate arrays Speech recognition Energy efficiency Convolutional neural networks Recurrent neural networks Integrated circuit modeling Accelerator field programmable gate array inference microarchitecture recurrent neural networks

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