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Evaluating Fault-Tolerant Techniques on COTS RISC-V NOEL-V Processor in Zynq UltraScale plus FPGA Under Proton Testing

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2023年第8期70卷 1708-1715页

作者： de Oliveira, Adria Barros Kastensmidt, Fernanda Lima Univ Fed Rio Grande do Sul Inst Informat INF Programa Posgrad Microeletron PGMICRO BR-91501970 Porto Alegre RS Brazil

This work evaluates different fault tolerance techniques on the RISC-V NOEL-V processor synthesized into the SRAM-based Zynq UltraScale+ field programmable gate array (FPGA) under proton testing. We investigate the effect of the cache size on the reliability of the processor and the use of scrubbing combined with triplication, duplication with comparison (DWC), and cache refreshing. The design area in SRAM-based FPGAs directly affects the soft error cross section. However, results show that increasing the L1 cache size and using the correct combination of mitigation techniques reduces the overall single event effect (SEE) susceptibility of the RISC-V NOEL-V processor.

关键词： field programmable gate arrays Fault tolerant systems Protons Process control Registers Random access memory Particle beams Commercial off-the-shelf (COTS) fault injection NOEL-V protons RISC-V single event effect (SEE) xilinx zynq ultrascale plus field programmable gate array (FPGA)

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Experimental Survey of FPGA-Based Monolithic Switches and a Novel Queue Balancer

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2023年第5期34卷 1621-1634页

作者： Papaphilippou, Philippos Sano, Kentaro Adhi, Boma Anantasatya Luk, Wayne Imperial Coll London Dept Comp London SW7 2BX England Huawei Technol R&D UK Ltd Cambridge CB4 0WG England RIKEN Ctr Computat Sci Kobe Hyogo 6500047 Japan

This article studies small to medium-sized monolithic switches for FPGA implementation and presents a novel switch design that achieves high algorithmic performance and FPGA implementation efficiency. Crossbar switches based on virtual output queues (VOQs) and variations have been rather popular for implementing switches on FPGAs, with applications in network switches, memory interconnects, network-on-chip (NoC) routers etc. The implementation efficiency of crossbar-based switches is well-documented on ASICs, though we show that their disadvantages can outweigh their advantages on FPGAs. One of the most important challenges in such input-queued switches is the requirement for iterative scheduling algorithms. In contrast to ASICs, this is more harmful on FPGAs, as the reduced operating frequency and narrower packets cannot "hide" multiple iterations of scheduling that are required to achieve a modest scheduling performance. Our proposed design uses an output-queued switch internally for simplifying scheduling, and a queue balancing technique to avoid queue fragmentation and reduce the need for memory-sharing VOQs. Its implementation approaches the scheduling performance of a state-of-the-art FPGA-based switch, while requiring considerably fewer resources.

关键词： field programmable gate arrays Scheduling Complexity theory Scheduling algorithms Integrated circuit interconnections Switches Hardware Crossbar FPGA Index Terms NoCs output-queued queue balancing scheduling algorithms switch virtual output queues

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The AMD 400-G Adaptive SmartNIC System on Chip: A Technology Preview

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IEEE MICRO 2023年第3期43卷 40-49页

作者： Dastidar, Jaideep Riddoch, David Moore, Jason Pope, Steven Wesselkamper, Jim AMD Adapt & Embedded Comp Grp San Jose CA 95124 USA AMD Network Architecture Team Cambridge England

This article presents the AMD 400-G Adaptive Smart Network Interface Card (SmartNIC) system on chip (SoC), a domain-specific architecture for offload acceleration of multitenant cloud network and storage applications. The article introduces the motivating factors behind SmartNIC and data processing unit accelerators in the datacenter. The article then describes how and why the adaptive SoC aims to strike a balance among software processing on embedded processors, fast-path application-specific integrated circuit-like processing on hardened logic, and adaptive and composable processing on an integrated field-programmable gate array. In architecting various subsystems of an SoC, the article describes how the device adapts to varying workloads over time through a dynamic function exchange of programmable logic (PL) and adapts to varying workloads over space by having different hardware execution pipelines executing alongside different PL binaries. The article also describes how security attestation and authentication, firewalls, and cryptographic acceleration permeate the device for a robust, multitenant confidential compute environment.

关键词： Software Computer architecture Servers Multiaccess communication field programmable gate arrays Product design Bandwidth

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Multi-Functional Resource-Constrained Elliptic Curve Cryptographic Processor

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IEEE ACCESS 2023年 11卷 4879-4894页

作者： Kieu-Do-Nguyen, Binh Pham-Quoc, Cuong Tran, Ngoc-Thinh Pham, Cong-Kha Hoang, Trong-Thuc Univ Electrocommun UEC Dept Comp & Network Engn Tokyo 1828585 Japan Ho Chi Minh City Univ Technol HCMUT VNU HCM Dept Comp Engn Ho Chi Minh City 740050 Vietnam

With the rising data evolution, the demand for secured communications over networks is rising immensely. Elliptic Curve Cryptography (ECC) provides an attractive solution to fulfill the requirements of modern network applications. Many proposals published over the year over different variants of ECC satisfied some of the issues. Nevertheless, modern network applications such as Internet-of-Thing (IoT) and Software-Defined Networking (SDN) put the requirements on various aspects and can only be solved by different ECC algorithms. Looking at this point of view, an efficient architecture that could combine multiple ECC algorithms becomes an urgent request. In addition, even though many investigations of ECC on field-programmable gate arrays (FPGA), an efficient architecture that could be well-deployed on Application-Specific Integrated Circuit (ASIC) needs to get more study. Therefore, this paper proposes an area-efficient ECC hardware design that could integrate multiple ECC algorithms. The proposed design is deployed on both ASIC and FPGA platforms. Four well-known ECC-based Digital Signature Algorithms (DSAs), which are the Edwards-curve Digital Signature Algorithm (EdDSA) with Curve25519, Elliptic Curve Digital Signature Algorithm (ECDSA) with National Institute of Standards and Technology (NIST) Curve P-256, P-384, and P-521, are implemented. Furthermore, the design supports all DSA schemes: public-key generation, signature generation, and verification. We also provide optimized calculation flows for modular multiplication, modular inversion, point addition, point doubling, and Elliptic Curve Point Multiplication (ECPM) for two different elliptic curves: the NIST curve and Edward curve, on a unique architecture. The calculation processes are designed in projective coordinates and optimized in time and space to achieve a high level of parallelism. The proposed ECC processor could run up to 102-MHz on ASIC 180-nm and 109.7-MHz on Xilinx Virtex-7. In terms of area, T

关键词： field programmable gate arrays Elliptic curve cryptography Elliptic curves NIST Digital signatures Cryptography Arithmetic ASIC cryptography processor elliptic curve FPGA

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Reducing the computational complexity of high-resolution hologram calculations using polynomial approximation

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OPTICS EXPRESS 2023年第11期31卷 18576-18586页

作者： Shiomi, Harutaka Shimobaba, Tomoyoshi Kakue, Takashi Ito, Tomoyoshi Chiba Univ Grad Sch Engn 1-33 Yayoi ChoInage Ku Chiba Chiba 2638522 Japan

In this paper, we have proposed a hologram calculation method using polynomial approximations for reducing the computational complexity of point-cloud-based hologram calculations. The computational complexity of existing point-cloud-based hologram calculations is proportional to the product of the number of point light sources and hologram resolution, whereas that of the proposed method can be reduced to approximately proportional to the sum of the number of point light sources and hologram resolution by approximating the object wave with polynomials. The computation time and reconstructed image quality were compared with those of the existing methods. The proposed method was approximately 10 times faster than the conventional acceleration method, and did not produce significant errors when the object was far from the hologram.

关键词： field programmable gate arrays Holographic displays Image quality Light sources Light wavelength Three dimensional imaging

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FCRoute: A Fast FPGA Connection Router Using Soft Routing-Space Pruning Algorithm

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2023年第3期42卷 887-899页

作者： Wang, Dekui Feng, Jun Zhou, Wei Hao, Xingxing Zhang, Xiaodan Northwest Univ Sch Informat Sci & Technol Xian 710127 Peoples R China

Routing is one of the most time-consuming stages in the field-programmable gate array (FPGA) design flow. Even if various attempts have been made to reduce route time, the existing work rarely focuses on improving the underlying A*-based FPGA connection router. In this article, we present a fast FPGA connection router called FCRoute based on a novel soft routing-space pruning algorithm. Within FCRoute, a routing resource priority mechanism is applied to classify the routing resource nodes into high-priority nodes and low-priority ones. On the whole, FCRoute is composed of fast maze search and backtracking process. During the fast maze search, we explore only the high-priority nodes in the routing space. In this way, a great deal of unnecessary work can be avoided. When the fast maze search fails to find the target sink, it allows the backtracking process to explore the low-priority nodes promising to be on the best path, after which a new fast maze search is called. By avoiding the exploration of the majority of low-priority nodes, FCRoute maintains runtime efficiency while ensuring global search ability. In addition, we further accelerate FCRoute with an engineering enhancement which simplifies the cost computations of nodes. Runtime and quality of results are compared with the state-of-the-art connection router in VPR 8. Experimental results show that on average FCRoute explores less than half the number of routing resource nodes, and therefore reduces runtime by 38% while enabling the quality of results. When combined with the enhancement, FCRoute achieves an average 45% reduction on runtime without sacrificing the quality of results.

关键词： Routing field programmable gate arrays Runtime Costs Backtracking Program processors Approximation algorithms field-programmable gate array (FPGA) routing routing algorithm shortest path soft pruning

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Serving Multi-DNN Workloads on FPGAs: A Coordinated Architecture, Scheduling, and Mapping Perspective

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IEEE TRANSACTIONS ON COMPUTERS 2023年第5期72卷 1314-1328页

作者： Zeng, Shulin Dai, Guohao Zhang, Niansong Yang, Xinhao Zhang, Haoyu Zhu, Zhenhua Yang, Huazhong Wang, Yu Tsinghua Univ Dept Elect Engn Beijing 100190 Peoples R China Shanghai Jiao Tong Univ Qing Yuan Res Inst Shanghai Peoples R China

Deep Neural Network (DNN) INFerence-as-a-Service (INFaaS) is the dominating workload in current data centers, for which FPGAs become promising hardware platforms because of their high flexibility and energy efficiency. The dynamic and multi-tenancy nature of INFaaS requires careful design in three aspects: multi-tenant architecture, multi-DNN scheduling, and multi-core mapping. These three factors are critical to the system latency and energy efficiency but are also challenging to optimize since they are tightly coupled and correlated. This paper proposes H3M, an automatic Design Space Exploration (DSE) framework to jointly optimize the architecture, scheduling, and mapping for serving INFaaS on cloud FPGAs. H3M explores: (1) the architecture design space with Heterogeneous spatial Multi-tenant sub-accelerators, (2) layer-wise scheduling for Heterogeneous Multi-DNN workloads, and (3) single-layer mapping to the Homogeneous Multi-core architecture. H3M beats state-of-the-art multi-tenant DNN accelerators, Planaria and Herald, by up to 7.5x and 3.6x in Energy-Delay-Product (EDP) reduction on the ASIC platform. On the Xilinx U200 and U280 FPGA platforms, H3M offers 2.1-5.7x and 1.8-9.0x EDP reduction over Herald.

关键词： Computer architecture field programmable gate arrays Dynamic scheduling Optimization Hardware Bandwidth Parallel processing Multi-tenancy deep neural network multi-core accelerator FPGA

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A CNN Inference Accelerator on FPGA With Compression and Layer-Chaining Techniques for Style Transfer Applications

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第4期70卷 1591-1604页

作者： Kim, Suchang Jang, Boseon Lee, Jaeyoung Bae, Hyungjoon Jang, Hyejung Park, In-Cheol Korea Adv Inst Sci & Technol KAIST Sch Elect Engn Daejeon 34141 South Korea

Recently, convolutional neural networks (CNNs) have actively been applied to computer vision applications such as style transfer that changes the style of a content image into that of a style image. As the style transfer CNNs are based on encoder-decoder network architecture and should deal with high-resolution images that become mainstream these days, the computational complexity and the feature map size are very large, preventing the CNNs from being implemented on an FPGA. This paper proposes a CNN inference accelerator for the style transfer applications, which employs network compression and layer-chaining techniques. The network compression technique is to make a style transfer CNN have low computational complexity and a small amount of parameters, and an efficient data compression method is proposed to reduce the feature map size. In addition, the layer-chaining technique is proposed to reduce the off-chip memory traffic and thus to increase the throughput at the cost of small hardware resources. In the proposed hardware architecture, a neural processing unit is designed by taking into account the proposed data compression and layer-chaining techniques. A prototype accelerator implemented on a FPGA board achieves a throughput comparable to the state-of-the-art accelerators developed for encoder-decoder CNNs.

关键词： field programmable gate arrays Convolutional neural networks Labeling Hardware Superresolution Convolution Throughput Convolutional neural network (CNN) style transfer application compression chaining neural processing unit (NPU) field programmable gate array (FPGA)

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A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第5期70卷 2003-2015页

作者： Gao, Zhen Xiao, Jiajun Liu, Qiang Ullah, Anees Reviriego, Pedro Tianjin Univ Sch Elect & Informat Engn Tianjin 300072 Peoples R China Tianjin Univ Sch Microelect Tianjin 300072 Peoples R China Univ Engn & Technol Dept Elect Engn Peshawar 220101 Abbottabad Pakistan Univ Politcn Madrid Dept Ingeneria Sistemas Telemticos Madrid 28040 Spain

Digital channelizers (DCs) based on the Discrete Fourier Transform (DFT) and polyphase filter banks are widely used in on-board processing (OBP) platforms to extract narrowband sub-channels from a wideband signal efficiently. In high-capacity communication satellite platforms there are always multiple DCs extracting narrowband signals from multiple wideband signals in parallel. field-programmable gate arrays (FPGAs) are a popular option for the implementation of DCs due to their parallel computing capabilities and good re-configurability, but FPGAs suffer single-event upsets (SEUs) on the space platform. This paper focuses on the efficient protection of parallel DCs with enhanced coding techniques. We first prove that a linear relationship between parallel DCs can be introduced and maintained among the multiple outputs. However, traditional coding schemes cannot be directly applied for the detection of faulty DCs due to the quantization noise introduced by fixed point implementations. To address this issue, we propose an enhanced coding scheme by averaging in the space and time domains to minimize the effect of quantization noise, introducing thresholds and a majority voter to further improve the detection probability. Both theoretical analysis and fault injection experiments prove the effectiveness of the proposed protection scheme. Experimental results show that all the SEUs that cause an SNR lower than 20dB can be detected and recovered, and the resource overheads are about 1.6 times and 1.3 times of that of the unprotected DCs for systems with 8 DCs and 16 DCs, respectively.

关键词： Filter banks Discrete Fourier transforms field programmable gate arrays Encoding Reliability Wideband Signal to noise ratio Digital channelizers fault tolerance design SRAM-FPGAs parallel processing single event upsets

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Time-Distributed Non-Convex Optimized Support Vector Machine for Vehicular Tracking Systems

IEEE CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING

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IEEE CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING 2023年第2期46卷 170-178页

作者： Selvakumar, R. Venkatalakshmi, K. Sri Venkateswara Inst Sci & Technol Dept Elect & Commun Engn Kolundhalur 631203 India Anna Univ Chennai Univ Dept Elect & Commun Engn Coll Engn Tindivanam Tindivanam 604001 India

This article presents a non-convex optimized support vector machine (NCVX OSVM) algorithm for active steering stability of vehicles on a curved road. Initially, we considered a curved road geometrics formulation and designed a time-distributed (TD) model for NCVX OSVM to compute the steering angle 0(?)- 180(?) at 10 m/s to follow active navigation at the highest curve entry speed. The proposed TD NCVX OSVM is interconnected with three modules. In the first module, formulated NCVX cost functions and Optimized SVM for smooth steering stability. The second module is based on improving faster training time (IFTT) by using the Naive Bayes probabilistic classifier (NBPC). The third module uses an optimized non-convex (NCVX) cost function to reduce the error phenomenon. The performance of these three modules is evaluated by several 100 data points from vehicle onboard sensors. Further, it is pre-processed in the curved road (start, continue, exit) conditions. The decisive of TD-NCVX OSVM design is demonstrated by using experimental learning on FPGA Zynq 7000 processor and programmed with python script. The empirical calculation shows an accuracy of 98.36%. Furthermore, the proposed design predicts an acceptable upper limit for curved steering whenever the vehicle turning speed is greater than 30 mi/h.

关键词： Roads Support vector machines field programmable gate arrays Navigation Hardware Wireless sensor networks Training Curved road Naive Bayes probability classifier (NBPC) non-convex (NCVX) optimization support vector machine time distributed (TD) vehicle steering control

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