Single event effect vulnerabilities of currently available commercial-off-the-shelf (COTS) field programmable gate arrays (FPGAs) have been measured. They are compared with those observed in older COTS devices as well...
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ISBN:
(纸本)0780393678
Single event effect vulnerabilities of currently available commercial-off-the-shelf (COTS) field programmable gate arrays (FPGAs) have been measured. They are compared with those observed in older COTS devices as well as with some radiation hardened devices.
The last decade has a rapid development in the structure of a programmable processor called fieldprogrammablegate Array (FPGA), which is used to implement a hardware circuit to perform the functions for high speed a...
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ISBN:
(纸本)9781467356138;9781467356121
The last decade has a rapid development in the structure of a programmable processor called fieldprogrammablegate Array (FPGA), which is used to implement a hardware circuit to perform the functions for high speed application. Sobel edge detection is a method to find the edge pixels in an image. This method exploits the change in intensity with respect to neighboring pixels. This paper introduces the implementation of Sobel edge detection method in the FPGA processor [1,2]. The implementation is performed based on two FPGA families from Xilinx, Spartan and Virtex. The cost of these implementations using Spartan3 is 41.66%, Spartan6 is 70%, Virtex5 is 3.69% and Virtex6 is 3.61%. The frequency is 169.188 MHz for using Spartan3, 45.7 MHz for Spartan6, 85.060 MHz for Virtex5 and 65.8 MHz for Virtex6.
The Fast Fourier Transform (FFT) is an important algorithm in the fields of science and engineering, where it is used in diverse areas such as communications, signal processing, instrumentation, image and video analys...
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ISBN:
(纸本)9781509012527
The Fast Fourier Transform (FFT) is an important algorithm in the fields of science and engineering, where it is used in diverse areas such as communications, signal processing, instrumentation, image and video analysis, etc. The algorithm is essentially a fast implementation of the Discrete Fourier Transform which allows it to reduce the asymptotic complexity of the latter from O(n(2)) to the former's O(n log n). In this paper, the radix-2 decimation in time FFT algorithm is implemented and investigated on field programmable gate arrays (FPGA) and Graphic Processing Units (GPU). The hardware descriptive language Verilog HDL (VHDL) is used for the FPGA, while the Open Computing Language (OpenCL) is used for the GPU. Both implementations are compared with various pre-installed IP-core modules of Xilinx and MATLAB for complex input of various sample sizes. From the results, it is concluded that the FPGA shows faster performance for a large number of FFT's of small sizes. On the other hand, the GPU is more promising for large number of FFT's of large sizes. The results also confirm that the FPGA based implementation is faster then the built-in IP-core modules of Xilinx. A hardware synthesis for FPGA is also provided.
In this paper, we study the incremental technology mapping problem for lookup-table (LUT) based field programmable gate arrays (FPGAs) under incremental changes. Given a gate-level network, a mapping solution associat...
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ISBN:
(纸本)0780363159
In this paper, we study the incremental technology mapping problem for lookup-table (LUT) based field programmable gate arrays (FPGAs) under incremental changes. Given a gate-level network, a mapping solution associated with it, and a sequence of changes to the original network, we compute a new mapping solution by modifying the existing one. Moreover, we assume that the given mapping solution is depth-optimal and we are required to come up with a modified mapping solution that maintains the depth optimality. The objective of our incremental mapper is to maintain depth-optimality with very high efficiency while minimizes the modifications to the existing mapping solution. We revealed a set of sufficient conditions for maintaining depth optimal mapping solution after a sequence of incremental changes. Based on these results, we developed a very fast incremental technology mapping algorithm, called IncFlow, that runs up to 300x faster than the well-known depth-optimal FlowMap algorithm [1](with an average of 14x speedup) while achieves the same depth-optimal mapping quality.
DSP based design approach for sinewave inverters are discussed in the past [1-5]. However, due to generalized hardware in DSP chips, implementation of a control block of a sinewave inverter for precise RMS control and...
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ISBN:
(纸本)0780378857
DSP based design approach for sinewave inverters are discussed in the past [1-5]. However, due to generalized hardware in DSP chips, implementation of a control block of a sinewave inverter for precise RMS control and Total Harmonic Distortion (THD) minimization may not be hardware efficient. As an alternative, special look-up table based FPGA approach for THD control is discussed in the paper, where no higher order harmonies are calculated individually.
This paper establishes a handshake between the fields of "parallel genetic algorithms" and reconfigurable systems, to provide a solution for the routing problem for FPGAs, that attempts to enhance the perfor...
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ISBN:
(纸本)0780375742
This paper establishes a handshake between the fields of "parallel genetic algorithms" and reconfigurable systems, to provide a solution for the routing problem for FPGAs, that attempts to enhance the performance of the circuit implemented by the FPGA. We propose to solve the problem of routing for FPGAs in three phases, out of which the first two utilize the concept of genetic algorithms to transform an initial population of random suggested routings to a population that contains solutions approximating the optimal one.
Historically, whenever a unique digital interface was needed, a unique piece of hardware was created. In lite field of Loaders/Verifiers this has often led to large, heavy, and expensive equipment to support aircraft ...
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ISBN:
(纸本)0780378377
Historically, whenever a unique digital interface was needed, a unique piece of hardware was created. In lite field of Loaders/Verifiers this has often led to large, heavy, and expensive equipment to support aircraft platforms. field programmable gate arrays (FPGAs) can be used to create many different interfaces without the need for unique hardware. This paper will explore the techniques used to develop interfaces using FPGAs and provide examples of how FPGAs have reduced the size, weight, and cost of flight line test equipment over the last nine years. FPGAs may also be used to implement some standard interfaces such as IEEE-488, RS-422 and PC parallel ports. The benefits and risks of using FPGAs for these standard interfaces are evaluated.
The semiconductor industry has adopted a horizontal business model wherein one company designs the Integrated Circuits (ICs), a second company fabricates them and a third one tests and packages them. Separating design...
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ISBN:
(纸本)9781538622544
The semiconductor industry has adopted a horizontal business model wherein one company designs the Integrated Circuits (ICs), a second company fabricates them and a third one tests and packages them. Separating design from fabrication introduces vulnerabilities in the IC supply chain. An offshore semiconductor foundry can overproduce FPGAs, and a malicious distributor can reinsert old, recycled and counterfeit FPGAs into the supply chain. We present an approach to fingerprint FPGAs by leveraging process variations and spatial correlations. We confirmed FPGA fingerprinting on 56 Xilinx Artix-7 FPGAs.
This paper shows research into the development of techniques that can be used to recover what was written oil a paper document after attempts have been made to obscure the content via methods such as burning or bleach...
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ISBN:
(纸本)9780819471697
This paper shows research into the development of techniques that can be used to recover what was written oil a paper document after attempts have been made to obscure the content via methods such as burning or bleach for example. Here instead of using expensive high-tech imagery and infrared equipment, there is the aim of using off-the-shelf equipment to reduce economic costs in the form of a Sony Ericsson Mobile Phone with a 2.0 mega pixel camera with built in light. The latter was used in the data collection phase after the test documents were produced, various factors were considered here such as light reflection and incident angles on the paper, position of camera, light frequencies, visible light collection and night mode light collection in order to achieve the optimum test image. The FPGA was then brought in for the post-collection processing of the images using techniques currently developed using graphical block methodologies for ease of use, then the best string of operations to obtain the most efficient results of what was previously written will be presented by comparing it to a similar untouched document. The paper then explains the expansions to the experiments which include different types and coloured inks from various sources which include standard pens to inkjet printer cartridges on numerously coloured paper to see how truly effect the developed technique is.
In this paper, we present some of the important design factors and performance issues in the development of field programmable gate arrays (FPGAs). Emphasis is placed on the design of logic blocks and interconnection ...
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ISBN:
(纸本)0780366433
In this paper, we present some of the important design factors and performance issues in the development of field programmable gate arrays (FPGAs). Emphasis is placed on the design of logic blocks and interconnection resources. We also discuss the possibility of using multiple-valued logic in the design of FPGA logic blocks.
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