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An Efficient Multi-Secret Image Sharing System Based on Chinese Remainder Theorem and Its FPGA Realization

IEEE ACCESS 2023年 11卷 9511-9520页

作者： Sharobim, Bishoy K. Fetteha, Marwan A. Abd-El-Hafiz, Salwa K. Sayed, Wafaa S. Said, Lobna A. Radwan, Ahmed G. Nile Univ Nanoelect Integrated Syst Ctr NISC Giza 12588 Egypt Cairo Univ Fac Engn Engn Math Dept Giza 12613 Egypt Nile Univ Sch Engn & Appl Sci Giza 12588 Egypt

Multi-Secret Image Sharing (MSIS) is important in information security when multiple images are shared in an unintelligible form to different participants, where the images can only be recovered using the shares from participants. This paper proposes a simple and efficient (n, n)-MSIS system for colored images based on XOR and Chinese Remainder Theorem (CRT), where all the n share are required in the recovery. The system improves the security by adding dependency on the input images to be robust against differential attacks, and by using several delay units. It works with even and odd number of inputs, and has a long sensitive system key design for the CRT. Security analysis and a comparison with related literature are introduced with good results including statistical tests, differential attack measures, and key sensitivity tests as well as performance analysis tests such as time and space complexity. In addition, field programmable gate Array (FPGA) realization of the proposed system is presented with throughput 530 Mbits/sec. Finally, the proposed MSIS system is validated through software and hardware with all statistical analyses and proper hardware resources with low power consumption, high throughput and high level of security.

关键词： Security field programmable gate arrays Cryptography Information security Encryption Image processing Information sharing System recovery Image color analysis Chinese remainder theorem field programmable gate array multi-secret image sharing secret sharing

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A Unified Multibit PUF and TRNG Based on Ring Oscillators for Secure IoT Devices

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IEEE INTERNET OF THINGS JOURNAL 2023年第7期10卷 6182-6192页

作者： Baturone, Iluminada Roman, Roberto Corbacho, Angel Univ Seville Inst Microelect Sevilla CSIC Seville 41092 Spain

Physically unclonable functions (PUFs) and true random number generators (TRNGs) are cryptographic primitives very well suited for secure IoT devices. This article proposes a circuit, named multibit-RO-PUF-TRNG, which offers the advantages of unifying PUF and TRNG in the same design. It is based on counting the oscillations of pairs of ring oscillators (ROs), one of them acting as a reference. Once the counter of the reference oscillator reaches a fixed value, the count value of the other RO is employed to provide the TRNG and the multibit PUF response. A mathematical model is presented that supports not only the circuit foundations but also a novel and simple calibration procedure that allows optimizing the selection of the design parameters. Experimental results are illustrated with large data sets from two families of FPGAs with different process nodes (90 and 28 nm). These results confirm that the proposed calibration provides TRNG and PUF responses with high quality. The raw TRNG bits do not need post-processing and the PUF bits (even 6 bits per RO) show very small aliasing. In the application context of obfuscating and reconstructing secrets generated by the TRNG, the multibit PUF response, together with the proposal of using error-correcting codes and RO selection adapted to each bit, provide savings of at least 79.38% of the ROs compared to using a unibit PUF without RO selection. The proposal has been implemented as an APB peripheral of a VexRiscv RV32I core to illustrate its use in a secure FPGA-based IoT device.

关键词： Internet of Things Proposals field programmable gate arrays Cryptography Ring oscillators Reliability Mathematical models Hardware security physical unclonable functions ring oscillators (ROs) true random number generators (TRNGs)

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FPGA Implementation of Variable Step Power Inversion Array for BeiDou Receiver

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IEEE ACCESS 2023年 11卷 109390-109396页

作者： Jia, Zhuoya Ni, Shuyan Luo, Yalun Zhang Mao, Wenxuan Sci & Technol Complex Elect Syst Simulat Lab Beijing 101416 Peoples R China Space Engn Univ Dept Elect & Opt Engn Beijing 101416 Peoples R China

Given the susceptibility of satellite signals to intentional or unintentional interference;it is imperative to incorporate hardware-based navigation anti-jamming algorithms. Currently, spatial domain filtering is widely applied. While numerous variable step size (VSS) algorithms were used to improve the performance, most of these are either computationally complex or depend on many parameters that are hard to tune manually. Some algorithms might improve one index but worsen overall performance, making them unreliable in practical scenarios. To address these challenges, we propose a novel variable step power inversion (PI) that involves just one adaptive parameter. By establishing a new non-linear function model between step size and system output, the parameter can be adapted based on the output. Meanwhile, a variable step PI that can be easily implemented by field programmable gate array (FPGA) is proposed, thereby achieving a balance between accuracy and iteration speed. The proposed algorithm can converge within 10 iterations, effectively suppressing individual interference below -300dB. In comparison to existing algorithms, the proposed algorithm is characterized by swift convergence, high convergence accuracy, low complexity, and robust anti-jamming capabilities. Finally, FPGA hardware testing is conducted, and the experimental and simulation results are in good agreement, affirming anti-jamming capabilities.

关键词： Convergence Interference field programmable gate arrays Steady-state Satellites Hardware Heuristic algorithms Navigation Power inversion array variable step size (VSS) navigation anti-jamming FPGA

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A Fast FPGA Connection Router Using Prerouting-Based Parallel Local Routing Algorithm

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2023年第11期42卷 3868-3880页

作者： Wang, Dekui Feng, Jun Liu, Ke Zhou, Wei Hao, Xingxing Zhang, Xiaodan Northwest Univ Sch Informat Sci & Technol Xian 710127 Peoples R China

Routing is one of the most time-consuming steps in the field-programmable gate array (FPGA) design process. Even if unceasing efforts have been made to accelerate FPGA routing, the existing work seldom pays attention to the underlying FPGA connection router. In this article, we present a fast FPGA connection router called PRoute which implements a novel prerouting-based parallel local routing algorithm. Basically, PRoute precomputes the potential routing solutions for various connection patterns on FPGAs, which can be directly used in the later practical routing. On the whole, PRoute is composed of A-star maze expansion and parallel local search. In the first part, PRoute gradually expands the maze wavefront toward the lowest-cost node to search for the target sink. For a wire-type node, PRoute invokes a fast parallel local search instead taking advantage of the prerouting results, and hence the time-expensive maze expansion can be reduced. Particularly, it allows PRoute to call one another between A-star maze expansion and parallel local search. This enables the runtime efficiency of PRoute while ensuring its global search ability. In addition, we put forward an engineering improvement to further speed up PRoute by avoiding the exploration of block output pins. To our best knowledge, this work is the first to apply the idea of prerouting for FPGAs. Experimental results show that PRoute achieves speedups of 1.8x, 2.4x, 3.2x, 4.1x, and 5.1x with 1, 4, 8, 16, and 32 threads relative to the baseline versatile place to route's connection router, respectively, without degrading the quality of results.

关键词： field programmable gate arrays Routing Runtime Pins Costs Wires Delays field-programmable gate arrays (FPGA) routing prerouting routing algorithm shortest path

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Compact and low-cost deep-ultraviolet microscope system for label-free molecular imaging and point-of-care hematological analysis

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BIOMEDICAL OPTICS EXPRESS 2023年第3期14卷 1245-1255页

作者： Gorti, Viswanath Kaza, Nischita Williams, Evelyn Kendall Lam, Wilbur A. Robles, Francisco E. Georgia Inst Technol Wallace H Coulter Dept Biomed Engn Atlanta GA 30332 USA Emory Univ Atlanta GA 30322 USA Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30322 USA Emory Univ Aflac Canc & Blood Disorders Ctr Childrens Healthc Sch Med Atlanta GA USA Emory Univ Sch Med Dept Pediat Atlanta GA 30322 USA

Deep-ultraviolet (UV) microscopy enables label-free, high-resolution, quantitative molecular imaging and enables unique applications in biomedicine, including the potential for fast hematological analysis at the point-of-care. UV microscopy has been shown to quantify hemoglobin content and white blood cells (five-part differential), providing a simple alternative to the current gold standard, the hematological analyzer. Previously, however, the UV system comprised a bulky broadband laser-driven plasma light source along with a large and expensive camera and 3D translation stage. Here, we present a modified deep-UV microscope system with a compact footprint and low-cost components. We detail the novel design with simple, inexpensive optics and hardware to enable fast and accurate automated imaging. We characterize the system, including a modified low-cost web-camera and custom automated 3D translation stage, and demonstrate its ability to scan and capture large area images. We further demonstrate the capability of the system by imaging and analyzing blood smears, using previously trained networks for automatic segmentation, classification (including 5-part white blood cell differential), and colorization. The developed system is approximately 10 times less expensive than previous configurations and can serve as a point-of-care hematology analyzer, as well as be applied broadly in biomedicine as a simple compact, low-cost, quantitative molecular imaging system.

关键词： Deep learning field programmable gate arrays Imaging systems Phase imaging Raman microscopy Real time imaging

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An FPGA-Based General-Purpose Feature Detection Algorithm for Space Applications

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IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS 2023年第1期59卷 98-108页

作者： Liu, Yunjie Wu, Xiaofeng Univ Sydney Camperdown NSW Australia Univ Sydney Sch Aerosp Mech & Mechatron Engn Camperdown NSW 2006 Australia

Spacecraft takes images for applications/missions like attitude determination, astronomy, and space situational awareness. Feature detection is a primary operation in vision-based processing systems. Although different feature detection algorithms are used for specific purposes, they need to achieve invariance by scaling, rotation, and other interference, and output robust results. This article develops a general-purpose feature detection hardware architecture based on the speeded-up robust features (SURF) algorithm. On the other hand, the efficiency of the algorithm can affect the overall system performance to a large extent, especially in real-time operations. This article presents an field-programmable gate array (FPGA)-based implementation of a modified SURF algorithm. The advantages of FPGAs including parallel and pipelining, fixed-point arithmetic, and bitwise operations are fully applied to improve the performance and efficiency of the system in terms of power consumption, and resource utilization.

关键词： Feature extraction Stars Feature detection field programmable gate arrays Hardware Satellites Approximation algorithms field-programmable gate array (FPGA) feature detection fixed-point arithmetic parallel pipelining speeded-up robust features (SURF)

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HE-Booster: An Efficient Polynomial Arithmetic Acceleration on GPUs for Fully Homomorphic Encryption

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2023年第4期34卷 1067-1081页

作者： Wang, Zhiwei Li, Peinan Hou, Rui Li, Zhihao Cao, Jiangfeng Wang, XiaoFeng Meng, Dan Chinese Acad Sci Inst Informat Engn State Key Lab Informat Secur Beijing 100093 Peoples R China Univ Chinese Acad Sci Sch Cyber Secur Beijing 101408 Peoples R China Indiana Univ Bloomington Bloomington IN 47405 USA

Fully Homomorphic Encryption (FHE) enables secure offloading of computations to untrusted cloud servers as it allows computing on encrypted data. However, existing well-known FHE schemes suffer from heavy performance overheads. Thus numerous accelerations based on FPGAs, ASICs, and GPUs have been proposed. Compared to FPGAs and ASICs, GPUs have obvious advantages in productivity and development costs. And also, GPUs have already been widely deployed in commercial cloud or supercomputing centers. Therefore, we present HE-Booster, an efficient GPU-based FHE acceleration design. For single-GPU acceleration, a thorough systematic design is exploited to map five common phases in typical FHE schemes to the GPU parallel architecture. In particular, inspired by the regular architecture of NTT/INTT, a novel inter-thread local synchronization is proposed to exploit thread-level parallelism. For multi-GPU acceleration, we propose a scalable parallelization design that exploits data-level parallelism through fine-grained data partition under different representations. Finally, experiments on 1 NVIDIA GPU demonstrate that our work outperforms 251.7x, 78.5x and 164.9x than three mainstream CPU-based libraries HElib, SEAL, and PALISADE, and up to 170.5x speedup is obtained compared to the GPU-accelerated library cuHE. What's more, performing 8 homomorphic multiplications on 8 GPUs can deliver up to a 7.66x performance boost compared to a single-GPU implementation.

关键词： Graphics processing units Arithmetic Cathode ray tubes Synchronization Libraries Instruction sets field programmable gate arrays Fully homomorphic encryption GPU acceleration number-theoretic transform

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Floating Point Calculation of the Cube Function on FPGAs

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2023年第1期34卷 372-382页

作者： Osorio, Roberto R. Univ A Coruna CITIC Comp Architecture Grp Coruna 15071 Spain

Specialized arithmetic units allow fast and efficient computation of lesser used mathematical functions. The overall impact of those units would be negligible in a general purpose processor, as added circuitry makes chips more complex despite most software would seldom make use of it. On the opposite side, custom computing machines are built for a specific task, and they can always benefit from specialized units if they are available. In this work, floating point architectures are proposed for computing the cube on Intel and Xilinx FPGAs. Those implementations reduce the cost and latency compared to using simple floating point multiplications and squarers.

关键词： field programmable gate arrays Computer architecture Complexity theory Mathematical models Arithmetic Pipeline processing Costs Floating-point arithmetic numerical analysis field programmable gate arrays digital integrated circuits

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A Study on Electromagnetic Scattering Characteristics of 4-D Antenna arrays

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IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION 2023年第1期71卷 275-287页

作者： Li, Zihao Xie, Chunmao Yang, Feng Chen, Yikai Qu, Shi-Wei Hu, Jun Yang, Shiwen Univ Elect Sci & Technol China UESTC Sch Elect Sci & Engn Chengdu 611731 Peoples R China Southwest China Inst Elect Technol Chengdu 610036 Peoples R China

A theoretical study on electromagnetic scattering mechanism of 4-D antenna arrays is performed for the first time. First, the scattering fields of one antenna element within an infinite 4-D array are derived under periodic boundary conditions. In order to estimate the scattering performances of 4-D antenna arrays, numerical models of the scattering fields are then established based on the traditional scattering pattern multiplication theory. Moreover, an effective time-domain full-wave approach is proposed for the scattering cross section (SCS) simulation of 4-D arrays. Finally, to verify the feasibility for SCS reduction through 4-D arrays, the differential evolution (DE) algorithm is adopted to synthesize a 14-element microstrip patch antenna array for the optimization of radiation and scattering performances. Numerical results show that 4-D arrays are capable of scattering the incident waves in both space domain and frequency domain simultaneously, thus accomplishing remarkable in-band SCS reduction.

关键词： Antenna arrays Electromagnetic scattering Phased arrays Microstrip antenna arrays Finite element analysis field programmable gate arrays Amplitude modulation 4-D antenna arrays electromagnetic scattering time modulation

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FlexKA: A Flexible Karatsuba Multiplier Hardware Architecture for Variable-Sized Large Integers

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IEEE ACCESS 2023年 11卷 55212-55222页

作者： Kang, Byeongmin Cho, Hyungmin Sungkyunkwan Univ Dept Comp Sci & Engn Suwon 16419 South Korea

The Karatsuba algorithm is an effective way to accelerate large integer multiplications through recursive function calls. However, existing hardware implementations of Karatsuba multipliers are limited to fixed operand sizes. To enable their application in diverse domains, including homomorphic encryption with varying multiplicative depths, it is necessary to support variable operand sizes. In this paper, we propose a novel Karatsuba multiplier design, named FlexKA, which supports variable operand sizes through a state machine that manages the dynamic call states of the operation. We evaluate FlexKA on the Xilinx ZynqMP FPGA and demonstrate that it supports variable operand sizes up to 256K bits, achieving a 9.2x speedup compared to a highly-optimized software library running on a CPU. Our results show that FlexKA is an efficient and effective solution for large integer multiplications with flexible operand sizes in hardware.

关键词： Hardware Signal processing algorithms Algorithms Software algorithms Memory modules Software Memory management Multiplying circuits field programmable gate arrays

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