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Insights From Bugs in FPGA High-Level Synthesis Tools: An Empirical Study of Bambu Bugs

IEEE TRANSACTIONS ON RELIABILITY 2025年

作者： Wang, Zun Jiang, He Li, Xiaochen Guo, Shikai Zhao, Xu Zhang, Yi Dalian Univ Technol Sch Software Dalian 116024 Peoples R China Key Lab Ubiquitous Network & Serv Software Liaonin Dalian 116024 Peoples R China DUT Artificial Intelligence Inst Dalian 116024 Peoples R China Dalian Maritime Univ Informat Sci & Technol Coll Dalian 116026 Peoples R China Beijing Inst Technol Sch Comp Sci & Technol Beijing 100081 Peoples R China

High-level synthesis (HLS) tools have been widely used in field-programmable gate array (FPGA) design to convert C/C++ code to hardware description language code. Unfortunately, HLS tools are susceptible to bugs, which can introduce serious vulnerabilities in FPGA products, leading to substantial losses. However, the characteristics of these bugs (e.g., root causes and bug-prone stages) have never been systematically studied, which significantly hinders developers from effectively handling HLS tool bugs. To this end, we conduct the first empirical study to uncover HLS tool bug characteristics. We collect 349 bugs of a widely used HLS tool, namely Bambu. We study the root causes, buggy stages, and bug fixes of these bugs by applying a multiperson collaboration method. Finally, 13 valuable findings are summarized. We find 14 categories of root causes in Bambu bugs;most bugs (22.1%) are caused by incorrect implementation of IR processing;the front end of Bambu is more bug-prone;to fix these bugs, 2.27 files and 80.19 lines of code need to be modified on average. We also present the insights gained from 95 Vitis HLS bugs. From these findings, we suggest that developers could use an on-the-fly code generator configuration method to generate suitable testing programs for HLS tool bug detection and apply large language models to assist in fixing HLS tool bugs.

关键词： Computer bugs Codes field programmable gate arrays Hardware design languages Resource management Hardware Software Logic gates Electronic mail Training Bug characteristics empirical study field-programmable gate array (FPGA) high-level synthesis (HLS) tool software bugs

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Sigma-Delta-Over-Fiber With WDM Serial Connection for Distributed MIMO

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JOURNAL OF LIGHTWAVE TECHNOLOGY 2025年第5期43卷 2151-2162页

作者： Olofsson, Frida Aabel, Lise Eriksson, Thomas Karlsson, Magnus Fager, Christian Chalmers Univ Technol Dept Microtechnol & Nanosci S-41296 Gothenburg Sweden Ericsson AB S-41756 Gothenburg Sweden Chalmers Univ Technol Dept Elect Engn S-41296 Gothenburg Sweden

In this paper, we investigate the first downlink with serially connected remote radio heads (RRHs) using sigma-delta-over-fiber (SDoF) for distributed MIMO (D-MIMO). Coarse wavelength-division multiplexing (CWDM) is used and one wavelength is assigned to each RRH. The serial connection architecture is implemented with passive off-the-shelf components. Specifically, signals are combined into one fiber cable by using an optical multiplexer (MUX) and signals are dropped at each RRH by using optical add-drop multiplexers (OADMS). The architecture implementation is scalable in terms of energy consumption and cost. We measure the sensitivity of SDoF towards the optical interference that occurs when several signals are combined into one fiber, and compare to alike measurements using analog radio-over-fiber (ARoF). We also address the challenge of different time-delays to each RRH, due to the different fiber lengths;we present a method for time-delay compensation, which makes the architecture using RRHs connected in series perform similarly to using RRHs connected in parallel. Finally, our measurements show that the architecture with serially connected RRHs can be used to serve two user equipment (UEs) simultaneously within the same time- and frequency resources, using multi-user MIMO technologies.

关键词： Optical fibers Optical amplifiers Wavelength division multiplexing Optical network units Optical modulation field programmable gate arrays Computer architecture Optical fiber sensors Optical fiber cables Stimulated emission Distributed multiple-input-multiple-output (MIMO) sigma-delta-over-fiber (SDoF) optical fronthaul wavelength-division multiplexing (WDM)

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SYNtzulu: A Tiny RISC-V-Controlled SNN Processor for Real-Time Sensor Data Analysis on Low-Power FPGAs

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第2期72卷 790-801页

作者： Leone, Gianluca Scrugli, Matteo Antonio Badas, Lorenzo Martis, Luca Raffo, Luigi Meloni, Paolo Univ Cagliari Dept Elect & Elect Engn DIEE I-09123 Cagliari Italy Politecn Torino Dept Control & Comp Engn DAUIN I-10129 Turin Italy

Spiking Neural Networks (SNNs) are energy-and performance-efficient tools that have been found to be very useful in AI applications at the edge. This paper introduces SYNtzulu, an SNN processing element designed to be used in low-cost and low-power FPGA devices for near-sensor data analysis. The system is equipped with a RISC-V subsystem responsible for controlling the input/output and setting runtime parameters, thus increasing its flexibility. We evaluated the system, which was implemented on a Lattice iCE40UP5K FPGA, in various use cases employing SNNs with accuracy comparable to the state-of-the-art. SYNtzulu dissipates a maximum power of 12.05 mW when performing SNN inference, which can be reduced to an average of just 1.45 mW through the use of dynamic power management.

关键词： field programmable gate arrays Encoding Neurons Computer architecture Real-time systems Hardware Synapses Spiking neural network (SNN) edge AI field programmable gate array (FPGA) energy efficiency RISC-V

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Robust and Efficient RTL to C Compiler Optimized for High-Level Synthesis

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2025年第2期44卷 559-567页

作者： Rashid, Imtiaz Schafer, Benjamin Carrion Univ Texas Dallas Dept Elect & Comp Engn Richardson TX 75080 USA

Designing hardware at the register transfer level (RTL) using low-level hardware description languages (HDLs) like Verilog or VHDL gives designers large degrees of controllability to create hardware architectures that will meet the given cost, power budget and performance requirements. The main problem with this approach is that the manually optimized architecture is fixed, which implies that future redesigns to, e.g., target other hardware platforms like field-programmable gate arrays (FPGAs) or newer technologies nodes might require the redesign and reverification of the RTL description. This is error prone and time consuming. To address this, in this work, we propose an RTL to C compiler that generates C code optimized for high-level synthesis (HLS) such that the redesign and reoptimization of new hardware design can be automated. HLS has multiple significant advantages over traditional RT-level design flows like being able to design and verify the behavioral description once and then retarget it for different hardware platforms and constraints by simply using a new technology library and synthesis constraints. Moreover, HLS allows to generate multiple functional equivalent design variants with unique tradeoffs like area, performance, and power from the same behavioral description by setting synthesis options in the form or pragmas (comments) to mainly control how to synthesize arrays (RAM or registers) and loops (unroll, partially unroll, no unroll, or pipeline). In order to leverage these advantages, in this work, we introduce an RTL to C compiler framework that we call MIRROR: maximizing the reusability of RTL through RTL to C Compiler and its new improved version MIRROR++ that is able to compile back to C different types of RTL descriptions, including pipelined circuits, finite state machines, and circuits that share functional units generating arrays and loops so that these can in turn be resynthesized (HLS) with different synthesis directives. Experimental

关键词： Codes Circuits Registers Mirrors field programmable gate arrays Very large scale integration System-on-chip Design space exploration (DSE) high-level synthesis (HLS) register transfer level (RTL) compiler

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URcon: Unified and Reconfigurable Control and Verification Platform for Multi-Mode Customized eDRAM and SRAM Macros

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IEEE ACCESS 2025年 13卷 34060-34069页

作者： Lee, Ho-Sung Jeon, Ik-Hyeon Lee, Jiwon Cheon, Hyeonjun Chae, Joo-Hyung Kwangwoon Univ Dept Elect & Commun Engn Seoul 01897 South Korea

With the rapid development of various technologies, processing large amounts of data has become essential. To address this trend, various high-density and high-performance memories have emerged. However, they employ different operation modes and architectures, necessitating the redesign of the control and verification platforms each time a new memory type is supported. To solve this problem, we propose a unified and reconfigurable platform to support the control and verification of various memories, each with different structures and operational modes. Some of the control and verification functions are integrated into the chip as a unified memory command controller (UMCC) to alleviate the limitations posed by the finite number of I/O pads. Other control and verification functions are implemented on a field-programmable gate array (FPGA) to support various memory operations and testing. Additionally, a software application has been used to manage the FPGA controller, enabling the flexible modification of input variables and enhancing the reconfigurability of the proposed platform. We designed prototype chips for customized 16-kb multi-mode embedded dynamic random-access memory (eDRAM) and static RAM (SRAM) macros using a 28-nm CMOS process. Their various operations and performances, such as data write, single- and multi-column data read, refresh, data retention time analysis, and power measurement, have been validated through the proposed platform. This platform can be extended and applied to verify other memories with minimal modifications.

关键词： Random access memory Computer architecture field programmable gate arrays Clocks Prototypes Microprocessors arrays Testing Memory architecture Power measurement Embedded dynamic random-access memory (eDRAM) finite state machine (FSM) multi-mode static random-access memory (SRAM) verification

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A Survey on Real-Time Object Detection on FPGAs

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IEEE ACCESS 2025年 13卷 38195-38238页

作者： Hozhabr, Seyed Hani Giorgi, Roberto Univ Siena Dept Informat Engn & Math I-53100 Siena Italy Consorzio Interuniv Nazl Informat I-00185 Rome Italy

This paper focuses on real-time object detection systems, analyzing existing field-programmable gate arrays (FPGAs) implementations that aim to achieve the best efficiency, performance, and accuracy at the same time. These three metrics are typically crucial for domains such as autonomous driving, and robotics. Fortunately, recent advancements in object detection models, particularly based on Convolutional Neural Networks (CNNs), have significantly improved object detection accuracy and speed. When these models are combined with FPGAs, it is possible to achieve even more power efficiency and more easily satisfy real-time constraints. FPGAs can deliver low latency and high throughput by leveraging true parallelism making them suitable platforms for developing real-time object detection systems. This paper reviews existing literature on FPGA-based real-time object detection, discussing commonly used algorithms, acceleration techniques, and optimization strategies. Evaluation metrics and typical datasets for assessing real-time systems are also examined. We have compared the performance of these implementations by using pixel throughput as a fair metric across different systems while processing video streams or images. Insights into state-of-the-art works, comparative analysis, challenges, and future research directions are provided to guide researchers interested in leveraging FPGA devices for real-time object detection applications.

关键词： Object detection Real-time systems field programmable gate arrays Detectors Surveys Accuracy Reviews Image edge detection Feature extraction Optimization Real-time object detection FPGA convolutional neural networks (CNNs) hardware accelerator

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Radar-aided reconfigurable intelligent surface for vehicular wireless communication

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OPTICS EXPRESS 2025年第5期33卷 11996-12011页

作者： Wang, Kun Tian, Yuze Yan, Tai Wang, Bo Shi, Xintong Xiong, Jie Yu, Wen Jin, Jing Lin, Hai Tang, Wenxuan Cent China Normal Univ Coll Phys Sci & Technol Wuhan 430079 Peoples R China South China Univ Technol Sch Future Technol Guangzhou 510641 Peoples R China Southeast Univ State Key Lab Millimeter Waves Nanjing 210096 Peoples R China Southeast Univ Inst Electromagnet Space Nanjing 210096 Peoples R China

In the intricate traffic environment of modern cities, challenges like insufficient wireless signal coverage and obstructed propagation links between base stations (BS) and vehicles are prevalent. Meanwhile, reconfigurable intelligent surface (RIS) offers what we believe to be a novel solution relying on its robust real-time control over electromagnetic (EM) waves, providing a new approach to achieving intelligent transportation and vehicle connectivity. In this paper, we propose a radar-aided intelligent wireless communication system for dynamic beam tracking. The system leverages frequency-modulated continuous wave (FMCW) radar to detect the location information of the surrounding vehicles, a pre-trained artificial neural network (ANN) combined with control boards to generate the voltage coding sequence of the desired deflection direction, and the dual-polarized RIS to realize intelligent beam tracking and wireless communication. We design a 3-bit dual-polarized RIS, consisting of 256 (16 x 16) independently controllable units, running at 3.5 GHz, and develop a high-speed control board to ensure real-time refresh of the voltage coding sequence. Comparative experiments are conducted in three different environments. The experiments consistently demonstrate that, with the assistance of the radar, the RIS can achieve dynamic beam tracking without manual intervention. The system can effectively improve wireless signal strength and communication stability, providing a new viable approach for the development of intelligent vehicular networking. (c) 2025 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement

关键词： Deep learning field programmable gate arrays Machine vision Neural networks Phase shift Visible light communications

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A High-Throughput FPGA Accelerator for Lightweight CNNs With Balanced Dataflow

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Zhao, Zhiyuan Chen, Yihao Feng, Pengcheng Li, Jixing Chen, Gang Shen, Rongxuan Lu, Huaxiang Univ Sci & Technol China Sch Microelect Hefei 230026 Peoples R China Chinese Acad Sci Inst Semicond Beijing 100083 Peoples R China Univ Chinese Acad Sci Inst Semicond Beijing 100089 Peoples R China

FPGA accelerators for lightweight convolutional neural networks (LWCNNs) have recently attracted significant attention. Most existing LWCNN accelerators focus on single-Computing-Engine (CE) architecture with local optimization. However, these designs typically suffer from high on-chip/off-chip memory overhead and low computational efficiency due to their layer-by-layer dataflow and unified resource mapping mechanisms. To tackle these issues, a novel multi-CE-based accelerator with balanced dataflow is proposed to efficiently accelerate LWCNN through memory-oriented and computing-oriented optimizations. Firstly, a streaming architecture with hybrid CEs is designed to minimize off-chip memory access while maintaining a low cost of on-chip buffer size. Secondly, a balanced dataflow strategy is introduced for streaming architectures to enhance computational efficiency by improving efficient resource mapping and mitigating data congestion. Furthermore, a resource-aware memory and parallelism allocation methodology is proposed, based on a performance model, to achieve better performance and scalability. The proposed accelerator is evaluated on Xilinx ZC706 platform using MobileNetV2 and ShuffleNetV2. Implementation results demonstrate that the proposed accelerator can save up to 68.3% of on-chip memory size with reduced off-chip memory access compared to the reference design. It achieves an impressive performance of up to 2092.4 FPS and a state-of-the-art MAC efficiency of up to 94.58%, while maintaining a high DSP utilization of 95%, thus significantly outperforming current LWCNN accelerators.

关键词： Frequency modulation Computer architecture System-on-chip Memory management field programmable gate arrays Computational modeling Computational efficiency Resource management Costs Bandwidth Lightweight convolutional neural network FPGA accelerator hybrid computing engines balanced dataflow resource allocation

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Real-Time sEMG Processing With Spiking Neural Networks on a Low-Power 5K-LUT FPGA

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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 2025年第1期19卷 68-81页

作者： Scrugli, Matteo Antonio Leone, Gianluca Busia, Paola Raffo, Luigi Meloni, Paolo Univ Cagliari DIEE I-09123 Cagliari Italy

The accurate modeling of hand movement based on the analysis of surface electromyographic (sEMG) signals offers exciting opportunities for the development of complex prosthetic devices and human-machine interfaces, moving from discrete gesture recognition, towards continuous movement tracking. In this study, we present two solutions for real-time sEMG processing, based on lightweight Spiking Neural Networks (SNNs) and efficiently implemented on a Lattice iCE40-UltraPlus FPGA, especially suitable for low-power applications. We first assess the performance in the discrete finger gesture recognition task, considering as a reference the NinaPro DB5 dataset, and demonstrating an accuracy of 83.17% in the classification of twelve different finger gestures. We also consider the more challenging problem of continuous finger force modeling, referencing the Hyser dataset for finger tracking during independent extension and contraction exercises. The assessment reveals a correlation of up to 0.875 with the ground-truth forces. Our systems take advantage of SNNs' inherent efficiency and, dissipating 11.31 mW in active mode, consume 44.6 mu J for a gesture recognition classification and 1.19 mu J for a force modeling inference. Considering dynamic power-consumption management and the introduction of idle periods, average power drops to 1.84 mW and 3.69 mW for these respective tasks.

关键词： Force Accuracy Real-time systems Gesture recognition field programmable gate arrays Computational modeling Power demand Spiking neural networks real-time monitoring healthcare

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Polarity-Focused Denoising for Event Cameras

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2025年第5期35卷 4370-4383页

作者： Shi, Chenyang Wei, Boyi Wang, Xiucheng Liu, Hanxiao Zhang, Yibo Li, Wenzhuo Song, Ningfang Jin, Jing Beihang Univ Sch Instrumentat & Optoelect Engn Beijing 100191 Peoples R China Tianmushan Lab Hangzhou 311115 Peoples R China Tsinghua Univ Dept Precis Instrument Beijing 100084 Peoples R China

Event cameras, which are highly sensitive to light intensity changes, often generate substantial noise during imaging. Existing denoising methods either lack the speed for real-time processing or struggle with dynamic scenes, mistakenly discarding valid events. To address these issues, we propose a novel dual-stage polarity-focused denoising (PFD) method that leverages the consistency of polarity and its changes within local pixel areas. Whether due to camera motion or dynamic scene changes, the polarity and its changes in triggered events are highly correlated with these movements, allowing for effective noise handling. We introduce two versions: PFD-A, which excels at reducing background activity (BA) noise, and PFD-B, which is designed to address both BA and flicker noise. Both versions are lightweight and computationally efficient. The experimental results show that PFD outperforms benchmark methods in terms of the SNR and ESR metrics, achieving state-of-the-art performance across various datasets. Additionally, we propose an FPGA implementation of PFD processes that handles each event in just 7 clock cycles, ensuring real-time performance. The codes are available at https://***/shicy17/PFD.

关键词： Noise reduction Noise Cameras Spatiotemporal phenomena Phase frequency detectors Real-time systems Circuits and systems Hardware 1/f noise field programmable gate arrays Event camera denoising method BA noise flicker noise

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