Circuits implemented in FPGAs have delays that are dominated by its programmable interconnect. This interconnect provides the ability to implement arbitrary connections. However, it contains both highly capacitive and...
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Circuits implemented in FPGAs have delays that are dominated by its programmable interconnect. This interconnect provides the ability to implement arbitrary connections. However, it contains both highly capacitive and resistive elements. The delay encountered by any connection depends strongly on the number of interconnect elements used to route the connection. These delays are only completely known after the place and route phase of the CAD flow. We propose the use of Clock Shifting optimization techniques to improve the clock frequency as a post place and route step. Clock Shifting Optimization is a technique first formalized in [4]. It is a cycle-stealing algorithm that allows one to reduce the critical path delay of a synchronous circuit by shifting the clock signals at each register. This technique allows late arriving signals to be sampled at a later point in time by intentionally introducing a skew on the clock input of the sampling register. Typical FPGAs contain a number of special purpose global clock networks that distribute clock signals to every register in the chip. Unused global clock lines in FPGAs can be used to distribute a finite set of clock skews to the entire circuit. We propose an efficient integer programming method to find the optimal circuit improvement for a finite set of clock skews. This technique is modified to consider inherent uncertainties present in the timing models. The uncertainty controls the aggressiveness of the optimizations as we must take great care in ensuring functionality for any range of possible timing characteristics. Our results confirm intuition that more aggressive speed optimizations can be performed as timing models become more accurate. We also show that providing 4 skewed versions of the nominal clock signal results in the best delay-area tradeoff. This result is evocative as it may suggest future FPGA architectures that contain greater numbers of global clock lines, as we tradeoff gains in speed for greater po
In this paper, dynamic reconfiguration and incremental rerouting techniques that are fault specific are presented. In this approach, the FPGA is initially routed without any extra interconnects for reconfiguration. Us...
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In this paper, dynamic reconfiguration and incremental rerouting techniques that are fault specific are presented. In this approach, the FPGA is initially routed without any extra interconnects for reconfiguration. Using the dynamic reconfiguration approach and Conv_T-DAG results in an average overhead of only 16% - an improvement of more than 50%. Over all circuits, the reconfiguration time per fault ranges from 16.8 to 72.9 secs. Simulation of smaller fault sets of one to four faults show very small track overheads ranging from 1.75% to 4.49% Conv_T-DAG can also be used for interconnect fault tolerance.
In this paper we evaluate the trade-offs between various low-leakage design techniques for field programmable gate arrays (FGPAs) in deep sub-micron technologies. Since multiplexers are widely used in FPGAs for implem...
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In this paper we evaluate the trade-offs between various low-leakage design techniques for field programmable gate arrays (FGPAs) in deep sub-micron technologies. Since multiplexers are widely used in FPGAs for implementing look up tables (LUTs) and connection and routing switches, several low-leakage implementations of pass transistor based multiplexers and routing switches are proposed and their design trade-offs are presented based on transistor-level simulation, physical design, and impact on overall system performance. We find that gate biasing, the use of redundant SRAM cells, and integration of multi-Vt technology are ideal for FPGAs, and they can reduce leakage current by 2X-4X compared to an implementation without any leakage reduction technique. For some of the potential low-leakage design techniques being evaluated in our study, the impact on chip area is very minimal to an increase of 15% - 30%.
FPGAs are characterized by a programmable interconnect that contains highly resistive and capacitive elements. While the configurable structure of the interconnect allows for the implementation of arbitrary circuits, ...
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ISBN:
(纸本)9781581133417
FPGAs are characterized by a programmable interconnect that contains highly resistive and capacitive elements. While the configurable structure of the interconnect allows for the implementation of arbitrary circuits, it has also become a significant bottleneck for high-speed circuits. Even if there are only a few signal paths that run along long stretches of interconnect, it is these paths that may determine the maximum operating frequency of the circuit. In this paper we investigate architectural features that could allow us to automatically pipeline the delay associated with long routes without an excessive area penalty. The goal is to reschedule circuit operations in such a way that a signal may use multiple clock cycles to traverse a long route, rather than requiring a single long clock period. This rescheduling would not effect the timing of the visible outputs (no latency is added to the overall system). Specifically, we analyze the effects of adding a small number of registered routing switches to an FPGA architecture with segmented routing resources. A parameterized FPGA architecture is studied where the percentage of registered routing switches is varied and the speed improvement and area penalty is evaluated. Novel algorithms are presented that allow a circuit to best utilize an architecture with a given percentage of registered switches. We believe that this is the first study that attempts to evauate the tradeoffs associated with switches required in FPGA architectures. Our experiments indicate that the architectural features introduced can produce significant speedup for high speed circuits without excessive area costs. We believe that these techniques will become increasingly important in the future as deep sub-micron process technologies shrink, and wire delays become even more significant.
Smart structural systems require the electronic control systems which are integrated into the structures to be small, light weight and power-efficient. The fieldprogrammablegate Array (FPGA) is a good platform to im...
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Smart structural systems require the electronic control systems which are integrated into the structures to be small, light weight and power-efficient. The fieldprogrammablegate Array (FPGA) is a good platform to implement such controllers. In our previous work FPGA-based digital controllers were built and tested on a cantilevered beam. In order to implement multivariable controllers, the hardware resources for FPGA-based architecture need to be further reduced. Distributed Arithmetic (DA) has long been proven to be a very efficient means to mechanize computations that are dominated by inner products involving constant multiplicand. The computational requirements of the smart structural controllers match this type very well. In this paper various DA structure controllers are designed and results are compared with multiply-and-accumulate (MAC) structure controllers. Single- and multi- variable controllers are implemented and tested on a cantilevered beam.
The proton induced SEU cross-sections of dynamic test designs implemented on Xilinx's Virtex-II and Spartan-3 FPGA's are presented. The cross-sections are used to estimate upset rates in the space radiation en...
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The proceedings contains 25 papers from the 1998 ACM/SIGDA International Symposium on field programmable gate arrays (FPGA). Topics discussed include: new FPGA architectures;technology mapping for FPGAs;multi-FPGA sys...
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The proceedings contains 25 papers from the 1998 ACM/SIGDA International Symposium on field programmable gate arrays (FPGA). Topics discussed include: new FPGA architectures;technology mapping for FPGAs;multi-FPGA systems & other reprogrammable architectures;partitioning and floor planning for FPGAs;fault detection and fault tolerance for FPGAs;fast computer aided design (CAD) tools for FPGAs;time multiplexed FPGAs;FPGAs with embedded memory;and programmable architectures with special features.
The proceddings contains 24 papers from International syposium on field programmable gate arrays. Some of the topics discussed include: timing driven placement for hierarchical programmable logic devices;performance d...
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The proceddings contains 24 papers from International syposium on field programmable gate arrays. Some of the topics discussed include: timing driven placement for hierarchical programmable logic devices;performance driven mapping for CPLD architectures;detailed routing arhitectures for embeembedded programmable logic IP cores;Microprocessor and applification specific integrated circuits;the effect of reconfigurable units in superscalar processors;run-time defect tolerance using Jbits;fpga implementation of a novel, fast motin estimation algorithm for real video compression.
The proceedings contain 64 papers from the ACM/SIGDA Thirteenth ACM International Symposium on field programmable gate arrays - FPGA 2005. The topics discussed include: the Stratix II logic and routing architecture;sk...
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The proceedings contain 64 papers from the ACM/SIGDA Thirteenth ACM International Symposium on field programmable gate arrays - FPGA 2005. The topics discussed include: the Stratix II logic and routing architecture;skew-programmable clock design for FPGA and skew-aware placement;sparse matrix-vector multiplication on FPGAs;power modeling and architecture evaluation for FPGA with novel circuits for VDD programmability;architecture adaptive routability-driven placement for FPGAs;energy-efficient FPGA interconnect architecture design;3D-Softchip: A novel 3D vertically integrated adaptive computing system;dynamic reconfiguration in FPGA-based SoC designs;and rapid prototyping of a test harness for forward error correcting codes.
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