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Design and Analysis of Area and Time Efficient Signed Square Architecture Using Nonconventional Method

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2025年第5期34卷

作者： Behera, Niharika Pradhan, Manoranjan Bhoi, Bandan Kumar Veer Surendra Sai Univ Technol Dept Elect & Telecommun Engn Burla India

Computing the square of any large signed number using conventional methods is challenging. Therefore, parallel and partial product generation while squaring signed numbers is complex and time-consuming. This paper suggests a very large scale integration design for an efficient signed square architecture using a nonconventional method. The square of a large magnitude signed number is reduced to a lower magnitude signed multiplication and an addition operation by the Yavadunam algorithm. The suggested method finds the deficit of the signed number from the adjacent base to perform the signed square operation. The proposed design is coded using Verilog hardware description language. The synthesis and simulation of this architecture are performed using Xilinx integrated synthesis environment 14.7 software. Furthermore, this architecture is implemented on the Virtex-4, spartan-3 and spartan-6 field programmable gate array devices. The design is also coded in cadence virtuoso centos version 5. Then, it is synthesized using 180nm and 90nm technology. The validation of the proposed architecture is examined using the performance parameters, such as path delay and area. The synthesis results show improvements in delay-area complexity compared to state-of-the-art architectures. The superiority of the proposed architecture is claimed based on performance comparisons with the previous square, multipliers and signed multiplier architectures.

关键词： Signed multiplier square architecture computer arithmetic field programmable gate array Yavadunam algorithm

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Windowed Sliding DFT Structure for Integrated Resistance and Capacitance Sensing With Wider Sensing Range

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷

作者： Tiwari, Ranjan Parasuraman, Sumathi Indian Inst Technol Roorkee Dept Elect Engn Roorkee 247667 Uttarakhand India

This article presents an integrated frequency domain measurement system for resistance (R) and capacitance (C) sensing. The proposed software and hardware combination achieves one of the largest R and C measurement ranges in the literature. A simple analog front-end circuit with a relaxation oscillator is designed to toggle between resistive and capacitive sensing. This oscillator accommodates the sensing variable (R or C) and converts this parameter change into the corresponding change in frequency of square wave output. A novel 2-in-1 Hanning and Blackman window-based FLL is designed to track the input square wave signal frequency. The proposed integrated measurement system contains two measuring units in a single system-on-chip, designed and implemented on an FPGA. Therefore, two types of measurements such as humidity measurement (C) and temperature measurement (R) are possible with a single instrument. Further, the windowed SDFT incorporation in a frequency-locked loop offers a wide capacitive and resistive measurement range. The range of R measurement is found to be ( 150 Omega -21.5 M Omega ) +/- 0.2% with an error of 0.023% +/- 0.53% while the same for C measurement is (3.4 pF-507.8 nF) +/- 0.5% and 0.038% +/- 0.53% . The proposed measurement system is also validated through the measurement of temperature from (30 degrees C to 90 degrees C) +/- 0.1% and humidity in the range of (40%RH-90%RH) +/- 4% separately.

关键词： Capacitance measurement field programmable gate array humidity sensor integrated measurement resistance measurement sensor interfacing circuit temperature sensor windowed sliding discrete Fourier transform (DFT) Capacitance measurement field programmable gate array humidity sensor integrated measurement resistance measurement sensor interfacing circuit temperature sensor windowed sliding discrete Fourier transform (DFT)

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Efficient Integer-Only-Inference of Gradient Boosting Decision Trees on Low-Power Devices

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第1期72卷 241-253页

作者： Alsharari, Majed Mai, Son T. Woods, Roger Reano, Carlos Queens Univ Belfast Sch Elect Elect Engn & Comp Sci Belfast BT7 1NN North Ireland Univ Valencia Dept Comp Sci Valencia 46010 Spain

There is increasingly interest in developing embedded machine learning hardware as it can offer better performance in terms of privacy, bandwidth efficiency, and scalability. Gradient-boosted decision trees (GBDT) represent a strong candidate as they employ less complex logic, but their efficient implementation in field programmable gate array (FPGA) needs to be explored in detail. In this paper, we propose sophisticated quantisation approaches to balance the dual goals of efficiency and performance. In particular, we introduce quantisation-aware training of GBDT for integer-only and binary arithmetic. Results are presented for implementations on a Zynq UltraScale + MPSoC FPGA with the best design using only 170 Look-up Tables and 233 flip-flops at a clock speed of 724 MHz. Implementations focused on network intrusion detection and jet substructure classification for large-scale physics experiments are explored. An order of magnitude less FPGA resources are used whilst offering extremely high throughput rate and maintaining accuracy. Code is available at https://***/malsharari/QATGBDT.

关键词： field programmable gate arrays Quantization (signal) Computational modeling Decision trees Accuracy Training Hardware Gradient-boosted decision trees embedded AI field programmable gate array quantization-aware training design framework

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StereoBit: Onboard Science Data Processing for Stereo Winds

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JOURNAL OF AEROSPACE INFORMATION SYSTEMS 2025年第5期22卷 325-335页

作者： Carr, James L. Wilson, Christopher M. Wilson, David T. Wu, Dong L. Madani, Houria CARR ASTRONAUT CORP Software Engn Div Sci Data Proc Branch Greenbelt MD 20770 USA NASA Goddard Space Flight Ctr Software Engn Div Sci Data Proc Branch Greenbelt MD 20771 USA

For future Earth decadal survey missions, the NASA Earth Science Technology Office has emphasized new technology concepts in NASA's New Observing Strategies, such as SmallSat solutions with distributed and constellation architectures and onboard processing capabilities. However, to enable advanced onboard computing, NASA requires more cutting-edge single-board computers to support complex algorithms and modern development flows. Traditionally, onboard processing is limited to fully radiation-hardened computer systems, typically technology generations behind consumer electronics and more restrictive with size, power efficiency, and cost. To address these concerns, NASA Goddard Space Flight Center has developed the SpaceCube family of processors that combines radiation-hardened and commercial-off-the-shelf components to produce high-performance, yet reliable systems that leverage modern design tools. To demonstrate capabilities of the next-generation SpaceCube v3.0 Mini processor, a flight design for StereoBit, a high-priority decadal survey Earth-science application, was implemented. StereoBit addresses the challenge of probing structure and dynamics of atmosphere in three dimensions using multi-angle, multiplatform stereo methods. This paper illustrates the design process of transforming StereoBit science-application C code to hardware description language for field programmable gate arrays using High-Level Synthesis. This paper then presents results of StereoBit on SpaceCube v3.0 Mini and discusses advantages of High-Level Synthesis over traditional flows for application design-space exploration.

关键词： Data Processing System field programmable gate array Geostationary Operational Environmental Satellite Earth Sciences Constellations NASA Computing and Informatics Planets Commercial off the Shelf Space Exploration and Technology

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Enhanced Real-Time Multiuser Uplink UWOC System Based on Hybrid Multiple Access and SGD-PID Power Control Algorithm

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JOURNAL OF LIGHTWAVE TECHNOLOGY 2025年第1期43卷 190-197页

作者： Li, Xiao Xia, Yu Gui, Liangqi Li, Han Lang, Liang Huazhong Univ Sci & Technol Sch Cyber Sci & Engn Res Ctr 6G Mobile Commun Wuhan 430074 Peoples R China Huazhong Univ Sci & Technol Sch Elect Informat & Commun Wuhan 430074 Peoples R China

Non-orthogonal multiple access (NOMA) has been widely regarded as the most promising technique for achieving high spectral efficiency in optical communication systems. However, the practical implementation of power domain NOMA faces challenges related to inter-user interference and decoding complexity, limiting its multiplexing capability to a pair of users. In this paper, we experimentally demonstrate a hybrid multiple access scheme in the four-user underwater wireless optical communication (UWOC) system. Specifically, power domain NOMA is employed to multiplex two users within a user pair (UP), while time division multiple access (TDMA) is utilized for each UP. To validate the efficacy of the hybrid multiple access technique, robust watertight transceivers are designed and implemented in a 10-m outdoor pool. A calculation method based on the channel condition is first introduced to retain the received power within a proper range when users in the UP are randomly positioned. Besides, an adaptive stochastic gradient descent-based proportional-integral-derivation (SGD-PID) algorithm is proposed for practical scenarios where determining the system and channel parameters is difficult. Experimental results show that the proposed adaptive power control schemes can effectively enhance system performance under different channel conditions experienced by users. The UWOC system achieves a data rate of 30 Mbps for each user, maintaining bit error rates (BERs) below forward error correction (FEC) threshold. The results highlight the remarkable potential of the hybrid multiple access scheme along with our proposed adaptive power control algorithm.

关键词： NOMA Time division multiple access Synchronization Power control Uplink Resource management Real-time systems field programmable gate array hybrid multiple access scheme non-orthogonal multiple access power control underwater wireless optical communication user pairing

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Remote Power Side- Channel Attacks on FPGAs

IEEE DESIGN & TEST

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IEEE DESIGN & TEST 2025年第1期42卷 13-19页

作者： Zhao, Mark Suh, G. Edward Stanford Univ Dept Elect Engn Stanford CA 94305 USA Nvidia Westford MA 01886 USA Cornell Univ Sch Elect & Comp Engn Ithaca NY 14853 USA

Editor's notes: Side-channel attacks, like those exploiting power and timing, are generally thought to require physical access to a system. This research challenges that idea by demonstrating how such attacks can be carried out on remote systems without physical access. It emphasizes the need to rethink how modern shared-FPGA systems are designed, prioritizing security as a core consideration. -Jeyavijayan Rajendran, Texas AM University, USA

关键词： field programmable gate arrays Logic Circuits Monitoring Power demand Logic gates Switches Channel models Side-channel attacks field programmable gate array ring oscillator power analysis attack side-channel attack system-on-chip

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Toward Universal Multiplexer Multiply-Accumulate Architecture in Stochastic Computing

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IEEE ACCESS 2025年 13卷 33874-33882页

作者： Lee, Yang Yang Halim, Zaini Abdul Ab Wahab, Mohd Nadhir Almohamad, Tarik Adnan Univ Sains Malaysia Sch Elect & Elect Engn Nibong Tebal 14300 Penang Malaysia Univ Sains Malaysia Sch Comp Sci Gelugor 11800 Penang Malaysia Karabuk Univ Fac Engn Dept Elect Elect Engn TR-78050 Karabuk Turkiye

Stochastic Computing (SC) has recently gained attraction due to its inherent error tolerance and extremely simple arithmetic hardware, making it particularly effective for accelerating modern applications such as neural networks on resource-constrained devices. Traditional SC architectures often adopt binary computing principles, relying on dedicated hardware, i.e. AND gates for multiplication and multiplexers (MUX) for addition. However, SC's mathematical foundation enables the fusion of complex operations into remarkably simple hardware. Several SC studies demonstrated the potential of MUX-based architectures to perform multiply-and-accumulate (MAC) operations, but existing designs face correlation complication, scaling problems, and limited application scope. This paper introduces an auxiliary logic block to address the complexity of MUX select inputs, significantly enhancing the scalability of MUX-based MAC operations. The proposed approach has been validated through SC image processing tasks, including grayscale conversion and Sobel edge detection, achieving up to 75% reduction in hardware resource utilization on field-programmable gate arrays (FPGAs) and up to 96% improvement in computational accuracy compared to traditional AND/XNOR-based SC multipliers.

关键词： Binary sequences Logic gates Hardware Arithmetic Correlation Logic Finite impulse response filters field programmable gate arrays Adders Accuracy Stochastic computing stochastic multiplier image processing field programmable gate array multiply-accumulate hardware

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Hardware-Efficient Polar Decoder for 5G Internet of Things Communication 9th

Hardware-Efficient Polar Decoder for 5G Internet of Things C...

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9th International Conference on Intelligent IoT as a Service

作者： Guo, Jing Li, Congduan Sun Yat Sen Univ Sch Elect & Commun Engn Shenzhen Peoples R China

ISBN: (纸本)9783031705069;9783031705076

Polar codes have aroused extensive attention due to their capacity-achieving property and low encoding and decoding complexity. With the increasing demand for real-time and high-quality applications, achieving low-latency communication in resource-constrained scenarios such as on Internet of Things (IoT) devices has become essential. This paper proposes a modified semi-parallel decoder for 5G IoT communication, with low decoding latency and high efficiency of hardware resources. 4-bit decoding algorithm and look-ahead approach are used in this work to reduce latency caused by conventional semi-parallel architecture. For a code length of N = 2(10), the proposed decoder improves latency by 48.64% and 75.19% than the conventional semi-parallel decoder and 2-bit decoder, separately. The significant improvement in hardware utilization rate of processing elements by 68.42% and 119.35% leads to high efficiency of hardware resources.

关键词： Internet of things Polar codes Wireless communication Hardware architecture field programmable gate array

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Line-by-Line Computation of Atmospheric Infrared Spectra With field programmable gate arrays

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IEEE JOURNAL OF SELECTED TOPICS IN APPLIED EARTH OBSERVATIONS AND REMOTE SENSING 2011年第3期4卷 701-709页

作者： Kohlert, Dieter Schreier, Franz Regensburg Univ Appl Sci Dept Elect Engn D-93053 Regensburg Germany DLR German Aerosp Ctr Remote Sensing Technol Inst D-82234 Wessling Germany

Radiative transfer modelling of high resolution infrared (or microwave) spectra still represents a major challenge for the processing of atmospheric remote sensing data despite significant advances in the numerical techniques utilized in line-by-line modelling by, e. g., optimized Voigt function algorithms or multigrid approaches. Special purpose computing hardware such as field programmable gate arrays (FPGAs) can be used to cope with the dramatic increase of data quality and quantity. Utilizing a highly optimized implementation of an uniform rational function approximation of the Voigt function, the molecular absorption cross section computation-representing the most compute intensive part of radiative transfer codes-has been realized on FPGA. Design and implementation of the FPGA coprocessor is presented along with first performance tests and an outlook for the ongoing further development.

关键词： Atmospheric radiative transfer field programmable gate array FPGA infrared microwave molecular absorption

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A VARIABLE-PRECISION SQUARE-ROOT IMPLEMENTATION FOR field-programmable gate arrayS

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JOURNAL OF SUPERCOMPUTING 1995年第3期9卷 315-336页

作者： LOUIE, ME ERCEGOVAC, MD Computer Science Department University of California Los Angeles

Applications requiring variable-precision arithmetic often rely on software implementations because custom hardware is either unavailable or too costly to build. By using the flexibility of the Xilinx XC4010 field programmable gate arrays, we present a hardware implementation of square root that is easily tailored to any desired precision. Our design consists of three types of modules: a control logic module, a data path module to extend the precision in 4-bit increments, and an interface module to span multiple chips. Our data path design avoids the common problem of large fan-out delay in the critical path. Cycle time is independent of precision, and operation latency can be independent of interchip communication delays.

关键词： SQUARE ROOT field programmable gate array FPGA VARIABLE PRECISION HIGH PRECISION

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